CN1694249A - 具有多层互连结构的半导体器件及其制造方法和设计方法 - Google Patents
具有多层互连结构的半导体器件及其制造方法和设计方法 Download PDFInfo
- Publication number
- CN1694249A CN1694249A CNA2004100851880A CN200410085188A CN1694249A CN 1694249 A CN1694249 A CN 1694249A CN A2004100851880 A CNA2004100851880 A CN A2004100851880A CN 200410085188 A CN200410085188 A CN 200410085188A CN 1694249 A CN1694249 A CN 1694249A
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- CN
- China
- Prior art keywords
- via plug
- interlayer dielectric
- interconnection pattern
- interconnection
- density
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 229910052814 silicon oxide Inorganic materials 0.000 description 2
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- 229910052905 tridymite Inorganic materials 0.000 description 2
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- 230000000694 effects Effects 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
Claims (21)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004137684A JP4703129B2 (ja) | 2004-05-06 | 2004-05-06 | 半導体装置およびその製造方法、設計方法 |
JP2004137684 | 2004-05-06 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1694249A true CN1694249A (zh) | 2005-11-09 |
CN100411164C CN100411164C (zh) | 2008-08-13 |
Family
ID=35238716
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004100851880A Expired - Lifetime CN100411164C (zh) | 2004-05-06 | 2004-09-30 | 具有多层互连结构的半导体器件及其制造方法和设计方法 |
Country Status (5)
Country | Link |
---|---|
US (2) | US7141881B2 (zh) |
JP (1) | JP4703129B2 (zh) |
KR (1) | KR100635297B1 (zh) |
CN (1) | CN100411164C (zh) |
TW (1) | TWI245361B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101079078B (zh) * | 2006-05-23 | 2011-08-03 | 瑞萨电子株式会社 | 设计半导体器件的方法 |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7271489B2 (en) | 2003-10-15 | 2007-09-18 | Megica Corporation | Post passivation interconnection schemes on top of the IC chips |
US7391107B2 (en) * | 2005-08-18 | 2008-06-24 | Infineon Technologies Ag | Signal routing on redistribution layer |
JP4731456B2 (ja) | 2006-12-19 | 2011-07-27 | 富士通セミコンダクター株式会社 | 半導体装置 |
JP5583332B2 (ja) * | 2008-06-06 | 2014-09-03 | ピーエスフォー ルクスコ エスエイアールエル | スルーホール配置装置およびスルーホール配置方法 |
US8647977B2 (en) * | 2011-08-17 | 2014-02-11 | Micron Technology, Inc. | Methods of forming interconnects |
US8575026B2 (en) * | 2011-11-03 | 2013-11-05 | Infineon Technologies Ag | Method of protecting sidewall surfaces of a semiconductor substrate |
US9177910B2 (en) | 2012-04-18 | 2015-11-03 | Micron Technology, Inc. | Interconnect structures for integrated circuits and their formation |
CN103543365B (zh) * | 2012-07-10 | 2015-12-16 | 中芯国际集成电路制造(上海)有限公司 | 互连结构最小间距的测试结构及测试方法 |
US9269747B2 (en) * | 2012-08-23 | 2016-02-23 | Micron Technology, Inc. | Self-aligned interconnection for integrated circuits |
KR20160139420A (ko) | 2015-05-27 | 2016-12-07 | 삼성전자주식회사 | 반도체 소자의 제조 방법 |
US9899297B1 (en) * | 2016-09-30 | 2018-02-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device having a through-silicon via and manufacturing method thereof |
US11424205B2 (en) * | 2018-06-29 | 2022-08-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor interconnect structure and method |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3102281B2 (ja) * | 1994-09-28 | 2000-10-23 | 川崎製鉄株式会社 | 半導体集積回路チップのレイアウト設計方法及び半導体集積回路チップ |
JP3890722B2 (ja) | 1998-02-16 | 2007-03-07 | ソニー株式会社 | 半導体装置の銅配線 |
US6265308B1 (en) * | 1998-11-30 | 2001-07-24 | International Business Machines Corporation | Slotted damascene lines for low resistive wiring lines for integrated circuit |
US6483176B2 (en) | 1999-12-22 | 2002-11-19 | Kabushiki Kaisha Toshiba | Semiconductor with multilayer wiring structure that offer high speed performance |
JP2001267323A (ja) | 2000-03-21 | 2001-09-28 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2001291720A (ja) * | 2000-04-05 | 2001-10-19 | Hitachi Ltd | 半導体集積回路装置および半導体集積回路装置の製造方法 |
JP4050876B2 (ja) * | 2001-03-28 | 2008-02-20 | 富士通株式会社 | 半導体集積回路装置とその製造方法 |
JP3561747B2 (ja) | 2001-03-30 | 2004-09-02 | ユーディナデバイス株式会社 | 高周波半導体装置の多層配線構造 |
JP2003142485A (ja) | 2001-11-01 | 2003-05-16 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
US6650010B2 (en) * | 2002-02-15 | 2003-11-18 | International Business Machines Corporation | Unique feature design enabling structural integrity for advanced low K semiconductor chips |
JP2004228111A (ja) * | 2003-01-20 | 2004-08-12 | Nec Electronics Corp | 半導体装置及びその製造方法 |
JP2005064226A (ja) * | 2003-08-12 | 2005-03-10 | Renesas Technology Corp | 配線構造 |
JP4230334B2 (ja) * | 2003-10-31 | 2009-02-25 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
-
2004
- 2004-05-06 JP JP2004137684A patent/JP4703129B2/ja not_active Expired - Fee Related
- 2004-09-14 US US10/939,594 patent/US7141881B2/en active Active
- 2004-09-15 TW TW093127888A patent/TWI245361B/zh active
- 2004-09-30 KR KR1020040077797A patent/KR100635297B1/ko active IP Right Grant
- 2004-09-30 CN CNB2004100851880A patent/CN100411164C/zh not_active Expired - Lifetime
-
2006
- 2006-10-23 US US11/584,645 patent/US7517792B2/en active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101079078B (zh) * | 2006-05-23 | 2011-08-03 | 瑞萨电子株式会社 | 设计半导体器件的方法 |
Also Published As
Publication number | Publication date |
---|---|
US7141881B2 (en) | 2006-11-28 |
US7517792B2 (en) | 2009-04-14 |
JP4703129B2 (ja) | 2011-06-15 |
US20070037382A1 (en) | 2007-02-15 |
KR100635297B1 (ko) | 2006-10-19 |
TWI245361B (en) | 2005-12-11 |
TW200537639A (en) | 2005-11-16 |
JP2005322689A (ja) | 2005-11-17 |
US20050248034A1 (en) | 2005-11-10 |
KR20050107277A (ko) | 2005-11-11 |
CN100411164C (zh) | 2008-08-13 |
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