CN1652316A - 制造多层封装件的方法 - Google Patents
制造多层封装件的方法 Download PDFInfo
- Publication number
- CN1652316A CN1652316A CNA2005100064466A CN200510006446A CN1652316A CN 1652316 A CN1652316 A CN 1652316A CN A2005100064466 A CNA2005100064466 A CN A2005100064466A CN 200510006446 A CN200510006446 A CN 200510006446A CN 1652316 A CN1652316 A CN 1652316A
- Authority
- CN
- China
- Prior art keywords
- electrode pad
- packaging part
- substrate
- projection
- solder flux
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 229910000679 solder Inorganic materials 0.000 claims abstract description 45
- 230000004907 flux Effects 0.000 claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 claims abstract description 21
- 238000004806 packaging method and process Methods 0.000 claims description 114
- 238000005476 soldering Methods 0.000 claims description 35
- 238000004377 microelectronic Methods 0.000 claims description 21
- 230000015572 biosynthetic process Effects 0.000 claims 4
- 238000007654 immersion Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 description 24
- 238000005538 encapsulation Methods 0.000 description 16
- 238000005520 cutting process Methods 0.000 description 6
- 238000007639 printing Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229920003023 plastic Polymers 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000013543 active substance Substances 0.000 description 1
- 238000002167 anodic stripping potentiometry Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 206010003664 atrial septal defect Diseases 0.000 description 1
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 235000010384 tocopherol Nutrition 0.000 description 1
- 235000019731 tricalcium phosphate Nutrition 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/035—Paste overlayer, i.e. conductive paste or solder paste over conductive layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10507—Involving several components
- H05K2201/10515—Stacked components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3485—Applying solder paste, slurry or powder
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
本发明公开一种制造多层封装件的方法,该方法确保易于敷设焊膏或焊剂。所述方法包括形成第一封装件,其包括在其上设置有突起的第一基板,以及形成第二封装件,其包括设置在其上对应于所述突起的第二基板,将焊膏或焊剂敷设在第一封装件的突起上,并且将第一封装件的所述突起和第二封装件的电极焊盘电连接。
Description
技术领域
本发明涉及一种制造多层封装件的方法,更特别地涉及这样一种制造多层封装件的方法,该方法确保易于敷设焊膏或焊剂以不受第二封装件的结构形状限制地互连第一封装件的突起和第二封装件的相应的电极焊盘。
背景技术
半导体装置阵列的紧密互连扩宽了它们的应用范围。在这点上,已经提出了使用以空间节约效应紧密排列的两个或多个半导体芯片的各种阵列结构。多芯片模块(MCM)技术已经得到发展,其中多个半导体芯片被安装在一个封装件上。被重叠起来的两个或多个封装件的多层封装件技术也得到了发展。
现在对通常的多层半导体封装件进行描述。通常,用于诸如球栅阵列(BGA)半导体封装件的半导体封装件的制造方法包括:将在其上具有多个半导体芯片的晶片切割成单个芯片(切割工序),将这些半导体芯片粘合(bonding)到预先准备好的印刷电路板(PCB)的预定区域(半导体芯片的粘合工序),使用导线将所述半导体芯片和PCB的所述预定区域互连(焊线工序),用封装装置封装所述半导体芯片从而保护所述半导体芯片不受外部环境的影响(成型工序),将用作所述PCB输入/输出端子的焊球连接到PCB的表面(焊球连接工序),以及将所述PCB切割成预定的半导体封装单元(单切(singulation)工序)。因此所制造的两个或多个半导体封装件的组件被称为多层封装件。
将半导体封装件安装在一个系统板表面上的表面安装技术被公开在韩国专利No.0398716中。根据所述公开的方法,在芯片电极上具有焊料突起的封装件被粘合到印有焊膏的电路板或中间基板上。但是,根据所述公开的专利,仅对焊料突起和焊膏的材料进行了描述,而对把所述焊膏敷设到所述电路板或所述封装件焊料突起的方法没有进行描述。
传统上,通过将焊剂或焊膏孔版印刷在形成于所述半导体基板或第二封装件上的电极焊盘上,从而将具有焊料突起的第一封装件安装在半导体基板或第二封装件上。但是,这种孔版印刷在封装件到封装件的安装中存在问题,不同于封装件到半导体基板的安装。
也就是说,在形成经由突起将多个封装件重叠的多层封装件的情况下,各封装件具有对应于在其上突起的电极焊盘,由于所述封装件的半导体基板的分开结构的存在,使得焊料或焊膏难于通过孔版印刷敷设到某个封装件上。
以下,将会通过结合附图1对制造多层封装件的传统方法进行说明。
图1是一剖视图,示出一种制造多层封装件的传统方法,其中两个封装件重叠在一起。参考图1,传统的多层封装件包括上部封装件160和下部封装件165。如上所述,所述上部封装件160通过执行晶片切割工序,半导体芯片粘合工序,焊线工序,成型工序,焊球连接工序以及单切工序而形成。所述下部封装件165除了第二微电子半导体芯片125利用翻转芯片135代替焊线130被安装在第二基板115上以外,与上部封装件160以相同的方式形成。
所述上部封装件160的第一突起150被电连接到相应的下部封装件165的电极焊盘157上。这里,焊剂175被预先施加到与第一突起150相连的所述下部封装件165的电极焊盘157上。所述焊剂175的敷设一般通过孔版印刷进行。但是,在下部封装件165中其上具有第二微电子半导体芯片125的情况下,如图1所示,在电极焊盘157上孔版印刷所述焊剂175可能是困难的。
在图1中,附图标记110指示第一基板,附图标记120指示第一微电子芯片,每个附图标记140和145指示封装装置,以及附图标记155指示第二突起。
发明内容
本发明提供一种制造多层封装件的方法,该方法确保易于敷设焊膏,以不受第二封装件的结构形状的限制地互连第一封装件的突起和第二封装件的相应电极焊盘。
本发明还提供一种制造多层封装件的方法,该方法确保易于敷设焊剂,以不受第二封装件的结构形状的限制地到互连第一封装件的突起和第二封装件的相应电极焊盘。
根据本发明的一个方面,一种制造多层封装件的方法包括:形成包括在其上设置有突起的第一基板的第一封装件,以及形成包括在其上设置有对应于所述突起的电极焊盘的第二基板的第二封装件,将焊剂敷设到第一封装件的突起上,并且将第一封装件的突起和第二封装件的电极焊盘电连接。
根据本发明的另一个方面,制造多层封装件的方法包括:形成包括在其上设置有突起的第一基板的第一封装件,以及形成包括在其上设置有对应于所述突起的电极焊盘的第二基板的第二封装件,将焊剂敷设到第一封装件的突起上,并且将第一封装件的所述突起和第二封装件的电极焊盘电连接。
还是根据本发明的另一个方面,制造多层封装件的方法包括:形成包括在其上设置有突起的第一基板的第一封装件,以及形成包括在其上设置有对应于所述突起的电极焊盘的第二基板的第二封装件,运用点蘸工具将焊膏敷设到第二封装件的电极焊盘上,并且将第一封装件的所述突起和第二封装件的电极焊盘电连接。
仍旧是根据本发明的另一个方面,制造多层封装件的方法包括:形成包括在其上设置有突起的第一基板的第一封装件,以及形成包括在其上设置有对应于所述突起的电极焊盘的第二基板的第二封装件,运用点蘸工具将焊剂敷设到第二封装件的电极焊盘上,并且将第一封装件的所述突起和第二封装件的电极焊盘电连接。
附图说明
本发明的上述和其它特点及优点将会结合附图并且结合对本发明的示例性实施例所做的详细说明而变得更加显而易见。
图1是一剖面图,示出一种制造多层封装件的传统方法,其中两个封装件重叠在一起;
图2A至2D是横截面图,它们顺序示出根据本发明实施例的多层封装件的制造过程;
图3是横截面图,示出根据本发明另一个实施例的多层封装件的制造方法;以及
图4A和4B是图3中部分A的放大的横截面图。
具体实施方式
本发明的优点和特点以及实现本发明的方法通过参考下面对优选实施例的说明以及附图更易于理解。但是,本发明可以用许多不同的方法来实现并且不应受到在这里所述的实施例的限制。然而,所提供的这些实施例将会是完整而全面的,并且会向本领域技术人员完全地传递本发明的概念,以及本发明仅由所附的权利要求书所限定。在整个说明书中,相同的附图标记指示相同的元件。
本发明的下列的实施例构成高频微型处理器,专用集成电路(ASIC)产品,或诸如动态随机访问存储器(DRAMs)以及静态随机访问存储器(SRAMs)的高速存储装置。这些装置的绝大多数具有多管脚输入/输出端口。对于多管脚结构,构成这些装置的绝大多数封装件可由塑料或陶瓷的管脚栅格阵列(PGA)封装、基板栅格阵列(LGA)封装、球状栅格阵列(BGA)封装、四边引出扁平封装或导线架封装形成。
在此可用的基板可以是印刷电路板(PCB)、陶瓷基板、金属基板或硅基板,该基板可以被用于诸如PGA封装、LGA封装、BGA封装、四边引出扁平封装以及导线架封装的封装件中。
通常,根据所使用的密封剂,封装可以被分类成树脂密封封装,薄膜封装(TCPs),玻璃密封封装以及金属密封封装。封装也可以根据安装技术被分类成插入技术类型(DIPs)和表面安装技术类型(SMT)。双列直插式封装(DIPs)和PGA封装是插入技术类型封装的代表。四边引出扁平封装(QFPs)、塑料引线芯片载体(PLCC)封装、陶瓷引线芯片载体(CLCC)封装以及BGA封装是SMT类型封装的代表。
对在单个封装件中包含一个微电子芯片来说很普通。但是,两个或多个芯片可以被包含在单个封装件中。后者被称为多芯片封装件(MCP)或多芯片模块(MCM)。通过重叠两个或多个封装件而获得的结构被称为多层封装件。这些具有多个芯片的封装件具有节约成本的效果和极佳的性能。它们增加存储能力以及加快处理速度,并且因此它们对存储模块,核心逻辑芯片组,微型处理器以及要求优秀电子性能、高板载密度和高表面安装量的微型控制系统来说是理想的封装件。因此,具有多芯片的所述封装件主要用于膝上电脑,便携式电脑,小笔记本电脑,电信(telecom),无线设备和PC卡。
将要被安装在封装件中的微电子芯片可以从许多半导体设备中选择。在这里使用的微电子芯片的优选示例包括逻辑和模拟器件,专用产品(ASPs)以及无线产品。在这种示例性应用中,一组芯片中的每个芯片都易于被使用。对于单个芯片来说,需要精确的设计和开发时间以实现芯片重叠的性能。而且,会出现诸如具有低早期收益的大型芯片和大型封装件占据大量昂贵基板空间的问题。出于这种考虑,本发明可以克服诸如无线通讯传呼器,硬盘驱动器,膝上电脑和医用设备的不断尺寸缩小应用的空间限制。
在这里所使用的微电子芯片的示例包括诸如DRAMs、SRAMs和闪存的高度集成的半导体存储芯片、MEMS(微型机电系统)芯片、光学电子芯片以及诸如CPU和数字式信号处理器(DSPs)的处理器。为了一个整体功能,所述微电子芯片可能是相同类型的电子芯片或不同的电子芯片。
出于方便起见,本发明的实施例以BGA封装件和PCB进行说明。
此后,将参考图2A到2D描述本发明的一个实施例。
参考图2A,第一封装件260使用通常的BGA封装制造工艺进行准备。
根据BGA封装制造工艺,具有其上多个第一微电子芯片的晶片被分成单个芯片(晶片切割工序)。这些第一微电子芯片被粘合到先前准备好的PCB的预定区域(微电子芯片粘合工序)。所述微电子芯片和所述PCB的预定区域使用传导性焊线(焊线工序)被互连起来。所述微电子芯片由所述密封材料封装起来以保护所述微电子芯片不受外部环境的影响(成型工序)。将用作所述PCB输入/输出端子的突起连接到PCB的表面(突起连接工序)。所述PCB被切割成预定封装单元(单切工序)。
参考图2A和2B,第一封装件260,其中形成在第一基板210的下表面上的第一突起250被设置在保持着焊剂或焊膏275的容器270的上方,并且随后第一封装件260的第一突起250的未端被浸在所述焊剂或所述焊膏275中。
所述焊剂275可以包括作为主要成分的树脂和诸如氯、氟和溴的微量卤素活性剂。所述焊剂275通过去掉污物或附着在将要被焊接的表面的氧化薄膜来促进焊接,从而减少在金属表面上的焊料成球倾向,从而使所述焊料良好地扩散在金属表面上,并且通过防止被焊接的物体和焊料表面不与氧气接触来防止表面的再次氧化。
所述焊膏275可以是在焊剂介质中均匀的焊料微粒的悬浮物。
包含着所述焊剂或焊膏275的容器270形成有预定深度的池277。所述容器270包括由金属或橡胶制成的刮刀(squeegee)(未示出)从而将焊剂或焊膏275推入到所述池277中。因此,所述焊剂或焊膏275可以在所述容器270中被填充成均匀厚度。
参考图2C,第一封装件260的第一突起250被设置在第二封装件265的相应的电极焊盘257之上。在此时,第一封装件260的位置可以由形成在第一突起250的下部表面上或第一封装件260的第一基板210上的识别标志(未示出)来确定。第二封装件265的位置可以由形成在所述电极焊盘257的上部表面上或第二封装件265的第二基板215上的识别标志来确定。
优选地,第二封装件265的电极焊盘257是由镀铜的金/镍或经过有机防护表面(OSP)处理的铜制成。更明确地,由焊料覆盖的所述电极焊盘257是再熔的。
优选地,第一封装件260和第二封装件265同时进行准备。在这个实施例中,使用反转芯片235代替在第一封装件260中使用的焊线230将第二微电子芯片225安装在第二基板215上。
参考图2D,当第一封装件260被安装在第二封装件265上时,从而使第一突起250被设置在所述电极焊盘257上,第一封装件260和第二封装件265通过再熔而电连接在一起。
如上所述,根据所示出的实施例,即使第二封装件265具有所述电极焊盘257以及在相同表面上的第二微电子芯片225,多层封装件也可以与第二封装件265的结构形状无关地轻易完成。
另外,对每一封装件,由于执行所述焊剂的敷设和设置不同于传统的孔版印刷方法,所以可以实现精确的粘合。
同时,第二微电子芯片225在第二封装件265的第二基底215上的存在经常需要第一封装件260和第二封装件265之间的预定间距,如图2D所示。在这种情况下,当所述电极焊盘257和第一突起250通过敷设在第一突起250上的焊膏275被粘合在一起时,第一封装件260和第二封装件265之间的所述间距可以按需调整。
下面将结合附图3,4A和4B对本发明的另一个实施例进行说明。图3是一剖面图,示出根据本发明另一个实施例的制造多层封装件的方法。图4A和4B是图3中部分A的放大横截面图。出于简化的目的,与先前实施例附图中所示元件具有相同功能的元件由相同的附图标记来标识,不再给出对其的解释。
图3中所示的实施例与先前实施例的不同之处仅在于焊剂或焊膏375的敷设。
参考图3,使用点蘸工具320将焊剂或焊膏375施加在第二封装件265的电极焊盘257上。所述点蘸工具320通常提供有多个面向所述电极焊盘257的针形销330,从而使焊剂或焊膏375可以被点在第二基板215的电极焊盘257上。所述点蘸工具320被电连接到一个控制器310从而一起被操作。所述控制器310控制所述点蘸工具320,从而在所述针形销330的端部被浸在填充于一个容器(未示出)中的焊剂或焊膏375中时,所述点蘸工具320被传送到第二基板215并且点蘸工具320的焊剂或焊膏375会被点到第二基板215的电极焊盘257上。这一步骤以后的下述步骤与先前所述实施例中所示的步骤相同。即,当第一封装件260被安装在第二封装件265上从而使第一突起250设置在所述电极焊盘257上时,第一封装件260和第二封装件265通过再熔而电连接在一起。
参考图4A和4B,所述针形销330被分成具有圆形封闭端的杆型针销330a和在其中具有空间340的圆筒型针销330b。相对于杆型针销330a,在所述容器(未示出)中的焊剂或焊膏375的吸取量由每个所述杆型针销330a的所述端部的直径所确定。相对于圆筒型针销330b,在所述容器(未示出)中的焊剂或焊膏375的吸取量由每个所述圆筒型针销330b的所述端部的所述空间340的直径所确定。
使用点蘸工具320的焊剂375在电极焊盘257上的敷设可使多层封装件的制造易于进行而与第二封装件265的结构形状无关。而且,当第一突起250被粘合到通过点蘸工具320在其上施加焊膏375的电极焊盘257时,第一封装件260和第二封装件265之间的空间可以按需调整。
虽然本发明已经通过参考这些实施例进行了说明,但是本领域技术人员将会认识到在不背离本发明的精神和范围的前提下,可以在形式和细节上做出多种改变。所述的实施例将在各个方面被认作是示例性的而不是限制性的。
从上述的说明中明显看出,根据本发明的制造多层封装件的方法可以确保焊膏或焊料的容易且精确的敷设,从而不受第二封装件结构形状的限制在第一封装件的突起和第二封装件的相应电极焊盘之间实现互连。
尽管已经通过参照其优选实施例对本发明进行了描述,可以理解的是本发明不受限于此。对于本领域技术人员来说,可以在上述说明中进行各种替换和修改。因此,所述这些替换和修改将被包括在所附的权利要求书中限制的本发明的保护范围内。
Claims (16)
1、一种制造多层封装件的方法,所述方法包括:
形成包括第一基板的第一封装件,在第一基板上设置有突起,以及形成包括第二基板的第二封装件,在第二基板上设置有对应于所述突起的电极焊盘;
将焊膏敷设在所述突起上,以及
电连接所述突起与所述电极焊盘。
2、根据权利要求1所述的方法,其中所述电极焊盘被安装在第二封装件的表面上,在第二封装件上形成有第二微电子芯片,并且所述电极焊盘被设置在所述第二基板的外边缘上。
3、根据权利要求1所述的方法,其中敷设所述焊膏包括将所述突起浸入在所述焊膏中达到一个基本均匀的厚度。
4、根据权利要求3所述的方法,其中使用刮刀将所述焊膏填充在容器的池内。
5、一种制造多层封装件的方法,所述方法包括:
形成包括第一基板的第一封装件,在第一基板上设置有突起,以及形成包括第二基板的第二封装件,在第二基板上设置有对应于所述突起的电极焊盘;
将焊剂敷设在所述突起上,以及
电连接所述突起与所述电极焊盘。
6、根据权利要求5所述的方法,其中所述电极焊盘被安装在第二封装件的表面上,在第二封装件上形成有第二微电子芯片,并且所述电极焊盘被设置在所述第二基板的外边缘上。
7、根据权利要求5所述的方法,其中敷设所述焊剂包括将所述突起浸入焊剂中到达一个基本均匀的厚度。
8、根据权利要求7所述的方法,其中使用刮刀将所述焊剂填充在容器的池内。
9、一种制造多层封装件的方法,所述方法包括:
形成包括第一基板的第一封装件,在第一基板上设置有突起,以及形成包括第二基板的第二封装件,在第二基板上设置有对应于所述突起的电极焊盘;
使用点蘸工具将焊膏敷设在所述电极焊盘上,以及
电连接所述突起与所述电极焊盘。
10、根据权利要求9所述的方法,其中所述电极焊盘被安装在所述第二封装件的表面上,在其上形成有第二微电子芯片,并且所述电极焊盘设置在第二基板的外边缘上。
11、根据权利要求9所述的方法,其中敷设所述焊膏包括在所述点蘸工具装载所述焊膏后在所述电极焊盘上敷设所述焊膏,并且所述点蘸工具是圆筒型点蘸工具。
12、根据权利要求9所述的方法,其中敷设所述焊膏包括在所述点蘸工具装载所述焊膏后在所述电极焊盘上敷设所述焊膏,并且所述点蘸工具是杆型点蘸工具。
13、一种制造多层封装件的方法,所述方法包括:
形成包括第一基板的第一封装件,在第一基板上设置有突起,以及形成包括第二基板的第二封装件,在第二基板上设置有对应于所述突起的电极焊盘;
使用点蘸工具将焊剂敷设在所述电极焊盘上,以及
将所述突起与所述电极焊盘电连接。
14、根据权利要求13所述的方法,其中所述电极焊盘被安装在所述第二封装件的表面上,在其上形成有第二微电子芯片,并且所述电极焊盘设置在第二基板的外边缘上。
15、根据权利要求13所述的方法,其中敷设所述焊剂包括在所述点蘸工具装载所述焊剂后在所述电极焊盘上敷设所述焊剂,并且所述点蘸工具是圆筒型的点蘸工具。
16、根据权利要求13所述的方法,其中敷设所述焊剂包括在所述点蘸工具装载所述焊剂后在所述电极焊盘上敷设所述焊剂,并且所述点蘸工具是杆型点蘸工具。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020040008062A KR100642746B1 (ko) | 2004-02-06 | 2004-02-06 | 멀티 스택 패키지의 제조방법 |
KR8062/2004 | 2004-02-06 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN1652316A true CN1652316A (zh) | 2005-08-10 |
Family
ID=34880242
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNA2005100064466A Pending CN1652316A (zh) | 2004-02-06 | 2005-02-01 | 制造多层封装件的方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US20050233567A1 (zh) |
JP (1) | JP2005223330A (zh) |
KR (1) | KR100642746B1 (zh) |
CN (1) | CN1652316A (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106033748A (zh) * | 2015-03-19 | 2016-10-19 | 何当豪 | 整合性电子构装方法 |
CN110311030A (zh) * | 2019-07-19 | 2019-10-08 | 厦门理工学院 | 一种实现全铜互连的led封装方法及led灯 |
CN113130430A (zh) * | 2021-04-16 | 2021-07-16 | 南通大学 | 一种适用于lga封装的焊点及包含其的系统级封装结构 |
CN115662946A (zh) * | 2022-11-03 | 2023-01-31 | 广东工业大学 | 一种超细节距全铜互连方法及超细节距全铜互连结构 |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090301760A1 (en) * | 2005-06-16 | 2009-12-10 | Masato Shimamura | Method of Soldering a Module Board |
US20070210433A1 (en) * | 2006-03-08 | 2007-09-13 | Rajesh Subraya | Integrated device having a plurality of chip arrangements and method for producing the same |
JP5005321B2 (ja) * | 2006-11-08 | 2012-08-22 | パナソニック株式会社 | 半導体装置 |
KR100817091B1 (ko) | 2007-03-02 | 2008-03-26 | 삼성전자주식회사 | 적층형 반도체 패키지 및 그 제조방법 |
US7994643B2 (en) | 2007-04-04 | 2011-08-09 | Samsung Electronics Co., Ltd. | Stack package, a method of manufacturing the stack package, and a digital device having the stack package |
JP4588046B2 (ja) * | 2007-05-31 | 2010-11-24 | 三洋電機株式会社 | 回路装置およびその製造方法 |
US7875988B2 (en) * | 2007-07-31 | 2011-01-25 | Seiko Epson Corporation | Substrate and manufacturing method of the same, and semiconductor device and manufacturing method of the same |
US20090039490A1 (en) * | 2007-08-08 | 2009-02-12 | Powertech Technology Inc. | Mounting assembly of semiconductor packages prevent soldering defects caused by substrate warpage |
US20090091009A1 (en) * | 2007-10-03 | 2009-04-09 | Corisis David J | Stackable integrated circuit package |
KR100985565B1 (ko) * | 2008-07-04 | 2010-10-05 | 삼성전기주식회사 | 시스템 인 패키지 모듈 및 이를 구비하는 휴대용 단말기 |
WO2010047006A1 (ja) | 2008-10-23 | 2010-04-29 | パナソニック株式会社 | 半導体装置およびその製造方法 |
US20100105168A1 (en) * | 2008-10-29 | 2010-04-29 | Freescale Semiconductor, Inc. | Microelecronic assembly and method for forming the same |
JP2013004738A (ja) * | 2011-06-16 | 2013-01-07 | Shinko Electric Ind Co Ltd | 配線基板の製造方法 |
KR101394203B1 (ko) * | 2011-12-29 | 2014-05-14 | 주식회사 네패스 | 적층형 반도체 패키지 및 그 제조 방법 |
KR101923535B1 (ko) | 2012-06-28 | 2018-12-03 | 삼성전자주식회사 | 패키지 온 패키지 장치 및 이의 제조 방법 |
US8889486B2 (en) * | 2012-09-05 | 2014-11-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for package on package structures |
JP2014167975A (ja) * | 2013-02-28 | 2014-09-11 | Toshiba Corp | 半導体製造装置及び半導体装置の製造方法 |
US10575393B1 (en) * | 2018-11-13 | 2020-02-25 | International Business Machines Corporation | Heat-shielding microcapsules for protecting temperature sensitive components |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5439162A (en) * | 1993-06-28 | 1995-08-08 | Motorola, Inc. | Direct chip attachment structure and method |
KR0139694B1 (ko) * | 1994-05-11 | 1998-06-01 | 문정환 | 솔더 볼을 이용한 반도체 패키지 및 그 제조방법 |
US5587342A (en) * | 1995-04-03 | 1996-12-24 | Motorola, Inc. | Method of forming an electrical interconnect |
JP3385872B2 (ja) * | 1995-12-25 | 2003-03-10 | 三菱電機株式会社 | はんだ供給法およびはんだ供給装置 |
US5933713A (en) * | 1998-04-06 | 1999-08-03 | Micron Technology, Inc. | Method of forming overmolded chip scale package and resulting product |
US6193143B1 (en) * | 1998-08-05 | 2001-02-27 | Matsushita Electric Industrial Co., Ltd. | Solder bump forming method and mounting apparatus and mounting method of solder ball |
JP3565047B2 (ja) * | 1998-10-07 | 2004-09-15 | 松下電器産業株式会社 | 半田バンプの形成方法および半田バンプの実装方法 |
US6228681B1 (en) * | 1999-03-10 | 2001-05-08 | Fry's Metals, Inc. | Flip chip having integral mask and underfill providing two-stage bump formation |
JP3239335B2 (ja) * | 1999-08-18 | 2001-12-17 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 電気的接続用構造体の形成方法およびはんだ転写用基板 |
JP3403677B2 (ja) * | 1999-09-06 | 2003-05-06 | マイクロ・テック株式会社 | 半田ボール形成方法 |
US6794202B2 (en) * | 2000-03-15 | 2004-09-21 | Tessera, Inc. | Assemblies for temporarily connecting microelectronic elements for testing and methods therefor |
JP3420203B2 (ja) * | 2000-10-27 | 2003-06-23 | Necエレクトロニクス株式会社 | ハンダバンプの形成方法 |
US6348401B1 (en) * | 2000-11-10 | 2002-02-19 | Siliconware Precision Industries Co., Ltd. | Method of fabricating solder bumps with high coplanarity for flip-chip application |
US6818545B2 (en) * | 2001-03-05 | 2004-11-16 | Megic Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
US6593220B1 (en) * | 2002-01-03 | 2003-07-15 | Taiwan Semiconductor Manufacturing Company | Elastomer plating mask sealed wafer level package method |
US6756294B1 (en) * | 2002-01-30 | 2004-06-29 | Taiwan Semiconductor Manufacturing Company | Method for improving bump reliability for flip chip devices |
TW531869B (en) * | 2002-02-27 | 2003-05-11 | Advanced Semiconductor Eng | Manufacturing process of lead-free soldering bump |
TW533521B (en) * | 2002-02-27 | 2003-05-21 | Advanced Semiconductor Eng | Solder ball process |
US6740577B2 (en) * | 2002-05-21 | 2004-05-25 | St Assembly Test Services Pte Ltd | Method of forming a small pitch torch bump for mounting high-performance flip-flop devices |
US7032807B2 (en) * | 2003-12-23 | 2006-04-25 | Texas Instruments Incorporated | Solder contact reworking using a flux plate and squeegee |
-
2004
- 2004-02-06 KR KR1020040008062A patent/KR100642746B1/ko not_active IP Right Cessation
-
2005
- 2005-02-01 JP JP2005025707A patent/JP2005223330A/ja not_active Withdrawn
- 2005-02-01 CN CNA2005100064466A patent/CN1652316A/zh active Pending
- 2005-02-07 US US11/053,599 patent/US20050233567A1/en not_active Abandoned
-
2008
- 2008-01-24 US US12/019,439 patent/US20080138934A1/en not_active Abandoned
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106033748A (zh) * | 2015-03-19 | 2016-10-19 | 何当豪 | 整合性电子构装方法 |
CN110311030A (zh) * | 2019-07-19 | 2019-10-08 | 厦门理工学院 | 一种实现全铜互连的led封装方法及led灯 |
CN113130430A (zh) * | 2021-04-16 | 2021-07-16 | 南通大学 | 一种适用于lga封装的焊点及包含其的系统级封装结构 |
CN115662946A (zh) * | 2022-11-03 | 2023-01-31 | 广东工业大学 | 一种超细节距全铜互连方法及超细节距全铜互连结构 |
Also Published As
Publication number | Publication date |
---|---|
JP2005223330A (ja) | 2005-08-18 |
KR20050079572A (ko) | 2005-08-10 |
US20080138934A1 (en) | 2008-06-12 |
US20050233567A1 (en) | 2005-10-20 |
KR100642746B1 (ko) | 2006-11-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1652316A (zh) | 制造多层封装件的方法 | |
US6660558B1 (en) | Semiconductor package with molded flash | |
US6545366B2 (en) | Multiple chip package semiconductor device | |
US9130064B2 (en) | Method for fabricating leadframe-based semiconductor package with connecting pads top and bottom surfaces of carrier | |
US5677575A (en) | Semiconductor package having semiconductor chip mounted on board in face-down relation | |
US20080111224A1 (en) | Multi stack package and method of fabricating the same | |
CN1914719A (zh) | 倒装晶片四方扁平无引脚封装及其方法 | |
CN102244012A (zh) | 半导体器件及其制造方法 | |
JP2003204015A (ja) | 半導体装置、半導体装置の製造方法、及びインターポーザ基板の製造方法 | |
CN1815726A (zh) | 电路板及其制造方法以及半导体封装及其制造方法 | |
US6335271B1 (en) | Method of forming semiconductor device bump electrodes | |
US6653219B2 (en) | Method of manufacturing bump electrodes and a method of manufacturing a semiconductor device | |
CN1855405A (zh) | 一种倒装芯片方法 | |
KR100324332B1 (ko) | 솔더 조인트 신뢰성을 향상시킨 비지에이 반도체 패키지및 그 제조 방법 | |
CN1767178A (zh) | 半导体载板及其制造方法与半导体封装组件 | |
KR100226335B1 (ko) | 플라스틱 성형회로 패키지 | |
CN101809740B (zh) | 电子部件安装构造体及其制造方法 | |
CN1848413A (zh) | 覆晶球格阵列封装构造中具有晶体配向(100)的应变硅晶圆 | |
WO2006091266A1 (en) | Method of making reinforced semiconductor package | |
KR101046392B1 (ko) | 반도체 패키지용 기판과, 이를 포함하는 반도체 패키지 및 이를 이용한 스택 패키지 | |
CN1154177C (zh) | 半导体封装及其制造方法 | |
CN100341124C (zh) | 芯片置入式封装制程 | |
CN1790693A (zh) | 倒装芯片及线接合半导体封装件 | |
CN1755906A (zh) | 适用集成电路及发光二极管的封装方法 | |
CN111162158B (zh) | 一种rgb芯片倒装封装结构及制备方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C12 | Rejection of a patent application after its publication | ||
RJ01 | Rejection of invention patent application after publication |