CN1755906A - 适用集成电路及发光二极管的封装方法 - Google Patents
适用集成电路及发光二极管的封装方法 Download PDFInfo
- Publication number
- CN1755906A CN1755906A CNA2004100802140A CN200410080214A CN1755906A CN 1755906 A CN1755906 A CN 1755906A CN A2004100802140 A CNA2004100802140 A CN A2004100802140A CN 200410080214 A CN200410080214 A CN 200410080214A CN 1755906 A CN1755906 A CN 1755906A
- Authority
- CN
- China
- Prior art keywords
- integrated circuit
- light emitter
- emitter diode
- suitable integrated
- seal method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Led Device Packages (AREA)
Abstract
Description
Claims (13)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNB2004100802140A CN100461354C (zh) | 2004-09-28 | 2004-09-28 | 适用集成电路及发光二极管的封装方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNB2004100802140A CN100461354C (zh) | 2004-09-28 | 2004-09-28 | 适用集成电路及发光二极管的封装方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1755906A true CN1755906A (zh) | 2006-04-05 |
CN100461354C CN100461354C (zh) | 2009-02-11 |
Family
ID=36689013
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004100802140A Expired - Fee Related CN100461354C (zh) | 2004-09-28 | 2004-09-28 | 适用集成电路及发光二极管的封装方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN100461354C (zh) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101599474B (zh) * | 2008-06-02 | 2011-04-13 | 相丰科技股份有限公司 | 集成电路模块及其制造方法 |
CN101567323B (zh) * | 2009-05-27 | 2012-07-25 | 深圳市蓝科电子有限公司 | 一种显示屏用三基色发光二极管的制造方法 |
CN105428495A (zh) * | 2014-09-02 | 2016-03-23 | 展晶科技(深圳)有限公司 | 发光二极管封装体及其制造方法 |
CN107342356A (zh) * | 2017-07-06 | 2017-11-10 | 庞绮琪 | 提高抗浪涌电流能力的led封装结构 |
WO2020133770A1 (zh) * | 2018-12-28 | 2020-07-02 | 武汉华星光电技术有限公司 | 背光模组及显示装置 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001338947A (ja) * | 2000-05-26 | 2001-12-07 | Nec Corp | フリップチップ型半導体装置及びその製造方法 |
JP4480108B2 (ja) * | 2000-06-02 | 2010-06-16 | 大日本印刷株式会社 | 半導体装置の作製方法 |
-
2004
- 2004-09-28 CN CNB2004100802140A patent/CN100461354C/zh not_active Expired - Fee Related
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101599474B (zh) * | 2008-06-02 | 2011-04-13 | 相丰科技股份有限公司 | 集成电路模块及其制造方法 |
CN101567323B (zh) * | 2009-05-27 | 2012-07-25 | 深圳市蓝科电子有限公司 | 一种显示屏用三基色发光二极管的制造方法 |
CN105428495A (zh) * | 2014-09-02 | 2016-03-23 | 展晶科技(深圳)有限公司 | 发光二极管封装体及其制造方法 |
CN107342356A (zh) * | 2017-07-06 | 2017-11-10 | 庞绮琪 | 提高抗浪涌电流能力的led封装结构 |
WO2020133770A1 (zh) * | 2018-12-28 | 2020-07-02 | 武汉华星光电技术有限公司 | 背光模组及显示装置 |
Also Published As
Publication number | Publication date |
---|---|
CN100461354C (zh) | 2009-02-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW546795B (en) | Multichip module and manufacturing method thereof | |
CN1658387A (zh) | 半导体装置及其制造方法 | |
US8860196B2 (en) | Semiconductor package and method of fabricating the same | |
CN1652316A (zh) | 制造多层封装件的方法 | |
CN1334602A (zh) | 半导体器件和封装方法 | |
US20110284997A1 (en) | Chip-Exposed Semiconductor Device and Its Packaging Method | |
CN1519928A (zh) | 半导体器件及其制造方法 | |
CN1945817A (zh) | 半导体器件及其制造方法 | |
CN101060087A (zh) | 电极及其制造方法,以及具有该电极的半导体器件 | |
CN1700458A (zh) | 具有第一和第二导电凸点的半导体封装及其制造方法 | |
KR20020062805A (ko) | 반도체 장치 및 그것을 이용하는 액정 모듈 | |
CN1832154A (zh) | 散热器及使用该散热器的封装体 | |
CN2838038Y (zh) | 半导体封装物 | |
CN1577827A (zh) | 半导体器件及其制造方法 | |
CN1855450A (zh) | 高散热性的半导体封装件及其制法 | |
CN1532930A (zh) | 半导体装置、电子设备及它们的制造方法,以及电子仪器 | |
CN1755906A (zh) | 适用集成电路及发光二极管的封装方法 | |
CN1228839C (zh) | 一种多晶粒封装结构 | |
CN1848413A (zh) | 覆晶球格阵列封装构造中具有晶体配向(100)的应变硅晶圆 | |
CN101047160A (zh) | 半导体连线封装结构及其与集成电路的连接方法 | |
CN1604310A (zh) | 半导体装置及其制造方法 | |
CN111162158B (zh) | 一种rgb芯片倒装封装结构及制备方法 | |
CN211507677U (zh) | 一种rgb芯片倒装封装结构 | |
CN2572564Y (zh) | 晶粒级封装结构 | |
CN2575844Y (zh) | 高散热效率的封装结构 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
ASS | Succession or assignment of patent right |
Owner name: XIANG FENG TECHNOLOGY CO. Free format text: FORMER OWNER: MUTUAL-TEK INDUSTRIES CO., LTD. Effective date: 20080822 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20080822 Address after: Taipei County of Taiwan Province Applicant after: Mutualpak Technology Co.,Ltd. Address before: Taipei County of Taiwan Province Applicant before: MUTUAL-TEK INDUSTRIES CO.,LTD. |
|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090211 |