CN100461354C - 适用集成电路及发光二极管的封装方法 - Google Patents

适用集成电路及发光二极管的封装方法 Download PDF

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CN100461354C
CN100461354C CNB2004100802140A CN200410080214A CN100461354C CN 100461354 C CN100461354 C CN 100461354C CN B2004100802140 A CNB2004100802140 A CN B2004100802140A CN 200410080214 A CN200410080214 A CN 200410080214A CN 100461354 C CN100461354 C CN 100461354C
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integrated circuit
metal substrate
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seal method
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CN1755906A (zh
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黄禄珍
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Mutual Pak Technology Co Ltd
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XIANGFENG SCIENCE AND TECHNOLOGY Co Ltd
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract

适用集成电路及发光二极管的封装方法，流程依次为提供一金属基板；蚀刻金属基板顶部以形成数个凹陷于金属基板上，金属基板未受蚀刻处形成一线路；使用一高分子介电材料填平该数个凹陷，形成数个金属凸块于该金属基板上的线路表面，涂布一金属结合剂于该数个金属凸块的各金属凸块上，在该数个金属凸块上设置一导电主体，在该导电主体外部密封上一封胶，及蚀刻该金属基板底部使该高分子介电材料露出，该金属基板底部形成数个底部接脚；在金属基板底部非接脚部分涂布一防焊油墨；测试线路。本发明可避免在IC圆片或发光二极管芯片上形成金属凸块的复杂工艺而达到降低成本的功效，并可广泛应用于各种IC组件导电主体的封装而提高封装方法的实用性。

Description

适用集成电路及发光二极管的封装方法
技术领域
本发明涉及一种适用集成电路及发光二极管的封装方法。
背景技术
今日的半导体技术已广泛应用于人们生活所遇到的各种电子设备之中，举凡个人计算机、移动电话及自动提款机等，皆包含有以半导体等技术所制造的电路板或其它电子组件。
请参阅图5及图6，为一般传统的半导体集成电路IC(Integrated Circuit)或发光二极管LED(Light Emitting Diode)的封装流程，其是在一金属导线架60、60a或铜箔基板上设置一芯片(晶片)70俗称装片或发光二极管芯片(二极管晶粒)70a，接着，在芯片70或芯片70a与导线架60、60a上的针脚61、61a或是铜箔基板上的焊点之间打上焊线21、21a，最后在芯片70或芯片70a与捍线21、21a的外部封上一层封胶72、72a，即完成封装程序。
请参阅图7至图9，关于集成电路的另一种封装方式为俗称的倒装封装，其流程为在一芯片(晶片)80表面形成数个金属凸块81，如图7所示；接着翻覆芯片80使其金属凸块81朝下而定位在一导线架或电路基板90或90a上相对应的数个针脚91或焊点上，最后在该芯片80的外部封上一层封胶95、95a。前述的倒装封装方式可以避免因打线而造成芯片电感、阻抗或其散热性的降低，且相对第一种封装方式可降低成本并提高合格率。但倒装封装方式仍具有如下的缺点：
1.金属凸块一般是以金或锡铅合金制造而成，其形成于芯片上的工艺冗长且复杂，一般为配合此项工艺，厂商必须额外另辟专业生产线且购置专用的工艺设备。
2.芯片是由硅圆片切割制造而成，其结构脆弱，故其上设置金属凸块时仍有损毁该芯片的可能性，某些类型的芯片更因为体积过小或厚度过薄而根本无法将金属凸块固定于其上，故现有倒装封装(覆晶封装)方式的实用性仍有不足。
发明内容
为了克服现有集成电路及发光二极管的封装方式的高成本及实用性差等缺点，本发明提供一种适用于集成电路及发光二极管的封装方法，其可避免在集成电路之上形成金属凸块的复杂工艺而达到降低成本的功效，并可广泛应用于各种集成电路及发光二极管的封装而提高封装工艺的实用性。
本发明解决其技术问题所采用的技术方案是：
一种适用集成电路及发光二极管的封装方法，其特征在于，包括以下流程：提供一金属基板；蚀刻该金属基板顶部以形成数个凹陷于该金属基板上，该金属基板未受蚀刻处则形成一线路；使用一高分子介电材料填平该数个凹陷；形成数个金属凸块于该金属基板上的该线路表面；涂布一金属结合剂于该数个金属凸块的各金属凸块上；在该数个金属凸块上设置一导电主体；在该导电主体外部密封上一封胶；蚀刻该金属基板底部使该高分子介电材料露出，该金属基板底部形成数个底部接脚；在该金属基板底部非接脚部分涂布一防焊油墨；以及对该线路进行测试。
前述的适用集成电路及发光二极管的封装方法，其中当所述导电主体设置于金属凸块上时，导电主体上的数个金属接点是分别相对应于各金属凸块上，接着在导电主体底部与金属基板顶部之间填充一底层封胶。
前述的适用集成电路及发光二极管的封装方法，其中导电主体为一芯片。
前述的适用集成电路及发光二极管的封装方法，其中导电主体为一发光二极管芯片，且该封胶为透明状。
前述的适用集成电路及发光二极管的封装方法，在形成底部接脚之后且在涂布该防焊油墨之前，在各底部接脚上涂布一镍或金层，接着在该金属基板底部的部分接脚处形成有一可避免逆电流或瞬间静电的线路保护电阻。
前述的适用集成电路及发光二极管的封装方法，其中金属凸块是以电镀方式形成于金属基板上。
前述的适用集成电路及发光二极管的封装方法，其中金属凸块是以印刷方式形成于金属基板上。
前述的适用集成电路及发光二极管的封装方法，其中金属结合剂为一银材料。
前述的适用集成电路及发光二极管的封装方法，其中金属结合剂为一银材料。
前述的适用集成电路及发光二极管的封装方法，其中金属结合剂为一锡材料。
前述的适用集成电路及发光二极管的封装方法，其中金属结合剂为一锡材料。
前述的适用集成电路及发光二极管的封装方法，其中在所述蚀刻该金属基板底部使该介电材料露出的步骤之后，还包含涂布一防焊油墨于该露出的介电材料上的步骤。
借由上述技术手段，本发明可避免在导电主体之上形成金属凸块的复杂工艺而达到降低成本的功效，并可广泛应用于各种导电主体的封装而提高封装方法的实用性。
本发明的封装方法可适用于各类集成电路或发光二极管的封装，且线路保护电阻能有效避免逆电流或瞬间静电而提高集成电路或发光二极管的寿命。
附图说明
下面结合附图和实施例对本发明进一步说明。
图1A～D为本发明的部分流程图。
图2E～F为本发明接续图1所示流程的部分流程图。
图3G～H为本发明接续图2所示流程的部分流程图。
图4为本发明完成各流程后的平面剖视图。
图5为现有集成电路封装的平面视图。
图6为现有发光二极管封装的平面视图。
图7为现有集成电路与金属凸块的平面视图。
图8为现有倒装型集成电路封装的平面视图。
图9为现有倒装型集成电路封装的平面示意图。
10  金属基板              101 接脚
11  高分子介电材料        12  金属凸块
13  金属结合剂            15  导电主体
151 金属接点              16  底层封胶
17  封胶                  18  镍或金
19  线路保护电阻          20  防焊油墨
60  导线架                60a 导线架
61  针脚                  61a 针脚
70  芯片                  70a 芯片
72  封胶                  72a 封胶
80  芯片                  81  金属凸块
90  导线架                90a 芯片
91  针脚
具体实施方式
请参阅图1，本发明一种适用于集成电路的封装方法包含有下列流程：
以一铜材料制成的金属基板10作为工艺基板(请参阅图1A所示)；
蚀刻该金属基板10顶部，该金属基板10上受蚀刻后的凹陷处以一高分子介电材料11填平，未受蚀刻处则形成线路(请参阅图1B所示)；
以电镀或印刷的方式，该金属基板10上线路表面形成数个金属凸块12(请参阅图1C所示)；
在各金属凸块12外涂布一以银浆或锡膏所制成的金属结合剂13(请参阅图1D所示)；
在金属凸块12上设置一可为芯片IC或发光二极管LED芯片的导电主体15，其中导电主体15上的数个金属接点151是分别相对应于各金属凸块21上，接着在导电主体15底部与金属基板10顶部之间填充一底层封胶16(Underfill)以增加导电主体15及金属基板10之间结构的稳固性(请参阅图2E所示)；
在该导电主体15外部密封上一封胶17，若该导电主体15为一发光二极管芯片时，则该封胶17须为透明状(请参阅图2F所示)；
蚀刻该金属基板10底部，该金属基板10底部形成数个底部接脚101(请参阅图3G所示)
在该金属基板10底部的接脚101上涂布一镍或金层18，接着在该金属基板10底部的部分接脚101处形成有一可避免逆电流或瞬间静电的线路保护电阻19，并接着在该金属基板10的非接脚101部分涂布一防焊油墨20(请参阅图3H所示)；
对线路进行测试。
前述适用集成电路的封装方法亦可适用于发光二极管的封装。
借由上述技术手段，本发明具有如下功效：
1.避免在集成电路或发光二极管之上形成金属凸块的复杂工艺，厂商不须额外开辟生产线或购置专用的工艺设备，这样可使集成电路或发光二极管封装成本降低。
2.本发明的封装方法因不须直接对集成电路或发光二极管芯片等导电主体实施可能伤害该导电主体的措施，故较脆弱的芯片或芯片结构也可利用本发明来进行封装流程，如此可达到于广泛应用于各类型集成电路或发光二极管的封装而提高封装方法的实用性。

Claims (11)

1.一种适用集成电路及发光二极管的封装方法，其特征在于，包括以下流程：
提供一金属基板；
蚀刻该金属基板顶部以形成数个凹陷于该金属基板上，该金属基板未受蚀刻处则形成一线路；
使用一高分子介电材料填平该数个凹陷；
形成数个金属凸块于该金属基板上的该线路表面；
涂布一金属结合剂于该数个金属凸块的各金属凸块上；
在该数个金属凸块上设置一导电主体；
在该导电主体外部密封上一封胶；及
蚀刻该金属基板底部使该高分子介电材料露出，该金属基板底部形成数个底部接脚；
在该金属基板底部非接脚部分涂布一防焊油墨；以及
对该线路进行测试。
2.根据权利要求1所述的适用集成电路及发光二极管的封装方法，其特征在于所述导电主体设置于金属凸块上时，导电主体上的数个金属接点是分别相对应于各金属凸块上，接着在导电主体底部与金属基板顶部之间填充一底层封胶。
3.根据权利要求2所述的适用集成电路及发光二极管的封装方法，其特征在于所述导电主体为一芯片。
4.根据权利要求2所述的适用集成电路及发光二极管的封装方法，其特征在于所述导电主体为一发光二极管芯片，且该封胶为透明状。
5.根据权利要求1到4中任一项所述的适用集成电路及发光二极管的封装方法，其特征在于在形成底部接脚之后且在涂布该防焊油墨之前，在各底部接脚上涂布一镍或金层，接着在该金属基板底部的部分接脚处形成有一可避免逆电流或瞬间静电的线路保护电阻。
6.根据权利要求5所述的适用集成电路及发光二极管的封装方法，其特征在于所述金属凸块是以电镀方式形成于金属基板上。
7.根据权利要求5所述的适用集成电路及发光二极管的封装方法，其特征在于所述金属凸块是以印刷方式形成于金属基板上。
8.根据权利要求6所述的适用集成电路及发光二极管的封装方法，其特征在于所述金属结合剂为一银材料。
9.根据权利要求7所述的适用集成电路及发光二极管的封装方法，其特征在于所述金属结合剂为一银材料。
10.根据权利要求6所述的适用集成电路及发光二极管的封装方法，其特征在于所述金属结合剂为一锡材料。
11.根据权利要求7所述的适用集成电路及发光二极管的封装方法，其特征在于所述金属结合剂为一锡材料。
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JP2001345336A (ja) * 2000-06-02 2001-12-14 Dainippon Printing Co Ltd 半導体装置の作製方法と、それに用いられる配線部材

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JP2001345336A (ja) * 2000-06-02 2001-12-14 Dainippon Printing Co Ltd 半導体装置の作製方法と、それに用いられる配線部材

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