CN102347300B - 芯片封装体及其制造方法 - Google Patents

芯片封装体及其制造方法 Download PDF

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Publication number
CN102347300B
CN102347300B CN201010597459.6A CN201010597459A CN102347300B CN 102347300 B CN102347300 B CN 102347300B CN 201010597459 A CN201010597459 A CN 201010597459A CN 102347300 B CN102347300 B CN 102347300B
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Prior art keywords
chip
coupling part
solder layer
width
welding disk
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Expired - Fee Related
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CN201010597459.6A
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CN102347300A (zh
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张国庆
郭武政
林孜翰
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XUMING PHOTOELECTRICITY Inc
VisEra Technologies Co Ltd
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XUMING PHOTOELECTRICITY Inc
VisEra Technologies Co Ltd
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Publication of CN102347300A publication Critical patent/CN102347300A/zh
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Abstract

本发明提供一种芯片封装体及其制造方法，芯片封装体包含基底以及设置在基底上的芯片，焊料层设置在基底与芯片之间，导电焊盘设置在焊料层与基底之间，其中导电焊盘包含第一部分设置在焊料层下，第二部分与第一部分隔开设置，以及连接部分设置在第一部分与第二部分之间，其中沿着第一方向，连接部分的宽度小于第一部分的宽度，第一方向垂直于第二方向，第二方向是由第一部分向连接部分延伸的方向。本发明能够避免焊料溢流，从而可提升芯片封装体的可靠度。

Description

芯片封装体及其制造方法
技术领域
本发明涉及一种芯片封装体，尤其涉及一种避免焊料溢流的芯片封装体的导电焊盘设计。
背景技术
在传统的芯片封装体中，芯片例如发光芯片，通常是经由焊料层，借由焊料回焊工艺焊接在金属焊盘上，金属焊盘的一部分会被焊料层覆盖，以与芯片焊接，并且金属焊盘还有一部分不会被焊料层及芯片覆盖。于焊料回焊工艺进行之前，在金属焊盘会被芯片覆盖的部分上设置焊料层。然而，在焊料回焊工艺进行之后，焊料层会从金属焊盘被芯片覆盖的部分溢流到金属焊盘未被芯片覆盖的部分上，在此情况下，介于芯片与金属焊盘之间的焊料层将会不足够用于将芯片焊接在金属焊盘上，因此，传统芯片封装体的可靠度会因为焊料溢流问题而降低。
因此，业界亟需一种可以克服上述问题的芯片封装体。
发明内容
为了解决上述问题，本发明提供一种芯片封装体，其经由导电焊盘的结构设计，避免焊料溢流问题发生，因此可提升芯片封装体的可靠度。
在一示范性实施例中，芯片封装体包括基底以及设置在基底之上的芯片，焊料层设置在芯片与基底之间，导电焊盘设置在焊料层与基底之间，其中导电焊盘包括第一部分设置在焊料层下，第二部分与第一部分隔开设置，以及连接部分设置在第一部分与第二部分之间，且其中沿着第一方向，连接部分的宽度小于第一部分的宽度，第一方向垂直于第二方向，第二方向是由第一部分向连接部分延伸的方向。
在一示范性实施例中，提供芯片封装体的制造方法，此方法包括在基底上形成导电焊盘，在导电焊盘上形成焊料层，以及在焊料层上提供芯片，此导电焊盘包括第一部分设置在焊料层之下，第二部分与第一部分隔开设置，第三部分与第一部分隔开，且与第二部分对向设置，以及连接部分设置在第一部分与第二部分之间，其中沿着第一方向，连接部分的宽度小于第一部分的宽度，第一方向垂直于第二方向，第二方向是由第一部分向连接部分延伸的方向。
依据上述实施例提供的芯片封装体，其经由导电焊盘的结构设计避免焊料溢流，因此可提升芯片封装体的可靠度。此外，本发明的芯片封装体可应用在具有导通孔在其中的基底上，因此可降低芯片封装体的尺寸。
为了让本发明的上述目的、特征、及优点能更明显易懂，以下配合附图，作详细说明如下。
附图说明
图1A-图1D图显示依据本发明的各种实施例，芯片封装体的导电焊盘的平面示意图。
图2显示依据本发明的一实施例，沿着图1A的剖面线2-2’的芯片封装体的剖面示意图。
图3显示依据本发明的一实施例，沿着图1D的剖面线3-3’的芯片封装体的剖面示意图。
图4显示依据本发明的一实施例，沿着图1D的剖面线4-4’的芯片封装体的剖面示意图。
图5A-图5E显示依据本发明的一实施例，制造芯片封装体的各阶段的剖面示意图。
上述附图中的附图标记说明如下：
100～基底；102～导通孔；104～阻挡膜；106～焊料层；108～贯穿孔；200～导电焊盘；210～导电焊盘的第一部分；220～导电焊盘的第二部分；230～导电焊盘的第三部分；240、241～导电焊盘的连接部分；300～芯片；302～上接触电极；304～导线。
具体实施方式
本发明的一示范性实施例提供一种芯片封装体的导电焊盘设计，以避免焊料溢流问题发生。图1A显示依据本发明的一实施例，芯片封装体的导电焊盘200的平面示意图。导电焊盘200设置在基底100上，其具有第一部分210设置在焊料层(未示出示出)下方；第二部分220与第一部分210隔开设置；第三部分230与第一部分210隔开，且与第二部分220对向设置；以及连接部分240设置在第一部分210与第二部分220之间。沿着第一方向Y，连接部分240的宽度W1小于第一部分210的宽度W2，第一方向Y垂直于第二方向X，第二方向X是由第一部分210向连接部分240延伸的方向。在一实施例中，连接部分240的宽度W1可介于约100μm至约200μm之间，并且第一部分210的宽度W2可介于约1000μm至约2000μm之间，连接部分240的宽度W1与第一部分210的宽度W2的比值可介于约1∶10到约1∶20之间。
参阅图2，其显示依据本发明的一实施例，沿着图1A的剖面线2-2’的芯片封装体的剖面示意图。导电焊盘200的第一部分210、第二部分220、第三部分230以及连接部分240(未示出)形成于基底100上，基底100可以是半导体基底、陶瓷基底或金属印刷电路板(metal printed circuit board；MPCB)。导电焊盘200可由金属形成，例如TiW、Cu、Ni或前述的组合。焊料层106设置在导电焊盘的第一部分210上，藉此将芯片300焊接至导电焊盘的第一部分210上。在一实施例中，焊料层106可由锡铜(Sn-Cu)合金形成。通常在焊料回焊工艺期间，焊料层106很容易溢流至金属焊盘上，然而，在本发明的实施例中，由于连接部分240的宽度W1小于第一部分210的宽度W2，在焊料回焊工艺期间，焊料层106很难溢流至连接部分240上。因此，于焊料回焊工艺进行之后，焊料层106被遏制在第一部分210内，而不会溢流至连接部分240与第二部分220上，此宽度较窄的连接部分240可有效地避免焊料层106发生溢流现象。
如图2所示，提供芯片300设置在焊料层106上方，于焊料回焊工艺之后，芯片300经由焊料层106焊接在导电焊盘的第一部分210上。芯片300可以是具有集成电路形成于其上的半导体芯片。在一实施例中，芯片300可以是发光二极管(light-emitting diode；LED)芯片，或者是齐纳二极管(Zenerdiode)芯片，其具有上接触电极302形成于芯片300的一侧，且经由导线304电性连接至导电焊盘的第三部分230。下接触电极(未示出)与上接触电极302对向形成，且设置在芯片300的底部。芯片300的下接触电极经由焊料层106、导电焊盘的第一部分210以及连接部分240，电性连接至导电焊盘的第二部分220。
在一实施例中，在焊料层106与导电焊盘的第一部分210之间可形成金属层(未示出)，此金属层可由Cu、Ni、Au或Ag形成，并且焊料层106可由Sn-Cu合金形成。因此，芯片300可经由在焊料层106与金属层之间的共晶接合(eutectic bonding)而接合在基底100上，藉此提升在金属层与Sn-Cu合金的焊料层106之间的界面接合强度。
在本发明的实施例中，芯片300可以形成在硅基底、蓝宝石基底(sapphiresubstrate)或金属基底，例如Cu基底上，芯片300例如为发光二极管(LED)芯片或齐纳(Zener)二极管芯片。在芯片300的基底与焊料层106之间可设置额外的金属层(未示出)，此额外的金属层可由Cu、Ni、Au或Ag形成，额外的金属层可增加LED芯片300的欧姆接触(ohmic contact)。此外，在额外的金属层与Sn-Cu合金的焊料层106之间的界面可得到较高的接合强度。
参阅图2，在此实施例中，芯片300以及导电焊盘200的第一部分210、第二部分220、第三部分230以及连接部分240(未示出)都设置在基底100上。在另一实施例中，于基底100内可形成空穴(cavity)(未示出)，并且芯片300以及导电焊盘200的第一部分210、第二部分220、第三部分230以及连接部分240可以设置在基底100的空穴内。
再参阅图1A，导电焊盘的第二部分210与第三部分230分别可具有一个或一个以上的导通孔(through vias)102形成于其上。导通孔102分别穿过导电焊盘的第二部分210与第三部分230，并且更进一步地穿过基底100，藉此在芯片300与外部电路(未示出)之间形成电性连接。
接着，参阅图1B，其显示依据本发明的一实施例，芯片封装体的导电焊盘200的平面示意图。图1B与图1A之间的差异在于形成阻挡膜(blockingfilm)104覆盖导电焊盘的连接部分240，并且阻挡膜104设置在导电焊盘的第一部分210与第二部分220之间。阻挡膜104可在焊料回焊工艺期间更进一步地遏制焊料层106的溢流问题，阻挡膜104可由有机或无机的绝缘材料形成，其中优选为无机绝缘材料。形成阻挡膜104的有机绝缘材料可以是干膜型光致抗蚀剂(dry film type photoresist)，干膜型光致抗蚀剂是一种用在光刻技术中形成精确图案的感光材料，并且提供绝佳的顺应性，让多层结构的薄层具有所需的厚度。形成阻挡膜104的无机绝缘材料可以是氧化硅(siliconoxides)、氮化硅(silicon nitrides)、氮氧化硅(silicon oxynitrides)或前述的组合。在一实施例中，阻挡膜104的厚度可为约3μm至约50μm之间，并且沿着方向Y，阻挡膜104的宽度W4小于或等于导电焊盘的第一部分210的宽度W2。
图1C显示依据本发明的一实施例，芯片封装体的导电焊盘200的平面示意图。图1C与图1A之间的差异在于导电焊盘的第一部分210与第二部分220之间设置两个连接部分240与241，虽然在图1C中仅显示两个连接部分240与241，但是在其他实施例中，于导电焊盘的第一部分210与第二部分220之间可设置两个以上的连接部分。第一连接部分240的宽度为W1，第二连接部分241的宽度为W3，其中宽度W1与宽度W3可以相同或不同。在一实施例中，宽度W1与宽度W3可介于约100μm至约200μm之间。
接着，参阅图1D，其显示依据本发明的一实施例，芯片封装体的导电焊盘200的平面示意图。图1D图与图1C之间的差异在于形成阻挡膜104覆盖连接部分240和241，并且阻挡膜104设置在导电焊盘200的第一部分210与第二部分220之间，在焊料回焊工艺期间，阻挡膜104会抑制焊料层106的溢流。阻挡膜104可由有机或无机的绝缘材料形成，其中优选为无机绝缘材料。形成阻挡膜104的有机绝缘材料可以是干膜型光致抗蚀剂，形成阻挡膜104的无机绝缘材料可以是氧化硅、氮化硅、氮氧化硅或前述的组合。在一实施例中，阻挡膜104的厚度可为约3μm至约50μm之间，并且沿着方向Y，阻挡膜104的宽度W4小于或等于导电焊盘的第一部分210的宽度W2。
参阅图3，其显示依据本发明的一实施例，沿着图1D的剖面线3-3’的芯片封装体的剖面示意图。如图3所示，阻挡膜104设置在导电焊盘200的第一部分210与第二部分220之间，沿着图1D的剖面线3-3’，在阻挡膜104下方无连接部分设置。在一实施例中，阻挡膜104大抵上与焊料层106齐平，藉此在焊料回焊工艺期间抑制焊料层106的溢流。沿着图1D的剖面线3-3’，阻挡膜104的厚度H1可为约3μm至约50μm之间。
参阅图4，其显示依据本发明的一实施例，沿着图1D的剖面线4-4’的芯片封装体的剖面示意图。如图4所示，阻挡膜104设置在第二连接部分241之上，并且介于导电焊盘200的第一部分210与第二部分220之间。在一实施例中，阻挡膜104大抵上与焊料层106齐平，藉此在焊料回焊工艺期间遏制焊料层106的溢流。沿着图1D的剖面线4-4’，在导电焊盘的第二连接部分241上的阻挡膜104的厚度H2可为约3μm至约50μm之间。
通常在焊料回焊工艺期间，焊料层106很容易溢流至金属焊盘上，然而，依据本发明的实施例，连接部分240和241以及/或阻挡膜104可以在焊料回焊工艺期间有效地抑制焊料层106的溢流现象。
图5A-图5E显示依据本发明的一实施例，沿着图1D的剖面线3-3’，制造图3的芯片封装体的各阶段剖面示意图。参阅图5A，首先提供基底100，例如为硅基底。然后借由溅镀工艺、物理气相沉积(physical vapor deposition；PVD)法或其他沉积方式在基底100上形成金属层(未示出)，金属层可由依序排列的TiW、Cu以及Ni层形成。在一实施例中，于形成金属层之前，可借由光刻与蚀刻工艺在基底100内形成空穴(未示出)，然后在基底100的空穴内形成金属层。接着，借由光刻与蚀刻工艺将金属层图案化，形成导电焊盘200的第一部分210、第二部分220、第三部分230以及连接部分240和241(在图5A-图5E中未示出)。
参阅图5B，形成贯穿孔(through holes)108分别穿过导电焊盘的第二部分220与第三部分230，并且更进一步地穿过基底100。然后，在贯穿孔108内填充导电材料，形成导通孔(through vias)102。
参阅图5C，在导电焊盘200的第一部分210与第二部分220之间形成阻挡膜104，并且阻挡膜104覆盖导电焊盘的连接部分240和241。在一实施例中，阻挡膜104可由有机绝缘材料形成，例如为干膜型光致抗蚀剂，其可借由光刻工艺或印刷工艺形成。在另一实施例中，阻挡膜104可由无机绝缘材料形成，例如为氧化硅、氮化硅或氮氧化硅，其可借由化学气相沉积(chemical vapor deposition；CVD)法、热氧化(thermal oxidation)工艺或其他沉积方式沉积，然后借由光刻与蚀刻工艺图案化。在一实施例中，由无机绝缘材料制成的阻挡膜104可借由印刷工艺形成。
参阅图5D，在导电焊盘的第一部分210上借由溅镀法、电子束蒸镀(e-gunevaporation)法或锡膏印刷(stencil printing)法形成焊料层106。在一实施例中，焊料层106可由Sn-Cu合金形成。从上视角度观之，焊料层106的尺寸大抵上与导电焊盘的第一部分210的尺寸相当。接着，在后续步骤中将LED芯片设置在焊料层106上，焊料层106和导电焊盘的第一部分210的位置与芯片300的位置相同。
参阅图5E，芯片300例如为LED芯片，其设置在焊料层106上。在一实施例中，LED芯片300可以是垂直式发光二极管(vertical typed LED)芯片，在LED芯片300的底部表面上具有下接触电极(未示出)，并且在LED芯片300的顶部表面上具有上接触电极302。上接触电极302可以是p型接触电极或n型接触电极，其具有与下接触电极相反的导电性。接着，形成导线304，电性连接LED芯片300的上接触电极302至导电焊盘的第三部分230，因此，LED芯片300的上接触电极302经由导电线304与导电焊盘的第三部分230电性连接至导通孔102，并且经由导通孔102更进一步地与外部电路电性连接。同时，LED芯片300的下接触电极经由焊料层106、导电焊盘的第一部分210、连接部分240和241以及第二部分220，电性连接至导通孔102，并且经由导通孔102更进一步地与外部电路电性连接。
然后，经由焊料层106并借由焊料回焊工艺，将LED芯片300焊接在导电焊盘的第一部分210上，与基底100接合在一起。在本发明的实施例中，由于连接部分240和241的宽度小于导电焊盘的第一部分210的宽度，因此在焊料回焊工艺期间可以阻止焊料层106溢流。另外，在导电焊盘的连接部分240和241之上，以及导电焊盘的第一部分210与第二部分220之间可以设置阻挡膜104，因此，在焊料回焊工艺期间可以更进一步地遏制焊料层106的溢流。
依据上述实施例提供芯片封装体，其经由导电焊盘的结构设计避免焊料溢流，因此可提升芯片封装体的可靠度。此外，本发明的芯片封装体可应用在具有导通孔在其中的基底上，因此可降低芯片封装体的尺寸。
虽然本发明已揭示优选实施例如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可做些许更动与润饰，因此本发明的保护范围当视所附的申请专利范围所界定的范围为准。

Claims (10)

1.一种芯片封装体，包括：
一焊料层，设置在一芯片与一基底之间；以及
一导电焊盘，设置在该焊料层与该基底之间，其中该导电焊盘包括一第一部分，设置在该焊料层之下；一第二部分，与该第一部分隔开设置；以及一连接部分和一额外的连接部分，设置在该第一部分与该第二部分之间，且其中沿着一第一方向，该连接部分的宽度小于该第一部分的宽度，且该额外的连接部分的宽度小于该第一部分的宽度，该第一方向垂直于一第二方向，该第二方向由该第一部分向该连接部分延伸。
2.如权利要求1所述的芯片封装体，其中该连接部分的宽度介于100μm至200μm之间。
3.如权利要求1所述的芯片封装体，还包括一阻挡膜，覆盖该连接部分和该额外连接部分，且设置在该第一部分与该第二部分之间，其中该阻挡膜的厚度介于3μm至50μm之间。
4.如权利要求3所述的芯片封装体，其中该阻挡膜的材料包括氧化硅、氮化硅、氮氧化硅或一干膜型光致抗蚀剂。
5.如权利要求1所述的芯片封装体，其中该芯片包括一发光二极管芯片或一齐纳二极管芯片，且该导电焊盘还包括一第三部分，与该第一部分隔开，且与该第二部分对向设置。
6.如权利要求5所述的芯片封装体，其中该芯片具有一下接触电极与一上接触电极，分别电性连接至该第二部分与该第三部分。
7.一种芯片封装体的制造方法，包括：
在一基底上形成一导电焊盘；
在该导电焊盘上形成一焊料层；以及
在该焊料层上提供一芯片，
其中该导电焊盘包括一第一部分，设置在该焊料层之下；一第二部分，与该第一部分隔开设置；一第三部分，与该第一部分隔开，且与该第二部分对向设置；以及一连接部分和一额外的连接部分，设置在该第一部分与该第二部分之间，且其中沿着一第一方向，该连接部分的宽度小于该第一部分的宽度，且该额外的连接部分的宽度小于该第一部分的宽度，该第一方向垂直于一第二方向，该第二方向由该第一部分向该连接部分延伸。
8.如权利要求7所述的芯片封装体的制造方法，还包括进行一焊料回焊工艺，将该芯片焊接在该基底上，其中在该焊料回焊工艺之后，该焊料层保持在该第一部分上。
9.如权利要求7所述的芯片封装体的制造方法，还包括形成一阻挡膜，覆盖该连接部分和该额外连接部分，其中该阻挡膜形成于该第一部分与该第二部分之间，该阻挡膜的材料包括氧化硅、氮化硅、氮氧化硅或一干膜型光致抗蚀剂，且形成该阻挡膜的步骤包括一光刻与蚀刻工艺或一印刷工艺。
10.如权利要求7所述的芯片封装体的制造方法，其中该芯片包括一发光二极管芯片或一齐纳二极管芯片，且该芯片具有一下接触电极与一上接触电极，分别电性连接至该第二部分与该第三部分。
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