CN1639853A - 电子电路设备和其生产方法 - Google Patents

电子电路设备和其生产方法 Download PDF

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Publication number
CN1639853A
CN1639853A CNA038056089A CN03805608A CN1639853A CN 1639853 A CN1639853 A CN 1639853A CN A038056089 A CNA038056089 A CN A038056089A CN 03805608 A CN03805608 A CN 03805608A CN 1639853 A CN1639853 A CN 1639853A
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China
Prior art keywords
electronic component
surface wiring
intermediate layer
wiring part
projection
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Pending
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CNA038056089A
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English (en)
Inventor
西條谨二
吉田一雄
大泽真司
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Toyo Kohan Co Ltd
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Toyo Kohan Co Ltd
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Publication date
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Publication of CN1639853A publication Critical patent/CN1639853A/zh
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    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
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Abstract

一种能够在电子元件芯片和连接多层衬底之间提供稳定的电连接并以高密度缩小的电子电路设备，以及其生产方法。电子元件芯片(1)和连接多层衬底(2)或者多个电子元件芯片在惰性气氛如氩或者还原气氛如氢中被加热，然后通过或不通过中间层(6)的中介来将彼此压焊在一起。或者它们的接合表面被活化，然后在室温或者加热条件下压焊，从而通过使用上面任何一种方法来直接地和冶金地接合它们，而生产出电子电路设备(40)。

Description

电子电路设备和其生产方法
技术领域
本发明涉及电子电路设备，特别地涉及以高密度缩小的设备和其生产方法。
背景技术
近年来，对于移动电话、数码相机、笔记本型电脑等来说，越来越多的努力被致力于使其缩小、变薄、变轻、廉价，来达到提高进一步的便携性的目的。因此，在用于这些设备和被安装了例如如多层衬底上的IC、电容器、电阻元件或者电感器的半导体的电子元件芯片的电子电路设备中，发展研究一直致力于除了缩小电子元件芯片之外如何以高密度连接要被安装的电子元件芯片，例如半导体芯片到多层衬底。
结果，一种倒装芯片安装方法，已经被作为一种实现高密度的安装方法而被实施，在该倒装芯片安装方法中电子元件芯片被面朝下直接连接以安装在多层衬底上。在倒装芯片安装中，提供给各电子元件芯片的连接电极通过电连接构件，如焊料或者金，与提供给在块中的多层衬底上的布线部分相连。
图3显示了在传统的电子电路设备中由倒装芯片安装方法连接的系统的一个例子的横截面示意图。如图1所显示，电子元件芯片1，包括电子元件10，在其中一侧上提供的电极11，和包括连接用的金或者焊料的在电极11上形成的凸起12。如图2所显示，连接多层衬底2，包括带有表面布线部分21和内部电路部分22的多层金属板3。并且电子元件芯片1的凸起12和连接多层衬底2的布线部分21通过焊球14相紧贴，它们当加热到一定的温度时被压紧，使焊料14熔化来通过电极11、凸起12、焊球14和连接多层衬底的布线部分21电连接电子元件芯片1和连接多层衬底2。随后，可热固化的密封树脂5从要被加热以固化的焊球14之间被注入。这样，如图3所显示，通过倒装芯片安装方法安装的电子电路设备40就可以获得了。
但是，这样倒装芯片安装的电子电路设备存在这样的缺点：由于在加热固化树脂的期间可固化树脂和由焊球构成的凸起之间巨大的热膨胀差异容易产生弯曲；或者当经受快速的温度变化或机械震动以产生接合断开时容易产生裂缝，在电子元件芯片与连接多层衬底的连接之间不能获得稳定的电连接。
在本发明中，一个目的是提供一种以高密度缩小的电子电路设备，它能够提供例如半导体芯片的电子元件芯片和多层衬底之间的稳定的电连接，以及还提供其生产方法。
发明内容
根据本发明权利要求1的电子电路设备是通过集成以下构成的电子电路设备：
电子元件芯片，它包括电子元件和在该电子元件的电极上形成的凸起；以及
连接多层衬底，它包括多层衬底和内部电路部分以及为多层衬底而形成并彼此电连接的表面布线部分，
所述集成是通过直接接合形成在电子元件的电极上的凸起到表面布线部分进行的。
另外，根据权利要求2的电子电路设备由通过集成以下构成的电子电路设备：
电子元件芯片，以及
连接多层衬底，它包含多层衬底、内部电路部分和为多层衬底而形成并彼此连接的表面布线部分，以及在表面布线部分上形成有凸起，
所述集成通过直接接合电子元件的电极到形成在表面布线部分上的凸起进行。
此外，根据权利要求3的电子电路设备是通过集成下列构成的电子电路设备：
带有中间层的电子元件芯片，它由包括电子元件的电子元件芯片、形成在该电子元件的电极上的凸起和中间层形成，而中间层则包含为衬底而将彼此电连接的布线部分，所述形成通过直接将中间层的衬底一侧上的表面布线部分和形成在该电子元件的电极上的凸起接合进行；以及
连接多层衬底，它包括多层衬底和内部电路部分以及为多层衬底而形成并彼此电连接的表面布线部分，
所述集成通过借助焊球将中间层的表面布线部分和多层衬底的表面布线部分接合起来。
此外，根据权利要求4的电子电路设备是通过集成下列构成的电子电路设备：
具有中间层的电子元件芯片，它由电子元件芯片和中间层形成，该中间层包括为衬底而彼此电连接的表面布线部分和形成在表面布线部分上的凸起，所述形成是通过直接将中间层的衬底一侧的表面布线部分上形成的凸起接合到电子元件的电极进行的；以及
连接多层衬底，它包括多层衬底和内部电路部分以及表面布线部分，该表面布线部分为多层衬底而形成并彼此电连接，
所述集成是通过借助焊球来将中间层的表面布线部分和多层衬底的表面布线部分接合进行的。
此外，根据权利要求5的电子电路设备是通过集成下列构成的电子电路设备：
第一电子元件芯片，它包括第一电子元件和形成在该第一电子元件的电极上的凸起；
具有为衬底而彼此电连接的表面布线部分的中间层；以及
第二电子元件芯片，它包括第二电子元件和形成在该第二电子元件的电极上的凸起，
所述集成是通过直接分别将第一电子元件的电极上的凸起和中间层的一侧的表面布线部分接合、以及将中间层另一侧的表面布线部分和第二电子元件的电极上的凸起接合进行的。
此外，根据权利要求6的电子电路设备是通过集成下列构成的电子电路设备：
第一电子元件芯片；
中间层，它包括为衬底而彼此电连接的表面布线部分和形成在表面布线部分上的凸起；以及
第二电子元件芯片，它包括第二电子元件和形成在该第二电子元件的电极上的凸起，
所述集成是通过直接分别将第一电子元件的电极和中间层一侧的表面布线部分上的凸起接合、以及中间层另一侧的表面布线部分和第二电子元件的电极上的凸起接合进行的。
此外，根据权利要求7的电子电路设备是通过集成下列构成的电子电路设备：
第一电子元件芯片；
中间层，它包括为衬底而彼此电连接的表面布线部分和形成在表面布线部分上的凸起；以及
第二电子元件芯片，
所述集成是通过直接分别将第一电子元件的电极和中间层一侧的表面布线部分上的凸起接合、以及中间层另一侧的表面布线部分上的凸起和第二电子元件的电极接合进行的。
此外，根据权利要求1到7任一项的电子电路设备，其特征在于：电子元件可以是半导体、电容器、电阻元件或电感器中的任何一个。
此外，根据权利要求1到7任一项的电子电路设备，其特征在于：凸起的外形是截锥体或者截金字塔形，其顶部直径或者顶部对角线的长度为凸起高度的10％或者以上。
根据本发明的权利要求10的电子电路设备的生产方法是其特征在于集成以下的电子电路设备的生产方法：
电子元件芯片，它包括电子元件和形成在该电子元件的电极上的凸起；以及
连接多层衬底，它包括多层衬底和内部电路部分，以及表面布线部分，该表面布线部分为多层衬底而形成并彼此电连接，
所述集成是通过直接将电子元件的电极上形成的凸起接合到表面布线部分进行的。
此外，根据本发明的权利要求11的电子电路设备的生产方法是其特征在于集成以下的电子电路设备的生产方法：
电子元件芯片；以及
连接多层衬底，它包括多层衬底、内部电路部分、表面布线部分，该表面布线部分为多层衬底而形成并将彼此电连接，以及在表面布线部分上形成有凸起，
所述集成是通过直接将电子元件的电极接合到表面布线部分上形成的凸起进行的。
此外，根据本发明的权利要求12的电子电路设备的生产方法是其特征在于集成以下的电子电路设备的生产方法：
具有中间层的电子元件芯片，它由包括电子元件的电子元件芯片、形成在该电子元件的电极上的凸起和中间层形成，该中间层具有带有彼此电连接的表面布线部分的衬底，所述形成是通过直接将中间层的衬底一侧的表面布线部分和电子元件的电极上形成的凸起接合进行的，
所述集成是通过借助焊球将中间层的表面布线部分和连接多层衬底接合进行的，该连接多层衬底包括多层衬底和内部电路部分以及表面布线部分，该表面布线部分为多层衬底而形成并将彼此电连接。
此外，根据本发明的权利要求13的电子电路设备的生产方法是其特征在于集成以下的电子电路设备的生产方法：
具有中间层的电子元件芯片，它由电子元件芯片和中间层形成，该中间层包括为衬底而将彼此电连接的表面布线部分和形成在表面布线部分上的凸起，所述形成是通过直接将中间层的衬底一侧的表面布线部分上形成的凸起和电子元件的电极接合进行的，
所述集成是通过借助焊球将中间层的表面布线部分和连接多层衬底接合进行的，该连接多层衬底包括多层衬底和内部电路部分以及表面布线部分，该表面布线部分为多层衬底而形成并将彼此电连接。
此外，根据本发明的权利要求14的电子电路设备的生产方法是其特征在于集成以下的电子电路设备的生产方法：
第一电子元件芯片，它包括第一电子元件和形成在该第一电子元件的电极上的凸起；
中间层，它包括为衬底而彼此电连接的表面布线部分；以及
第二电子元件芯片，它包括第二电子元件和形成在该第二电子元件的电极上的凸起，
所述集成是通过直接分别将第一电子元件的电极上的凸起和中间层一侧的表面布线部分接合、以及中间层另一侧的表面布线部分和第二电子元件的电极上的凸起接合进行的。
此外，根据本发明的权利要求15的电子电路设备的生产方法是其特征在于集成以下的电子电路设备的生产方法：
第一电子元件芯片；
中间层，它包括为衬底而将彼此电连接的表面布线部分和在表面布线部分上形成的凸起；以及
第二电子元件芯片，它包括第二电子元件和形成在该第二电子元件的电极上的凸起，
所述集成通过直接分别将第一电子元件的电极和中间层的表面布线部分的一侧上的凸起、以及中间层另一侧的表面布线部分和第二电子元件的电极上的凸起接合进行的。
此外，根据本发明的权利要求16的电子电路设备的生产方法是其特征在于集成以下的电子电路设备的生产方法：
第一电子元件芯片；
中间层，它包括为衬底而彼此电连接的表面布线部分和形成在表面布线部分上的凸起；以及
第二电子元件芯片，
所述集成是通过直接分别将第一电子元件的电极和中间层一侧的表面布线部分上的凸起、以及中间层另一侧的表面布线部分上的凸起和第二电子元件的电极接合进行的。
此外，根据权利要求10到16任一项的电子电路设备的生产方法，其特征在于：直接接合是通过在惰性气氛或者还原气氛中加热到200到300℃并且压焊执行的(权利要求17)。
或者，直接接合是通过对接合表面先进行活化处理后的压焊来执行的。
根据权利要求18的电子电路设备的生产方法，其特征在于：活化处理是通过在真空室中照射等离子、离子或者原子中任一种来执行的；或者
压焊是在室温或者加热的条件下执行的。
附图说明
图1的横截面示意图示出了电子元件芯片的例子，在该芯片上形成了传统的凸起；
图2的横截面示意图示出了连接多层衬底的例子；
图3的横截面示意图示出了传统电子电路设备的连接系统的例子；
图4的横截面示意图示出了根据本发明的电子元件芯片生产过程中一个步骤的状态的例子；
图5的横截面示意图示出了根据本发明的电子元件芯片的例子；
图6的横截面示意图示出了根据本发明的电子元件芯片另一个生产过程中一个步骤的状态的例子；
图7的横截面示意图示出了根据本发明的电子元件芯片另一个生产过程中另一个步骤的状态的例子；
图8的横截面示意图示出了根据本发明的电子元件芯片的另一个例子；
图9的横截面示意图示出了根据本发明的电子电路设备的连接系统的例子；
图10的横截面示意图示出了根据本发明的电子电路设备的连接系统的另一个例子；
图11的横截面示意图示出了根据本发明的电子电路设备的连接系统的另一个例子；以及
图12的横截面示意图示出了根据本发明的电子电路设备的凸起的横截面图。
具体实施方式
在下文中，本文将参考附图来对本发明进行详细的描述。
(实施例1)
图9是根据本发明权利要求1的电子电路设备的横截面示意图。在这幅图里，电子元件芯片1(例如，半导体芯片)，它可以是半导体、电容器、电阻元件或者电感器中任何的芯片，它包括电子元件10(例如，半导体，或者下列非半导体的电子元件)，该电子元件10可以是半导体、电容器、电阻元件或者电感器中的任何一个，它的一侧上提供有电极11和在电极11上形成凸起13。通过直接将电子元件芯片1和连接多层衬底2的表面布线部分21接合起来，就构成了电子电路设备40。直接接合连接多层衬底2的表面布线部分21和电子元件芯片1的凸起13可以通过用抗蚀剂构图的方法来形成，来使电极11部分单独露在外面，在电极11上通过采用电极电镀然后再清除掉抗蚀剂堆设一层来作为凸起13。它同样也可以按照图4和5所显示的方式来形成。也就是利用公开在PCT专利申请WO 99/58470的国家再次公开中的方法，其中将被固着的表面经受活化处理，然后对处理过的表面进行压焊，包含电极11和将构成导电层103的将被固着的铜箔表面的电子元件芯片1的表面，经受活化处理，活化处理以后是压焊的层叠来形成导电层103，随后利用蚀刻的方法将凸起13形成在电极11上。
直接接合连接多层衬底2的布线部分21的电子元件芯片1的凸起也可以通过如图6到8所显示的方式来形成。也就是通过利用汽化等方法将由铜构成的导电层103a形成在包含电极11的电子元件芯片1的表面上，接着通过利用众所周知的电镀法、汽化等形成其上由镍构成的蚀刻终止层103b。此外在其上用和描述由镍构成的蚀刻终止层103b一样的方式形成由铜构成的导电层103c。或者，在包含电极11的电子元件芯片1的表面上形成了由铜构成的导电层103a后，通过利用如公开在PCT专利申请WO 00/19533的国家再次公开中的金属箔的接合技术，形成蚀刻终止层103b的镍箔材料的接合表面以及形成导电层103c的铜箔材料先经受在真空室中的活化处理，在活化处理后通过对铜箔和镍箔进行层叠和冷轧来形成包覆板。然后，包覆板的镍表面和前述的提供在电子元件芯片1的导电层103a表面经受在真空室内的活化处理，活化处理后通过对包覆板和电子元件芯片1进行层叠和冷轧来形成三个层，这三个层包括由铜构成的导电层103a，由镍构成的蚀刻终止层103b和由铜构成的导电层103c。或者，通过利用如公开在PCT专利申请WO 00/19533的国家再次公开中的金属箔的接合技术，包括导电层103a、蚀刻终止层103b和导电层103c的三层包覆材料可能可以被形成，也就是通过利用如公开在PCT专利申请WO99/58470的国家再次公开中的压焊的方法来对电子元件芯片1的包含电极11的表面进行压焊和层叠。
通过选择蚀刻，该三层这样就获得了，同时也有可能将通过在脱离电极11的位置的表面布线部分103a和镍部分103b与电极电连接的凸起103c形成在电子元件芯片1上。
另一方面，关于连接多层衬底2，基底可能是通过利用传统的累积方法形成的。或者，它可能通过利用如公开在PCT专利申请WO00/05934的国家再次公开中的金属箔的接合技术和与电子元件芯片1的情形相类似方式的选择性蚀刻的方法来形成基底，在基底表面上提供绝缘层和表面布线部分21，然后电连接表面布线部分21和内部电路部分22来构成。随后，如图9所显示，连接多层衬底2的表面布线部分21直接紧贴和接合着电子元件芯片1的凸起13，来提供电子电路设备40。
关于接合方法，它们可以通过利用以下两种方法之一直接地和冶金地进行接合：
1)当加热到200到300℃时，在如氩的惰性气氛或者如氢的还原气氛中进行压焊；以及
2)接合表面预先通过照射原子活化，然后在室温或者当加热到200-300℃时压焊。活化处理也可能是通过等离子或离子照射。但是，由于等离子或离子照射可能使成分被破坏，原子照射为优选。随后，将密封树脂5填塞在凸起13周围。在这种连接中，虽然凸起13被提供给前述结构中的电子元件芯片1的电极11，但是该凸起也可能被提供给接合多层衬底2的表面布线部分21；或者凸起可能既被提供给电子元件芯片1的电极11，也被提供给连接多层衬底2的表面布线部分21。
(实施例2)
图10是一幅根据本发明权利要求3的电子电路设备的横截面示意图。在这幅图里，首先，凸起13以如实施例1中描述的同样的方式形成在的电子元件芯片1与中间层6直接接合。也就是中间层6包括由热阻树脂制成的衬底61，在其上形成了将彼此电连接起来的表面布线部分62。中间层6一侧的表面布线部分62紧贴着电子元件芯片1的凸起13，其中凸起13以如实施例1中描述的同样的方式直接接合来与中间层一起组成电子元件芯片7。
另一方面，连接多层衬底2以如图9所显示的相同的方式构成。连接多层衬底2的表面布线部分21通过焊球14和表面布线部分62紧贴，其中该表面布线部分62所处一侧和半导体芯片7的中间层6的连接多层衬底2相接合，其中中间层由前述的方式构成，而表面布线部分21被加热到能够熔化焊料14的温度，并受压来通过焊球14将中间层的表面布线部分62和连接多层衬底的表面布线部分21电连接起来。这样，电子电路设备40就可以被获得了。在这种连接中，在前述的结构中，虽然凸起13被提供给电子元件芯片1的电极11，但是凸起也可能被提供给中间层6的表面布线部分62；或者几个凸起可能既被提供给电极11，也被提供给中间层6的表面布线部分62。
在前述的实施例中显示了电子电路设备的例子，其中连接多层衬底直接或者通过中间层与电子元件芯片相连。但是可能有这样的情况：作为一种电子电路设备，它通过接合各个电子元件芯片构成(例如，半导体芯片和另一个半导体芯片，半导体芯片和电阻元件芯片，等等)构成。在下文中，本文将对这种通过接合各个电子元件芯片构成的电子电路设备的例子进行描述。
(实施例3)
图11是一幅根据本发明权利要求5的电子电路设备的横截面示意图。这幅图代表了通过中间层将各个电子元件芯片接合起来的情况。在这幅图里，首先，作为一个电子元件芯片的第一电子元件芯片1a的电极11a的凸起23a和提供给中间层6一侧的表面布线部分62a紧贴，其如实施例1描述的同样的方式直接接合。随后，作为另外电子元件芯片的第二电子元件芯片1b的电极11b的凸起23b和提供给中间层6的另一侧的表面布线部分62b紧贴，其如实施例1描述的同样的方式直接接合。这样，各个电子元件芯片可以通过其两侧的中间层电连接起来。另外，如图11所显示，中间层6的一侧的表面布线部分62b紧贴并接合着提供给连接多层衬底15的一侧的凸起24，来与连接多层衬底15电连接起来。随后，密封树脂16被从连接多层衬底15和第二电子元件芯片1b之间注入，并被加热来固化。提供给连接多层衬底15的另外一侧的表面布线部分(未显示)提供有凸起17，它使得有可能连接另一个多层衬底，电子元件芯片等(未显示)。这样，通过接合各电子元件芯片构成的电子电路设备40就可以被获得了。
在这种连接中，虽然接合的凸起23a被提供给了第一电子元件芯片1a的电极11a，但是该凸起也可能被提供给中间层6的表面布线部分62a，或者凸起可能既提供给第一电子元件芯片1a，也被提供给中间层6。此外，虽然接合的凸起23b被提供给了第二电子元件芯片1b的电极11b，但是该凸起也可能被提供给中间层6的表面布线部分62b，或者凸起可能既提供给第一电子元件芯片1b，也被提供给中间层6。此外，虽然接合的凸起24被提供给了接合的多层衬底15，但是该凸起也可能被提供给第二电子元件芯片1b的电极11b，或者几个凸起可能既提供给接合的多层衬底，也被提供给第二电子元件芯片1b。
在本发明中，在实施例1到3中形成的凸起的外形优选截去顶端的锥体或者截去顶端的金字塔形。如图12所显示，顶部的直径或者顶部的对角线的长度A是凸起高度的10％或者更多一些。这样，凸起顶部小的区域导致了在接合处每单位面积上承载了很大的压力，提高了接合的稳定性。本发明意图实现高密度下缩小尺寸的电子电路设备，并且凸起在最高处的高度为200μm。因此很难使凸起顶部直径或者顶部对角线的长度非常小，并且长度的较低限度是凸起高度的10％。
工业应用性
如实施例1到3中所显示，在根据本发明的电子电路设备中，电子元件芯片和连接多层衬底，或者各电子元件芯片都是直接地和冶金地通过或不通过中间层来接合以提供稳定的电接合。此外，凸起的外形是截锥体或者截金字塔形，顶部直径或者顶部对角线的长度为凸起高度的10％或者更多一些。这样，凸起顶部小的区域导致了在接合处每单位面积上承载很大的压力，提高了接合的稳定性。因此，根据本发明的电子电路设备具有特别完美的启动可靠性。

Claims (20)

1、一种电子电路设备，通过集成以下而构成：
电子元件芯片，它包括电子元件和形成在该电子元件的电极上的凸起；以及
连接多层衬底，它包括多层衬底和内部电路部分以及表面布线部分，表面布线部分为多层衬底而形成并彼此电连接，
所述集成是通过将形成在电子元件的电极上的凸起直接接合到表面布线部分进行的。
2、一种电子电路设备，通过集成以下而构成：
电子元件芯片；以及
连接多层衬底，它包括多层衬底、内部电路部分和表面布线部分，表面布线部分为多层衬底而形成并将彼此电连接，以及在表面布线部分上形成有凸起，
所述集成是通过将电子元件的电极直接接合到形成在表面布线部分上的凸起进行的。
3、一种电子电路设备，通过集成以下而构成：
具有中间层的电子元件芯片，它由包括电子元件和在电子元件的电极上形成的凸起的电子元件芯片以及包含表面布线部分的中间层形成，该表面布线部分为衬底彼此电连接，所述形成是通过直接将中间层的衬底一侧上的表面布线部分接合到在该电子元件的电极上形成的凸起进行的；以及
连接多层衬底，它包括多层衬底和内部电路部分以及表面布线部分，该表面布线部分为多层衬底而形成并彼此电连接，
所述集成是通过借助焊球来将中间层的表面布线部分接合到多层衬底的表面布线部分进行的。
4、一种电子电路设备，通过集成以下而构成：
具有中间层的电子元件芯片，它由电子元件芯片和中间层形成，该中间层包括为衬底而彼此电连接的表面布线部分和形成在表面布线部分上的凸起，所述形成是通过直接将中间层的衬底一侧的表面布线部分上形成的凸起接合到电子元件的电极进行的；以及
连接多层衬底，它包括多层衬底和内部电路部分以及表面布线部分，该表面布线部分为多层衬底而形成并将彼此电连接，
所述集成是通过借助焊球来将中间层的表面布线部分和多层衬底的表面布线部分接合进行的。
5、一种电子电路设备，通过集成以下而构成：
第一电子元件芯片，它包括第一电子元件和形成在该第一电子元件的电极上的凸起；
具有为衬底而彼此电连接的表面布线部分的中间层；以及
第二电子元件芯片，它包括第二电子元件和形成在该第二电子元件的电极上的凸起，
所述集成是通过直接分别将第一电子元件的电极上的凸起和中间层的一侧的表面布线部分接合、以及将中间层另一侧的表面布线部分和第二电子元件的电极上的凸起接合进行的。
6、一种电子电路设备，通过集成以下而构成：
第一电子元件芯片；
中间层，它包括为衬底而彼此电连接的表面布线部分和形成在表面布线部分上的凸起；以及
第二电子元件芯片，它包括第二电子元件和形成在该第二电子元件的电极上的凸起，
所述集成是通过直接分别将第一电子元件的电极和中间层一侧的表面布线部分上的凸起接合、以及中间层另一侧的表面布线部分和第二电子元件的电极上的凸起接合进行的。
7、一种电子电路设备，通过集成以下而构成：
第一电子元件芯片；
中间层，它包括为衬底而彼此电连接的表面布线部分和形成在表面布线部分上的凸起；以及
第二电子元件芯片，
所述集成是通过直接分别将第一电子元件的电极和中间层一侧的表面布线部分上的凸起接合、以及中间层另一侧的表面布线部分上的凸起和第二电子元件的电极接合进行的。
8、根据权利要求1到7任一项的电子电路设备，其中电子元件可以是半导体、电容器、电阻元件或电感器中的任何一个。
9、根据权利要求1到7任一项的电子电路设备，其特征在于：凸起的外形是截锥体或者截金字塔形，其顶部直径或者顶部对角线的长度为凸起高度的10％或者以上。
10、一种电子电路设备的生产方法，其特征在于集成：
电子元件芯片，它包括电子元件和形成在该电子元件的电极上的凸起；以及
连接多层衬底，它包括多层衬底和内部电路部分，以及表面布线部分，该表面布线部分为多层衬底而形成并彼此电连接，
所述集成是通过直接将电子元件的电极上形成的凸起接合到表面布线部分进行的。
11、一种电子电路设备的生产方法，其特征在于集成：
电子元件芯片；以及
连接多层衬底，它包括多层衬底、内部电路部分、表面布线部分，该表面布线部分为多层衬底而形成并将彼此电连接，以及在表面布线部分上形成有凸起，
所述集成是通过直接将电子元件的电极接合到表面布线部分上形成的凸起进行的。
12、一种电子电路设备的生产方法，其特征在于集成：
具有中间层的电子元件芯片，它由包括电子元件的电子元件芯片、形成在该电子元件的电极上的凸起和中间层形成，该中间层具有带有彼此电连接的表面布线部分的衬底，所述形成是通过直接将中间层的衬底一侧的表面布线部分和电子元件的电极上形成的凸起接合进行的，
所述集成是通过借助焊球将中间层的表面布线部分和连接多层衬底接合进行的，该连接多层衬底包括多层衬底和内部电路部分以及表面布线部分，该表面布线部分为多层衬底而形成并将彼此电连接。
13、一种电子电路设备的生产方法，其特征在于集成：
具有中间层的电子元件芯片，它由电子元件芯片和中间层形成，该中间层包括为衬底而将彼此电连接的表面布线部分和形成在表面布线部分上的凸起，所述形成是通过直接将中间层的衬底一侧的表面布线部分上形成的凸起和电子元件的电极接合进行的，
所述集成是通过借助焊球将中间层的表面布线部分和连接多层衬底接合进行的，该连接多层衬底包括多层衬底和内部电路部分以及表面布线部分，该表面布线部分为多层衬底而形成并将彼此电连接。
14、一种电子电路设备的生产方法，其特征在于集成：
第一电子元件芯片，它包括第一电子元件和形成在该第一电子元件的电极上的凸起；
中间层，它包括为衬底而彼此电连接的表面布线部分；以及
第二电子元件芯片，它包括第二电子元件和形成在该第二电子元件的电极上的凸起，
所述集成是通过直接分别将第一电子元件的电极上的凸起和中间层一侧的表面布线部分接合、以及中间层另一侧的表面布线部分和第二电子元件的电极上的凸起接合进行的。
15、一种电子电路设备的生产方法，其特征在于集成：
第一电子元件芯片；
中间层，它包括为衬底而彼此电连接的表面布线部分和在表面布线部分上形成的凸起；以及
第二电子元件芯片，它包括第二电子元件和形成在该第二电子元件的电极上的凸起，
所述集成通过直接分别将第一电子元件的电极和中间层的表面布线部分的一侧上的凸起、以及中间层另一侧的表面布线部分和第二电子元件的电极上的凸起接合进行的。
16、一种电子电路设备的生产方法，其特征在于集成：
第一电子元件芯片；
中间层，它包括为衬底而彼此电连接的表面布线部分和形成在表面布线部分上的凸起；以及
第二电子元件芯片，
所述集成是通过直接分别将第一电子元件的电极和中间层一侧的表面布线部分上的凸起接合、以及中间层另一侧的表面布线部分上的凸起和第二电子元件的电极接合进行的。
17、根据权利要求10到16任一项的电子电路设备的生产方法，其特征在于：直接接合是通过在惰性气氛或者还原气氛中加热到200到300℃并且压焊执行的。
18、根据权利要求10到16任一项的电子电路设备的生产方法，其特征在于：直接接合是通过对接合表面先进行活化处理后的压焊来执行的。
19、根据权利要求18的电子电路设备的生产方法，其特征在于：活化处理是通过在真空室中照射等离子、离子或者原子中任一种来执行的。
20、根据权利要求18的电子电路设备的生产方法，其特征在于：压焊是在室温或者加热的条件下执行的。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101473707B (zh) * 2006-06-22 2011-01-12 松下电器产业株式会社 电极结合方法和元件安装装置

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7265446B2 (en) * 2003-10-06 2007-09-04 Elpida Memory, Inc. Mounting structure for semiconductor parts and semiconductor device
JP2005340647A (ja) * 2004-05-28 2005-12-08 Nec Compound Semiconductor Devices Ltd インターポーザ基板、半導体パッケージ及び半導体装置並びにそれらの製造方法
WO2007013445A1 (ja) * 2005-07-25 2007-02-01 Tokyo Electron Limited 金属部材の処理方法及び金属部材の処理装置
JP2007036571A (ja) * 2005-07-26 2007-02-08 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
US8350382B2 (en) * 2007-09-21 2013-01-08 Infineon Technologies Ag Semiconductor device including electronic component coupled to a backside of a chip
US7927919B1 (en) * 2009-12-03 2011-04-19 Powertech Technology Inc. Semiconductor packaging method to save interposer
US9522514B2 (en) 2013-12-19 2016-12-20 Intel Corporation Substrate or panel with releasable core
US9434135B2 (en) 2013-12-19 2016-09-06 Intel Corporation Panel with releasable core
US9554472B2 (en) * 2013-12-19 2017-01-24 Intel Corporation Panel with releasable core
US9554468B2 (en) 2013-12-19 2017-01-24 Intel Corporation Panel with releasable core
US10062494B2 (en) 2014-11-03 2018-08-28 Qorvo Us, Inc. Apparatus with 3D inductors

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09181119A (ja) * 1995-12-27 1997-07-11 Matsushita Electron Corp 半導体装置およびその製造方法
JP3397045B2 (ja) * 1996-06-26 2003-04-14 カシオ計算機株式会社 半導体装置及びその製造方法
JPH10135217A (ja) * 1996-10-29 1998-05-22 Taiyo Yuden Co Ltd バンプ形成方法
JP3853979B2 (ja) * 1998-06-16 2006-12-06 日東電工株式会社 半導体装置の製法
JP2001060602A (ja) * 1999-08-23 2001-03-06 Fuji Electric Co Ltd フリップチップ実装構造及びその製造方法
JP2002064268A (ja) * 2000-08-18 2002-02-28 Toray Eng Co Ltd 実装方法および装置
JP3874062B2 (ja) * 2000-09-05 2007-01-31 セイコーエプソン株式会社 半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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