CN1551323A - 半导体器件的制造方法 - Google Patents

半导体器件的制造方法 Download PDF

Info

Publication number
CN1551323A
CN1551323A CNA2004100381372A CN200410038137A CN1551323A CN 1551323 A CN1551323 A CN 1551323A CN A2004100381372 A CNA2004100381372 A CN A2004100381372A CN 200410038137 A CN200410038137 A CN 200410038137A CN 1551323 A CN1551323 A CN 1551323A
Authority
CN
China
Prior art keywords
mentioned
resin
circuit board
chip
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2004100381372A
Other languages
English (en)
Inventor
桐谷美佳
Ҳ
田久真也
饭冢和宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of CN1551323A publication Critical patent/CN1551323A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05568Disposition the whole external layer protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525Means for applying energy, e.g. heating means
    • H01L2224/75251Means for applying energy, e.g. heating means in the lower part of the bonding apparatus, e.g. in the apparatus chuck
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757Means for aligning
    • H01L2224/75743Suction holding means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

一种半导体器件的制造方法,在一揽子地同时进行倒装芯片接合和树脂密封的工序中,在用超声波振动把在芯片上形成的突点电连到布线基板的焊盘上,同时,对上述芯片与上述布线基板之间进行树脂密封时,消除导通不良以提高可靠性。在用超声波振动把在芯片1上形成的突点3或焊盘倒装芯片接合到布线基板10的焊盘4或焊盘之上的突点上,同时,在上述芯片与上述布线基板之间形成树脂密封体时,在硬化前的低粘度区域中使突点3贯通树脂密封用树脂5。采用在使突点从密封用树脂贯通后再连接到焊盘上的办法,就可以充分地确保其连接性。

Description

半导体器件的制造方法
技术领域
本发明涉及在半导体芯片(以下,叫做芯片)倒装连接到布线基板上的类型的半导体器件中,一揽子地进行倒装芯片接合和树脂密封的半导体器件的制造方法。
背景技术
以往,对于半导体器件的制造方法,人们知道如下那样的工序。
首先,在硅等的晶片上用众所周知的工艺形成半导体元件。其次,在已形成了半导体元件的晶片的主表面上形成电连接到该半导体元件上的突点电极(以下,叫做突点)。其次,在把表面保护用带粘贴到晶片的主表面上之后对背面进行研削使晶片薄厚度化。然后,把划片带粘贴到薄厚度化后的晶片的元件形成面(主表面)上,采用用金刚石划片刀或激光划片刀等从背面一侧划片(完全切断划片)的办法使之芯片化。其次,用吸附工具(筒夹)吸附各芯片的背面进行拾取。在与此并行地把树脂密封用树脂粘贴到布线基板上之后(树脂密封用树脂,也可以预先粘贴到芯片上),采用把芯片粘贴到已粘贴上该树脂的布线基板上进行倒装芯片接合和树脂密封的办法进行装配。
以往,在在把半导体芯片倒装芯片接合到布线基板上的同时对芯片和布线基板间进行树脂密封的类型的半导体器件中,大多利用以上那样的制造工序。在把半导体芯片倒装芯片接合到布线基板上的同时对芯片和布线基板间进行树脂密封的工序之一,通常,先采用把突点夹在中间加热布线基板的连接电极(以下,也叫做焊盘或焊盘电极)和芯片的焊盘的办法把两者连接起来,然后,采用向芯片和布线基板间填充树脂的办法形成树脂密封体。在该情况下,也可以预先把突点安装在芯片上。或者,也可以预先安装到布线基板上。此外,还可以把突点安装到布线基板和芯片这双方上。在该情况下,要采用使分别安装的突点一体化的办法变成为1个突点。
然后,为了简化工序,有在倒装芯片接合之前把树脂密封用树脂放置在芯片与布线基板间的方法。使得把膏状或薄膜状的树脂夹在中间那样地使已安装到芯片(或布线基板)上的突点与布线基板(或芯片)的焊盘对向。对向的部分,要使分别安装到芯片与布线基板中的每一者上的突点彼此间对向。此外,采用使突点和焊盘或者突点彼此间接触并对两者进行加热粘接的办法,一揽子地进行倒装芯片接合和树脂密封。
此外,为了确实地效率良好地进行倒装芯片接合,还导入了用超声波振动进行的接合技术。在使用现有的超声波振动的倒装芯片接合技术中,布线基板被吸附到被叫做载置台的可加热的固定夹具上,芯片采用被吸附到被叫做工具的具有可以并用加压和超声波施加机构或加热的机构的装置上的办法进行装配。这时,为了使在芯片的焊盘之上形成的突点,和被形成为连接到布线基板的布线上的电镀突点或柱突点进行接合,要使芯片的元件形成面与布线基板的布线和焊盘形成面对向,边从工具给芯片施加超声波振动边给之加上重量(专利文献1)。
[专利文献1]
特开平8-45994号公报
但是,在一揽子地进行现有的倒装芯片接合和树脂密封的工序中,如果在高温下进行倒装芯片接合和树脂密封,则常常会因突点不能贯通树脂,树脂被夹在突点与布线基板之上的焊盘之间而产生导通不良。图9是说明现有的突点与焊盘之间的连接状态的照片,树脂被夹在了突点和焊盘之间。此外,还会因芯片和布线基板与树脂密封体之间以及布线基板与树脂密封体之间产生空隙而损害半导体器件的可靠性。
发明内容
本发明就是根据这样的事情而完成的,目的在于提供在一揽子地进行倒装芯片接合和树脂密封的工序中可以一揽子地同时进行没有导通不良的倒装芯片接合和可靠性高的树脂密封的半导体器件的制造方法。
本发明,在同时进行倒装芯片接合和树脂密封的半导体器件的制造方法中,其特征在于:为了确保突点连接的连接性,在使突点从树脂贯通后,用超声波振动,把在芯片或布线基板或在两方上形成的突点电连到布线基板或芯片的焊盘上,同时对芯片与布线基板间进行树脂密封。由于在突点贯通树脂后再进行接合,故可以减少连接不良。此外,还因防止了芯片-树脂间和布线基板-树脂间的空隙的发生而可以减少可靠性不良。
就是说,本发明的半导体器件的制造方法,在一揽子地同时进行至少通过1个突点电极把半导体芯片和布线基板电连起来的倒装芯片接合和树脂密封的半导体器件的制造方法中,其特征在于:在借助于超声波振动控制树脂密封用树脂的粘度使上述突点电极贯通上述树脂密封用树脂的同时,用上述超声波振动,把上述突点电极电连到上述半导体芯片或上述布线基板的别的突点电极上,或者电连到上述半导体芯片的连接电极或上述布线基板的连接电极中的任何一者上。
此外,在一揽子地同时进行至少通过1个突点电极把半导体芯片和布线基板电连起来的倒装芯片接合和树脂密封的半导体器件的制造方法中,其特征在于:借助于加热处理控制树脂密封用树脂的粘度,使上述突点电极贯通上述树脂密封用树脂,同时,用上述超声波振动,把上述突点电极电连到上述半导体芯片或上述布线基板的别的突点电极上,或者电连到上述半导体芯片的连接电极或上述布线基板的连接电极中的任何一者上。上述树脂密封用树脂的粘度,可以是0.01Pa·s~100Pa·s。上述超声波振动的强度,可以是100Hz~100kHz。上述倒装芯片接合与上述树脂密封可以在从20℃到上述树脂密封用树脂的反应率变成为50%的温度的范围内实施。之所以得以像这样地使实施温度作成为从低温到高温的的宽的范围,是因为可以调整树脂粘度的缘故。在上述半导体芯片上形成的突点电极从芯片表面算起的高度以及上述布线基板的连接电极从布线基板表面算起的高度之和,也可以比上述倒装芯片接合和树脂密封后的密封用树脂的厚度更大。
上述超声波振动,也可以从上述布线基板一侧,或从上述半导体芯片一侧,或者从上述布线基板一侧与上述半导体芯片一侧这两方施加。也可以从上述布线基板一侧,或从上述半导体芯片一侧,或者从上述布线基板一侧与上述半导体芯片一侧这两方进行加热。上述突点电极,也可以预先形成于上述布线基板上,或上述半导体芯片上,或者上述布线基板和半导体芯片上。
附图说明
图1是本发明的一个实施形态的芯片和布线基板的剖面图。
图2是说明在本发明的一个实施形态中,在把树脂粘贴到布线基板上后,进行倒装芯片接合的工序的剖面图。
图3是说明在本发明的一个实施形态中,在把树脂粘贴到布线基板上后,进行倒装芯片接合的工序的剖面图。
图4是说明在本发明的一个实施形态中,在把树脂粘贴到布线基板上后,进行倒装芯片接合的工序的剖面图。
图5的特性图,示出了在本发明的一个实施形态中,由本身为热硬化性树脂的环氧树脂等构成的树脂密封用树脂的硬化前的树脂粘度的温度依赖性。
图6的特性图,示出了在本发明的一个实施形态中,由本身为热硬化性树脂的环氧树脂等构成的树脂密封用树脂的硬化前的树脂粘度的超声波振动的频率依赖性。
图7是说明本发明的一个实施形态的突点与焊盘之间的连接状态的照片。
图8是说明在把树脂粘贴到本发明的一个实施形态的芯片上后,进行倒装芯片接合的工序的剖面图。
图9是说明现有的突点与焊盘的连接状态的照片。
具体实施方式
以下,参看附图说明发明的实施形态。
在本发明的实施形态中,要在温度100℃的条件下,用超声波振动实施一揽子连接、树脂密封的工序。采用在使树脂密封用树脂软化,突点完全贯通树脂密封用树脂后,进行突点与在布线基板之上形成的焊盘之间的接触的办法进行接合。为了维持该接合温度和树脂密封温度,要事先选定可使树脂密封用树脂充分地熔融,使粘度最低的温度。这样一来,就可以使突点从树脂密封用树脂中贯通出来。
图5的特性图示出了由本身为热硬化性树脂的环氧树脂等构成的树脂密封用树脂的硬化前的树脂粘度的温度依赖性。纵轴表示树脂粘度(Pas),横轴表示树脂温度(TEMP(℃))。树脂粘度的温度曲线A~E,依赖于超声波振动的频率,温度曲线A是频率为1Hz的情况,温度曲线B是10Hz的情况,温度曲线C是50Hz的情况,温度曲线D是79Hz的情况,温度曲线E是0.1Hz的情况。如图所示,树脂硬化前的树脂粘度,随着温度而变化,在在160~180℃的范围内示出的硬化开始的温度区域(硬化开始区域)以上的温度区域内,将急速地硬化(粘度增高),在硬化开始区域之前的温度,粘度比比该温度低的温度区域降低。该区域叫做低粘度区域。本发明虽然理想的是在该低粘度区域中进行,但是,没有必要限定于该区域。因为粘度会借助于超声波振动而变化。如温度曲线A~E所示,当频率增高时树脂粘度就降低。因此,采用对超声波振动的频率进行控制的办法,就可以调整树脂粘度。
图6的特性图,示出了由本身为热硬化性树脂的环氧树脂等构成的树脂密封用树脂的硬化前的树脂粘度的超声波振动的频率依赖性。纵轴表示树脂粘度(Pa·s),横轴表示超声波振动的频率(US(Hz))。特性线a是处理温度120℃时的树脂粘度-频率特性线,特性线b是处理温度100℃(是要在以下的实施形态中实施的温度)时的树脂粘度-频率特性线。此外,膏所给出的粘度,是用膏形成把芯片倒装芯片接合到布线基板上的情况下的两者间的树脂密封体的情况下的膏粘度,底充填(underfill)所给出的粘度,是向已进行了倒装芯片接合的芯片与布线基板之间流入树脂时的树脂粘度。如图所示,粘度大体上线性地随着超声波振动的频率而变化。由于只要树脂粘度在用膏进行的形成时的树脂粘度和用底充填进行的的形成时的树脂粘度以下,就可以实施本发明的半导体器件的制造方法,故本发明的超声波振动的频率范围,100Hz~100kHz是适当的,如果在该范围内,则可以把树脂密封用树脂的树脂粘度调整成对实施本发明最佳的值。即便是用比100Hz更小的值实施本发明也难以得到规定的树脂粘度。如果使实施温度变成为40℃或70℃等温度比较低的温度则树脂粘度会变得更高。在以下的实施例中,是在大约20~30kHz的范围(US-FC范围)内实施的。
其次,参看图1到图4及图7说明实施形态1。
图1是芯片和布线基板的剖面图。图2到图4是说明在把树脂粘贴到布线基板上后,进行倒装芯片接合的工序的剖面图。图7是说明该实施例的突点与焊盘之间的连接状态的照片。
倒装芯片型的半导体器件,由具备外部连接端子的印制基板等的布线基板,连接到该布线基板上的半导体芯片,填充到半导体芯片/布线基板间的树脂密封体构成。已制作上半导体元件或集成电路的芯片1,可采用把硅等的半导体晶片划成片的办法得到,半导体元件或集成电路的层间绝缘膜等,可以使用氧化硅膜或氮化硅膜以及被人们叫做LowK膜的低介电系数绝缘膜等的绝缘膜。在其之上形成有钝化膜,将成为端子的焊料等的突点3从钝化膜之间露了出来。突点3,已与内部的半导体元件或集成电路电连起来虽然未予画出,且在芯片1的表面上形成的铝等的焊盘2的之上形成。
另一方面,在支持芯片1的印制布线基板等的布线基板10上形成有把布线和布线电连起来的铝等的焊盘4。在布线基板10的装载芯片1的面上形成焊盘4,并把在芯片1上形成的突点3连接起来。此外,在布线基板10的另一面上通过未画出来的焊盘安装有突点。该突点可用做半导体器件的外部连接端子。此外,在形成了该布线基板10的焊盘4的面上膏状或薄膜状地形成有树脂密封用树脂5。
其次,参看图2到图4说明在把树脂粘贴到布线基板上后进行倒装芯片接合的工序。把与芯片1的元件形成面相反一侧的背面吸附固定到用多孔质材料形成了吸附面的载置台7上。在芯片1的元件形成面上形成有焊盘2和其之上的突点3。此外,与布线基板10的焊盘形成面相反一侧的背面被吸附到工具8上。在该工具8上设置有加热、加压和超声波振动施加机构。已被布线基板10的树脂5被覆起来的焊盘4,被配置为与芯片1的突点3对向。
其次,使载置台7和工具8进行位置对准以使突点3和焊盘4对准。然后,使工具8下降并使布线基板10面朝下。在该状态下,用加压和超声波施加机构边加压边施加超声波振动。这时,要预先作成为使得工具8维持100℃(图2)。此外,继续提供超声波振动使树脂密封用树脂软化,使突点3完全贯通树脂密封用树脂5。采用进行使突点3与在布线基板10之上形成的焊盘4接触的办法进行接合。为了维持该接合和树脂密封温度,要预先选定可使树脂密封用树脂5充分地熔融,粘度变成为最低的温度。这样一来,就可以使突点3从树脂密封用树脂5中贯通出来(图3)。此外,继续提供超声波振动以使布线基板10的焊盘4与突点3进行接合,在把两者电连起来的同时,使树脂5硬化在芯片1和布线基板10之间形成树脂密封体6。
如上所述,倘采用本实施形态,由于可以借助于突点贯通树脂,故可以减少接触不良。如图7所示,由于在突点与焊盘之间不存在树脂,故可以得到良好的连接。可以防止芯片-树脂间和布线基板-树脂间的空隙的发生,可以降低可靠性不良。此外,由于可以进行在低温下进行的一揽子连接和密封,故可以减小封装的弯曲。
另外,载置台7也可以根据需要至少设置加热机构或超声波施加机构中的一方。归因于像这样地构成,就可以边给布线基板和芯片这两方提供超声波振动边进行倒装芯片接合。此外,在本实施形态中,虽然在芯片之上的焊盘上形成突点,但是,在本发明中,既可以在布线基板的焊盘上形成突点,也可以在芯片和布线基板这两方上形成突点。
其次,参看图8说明实施形态2。
图8是说明在把树脂粘贴到芯片上后,进行倒装芯片接合的工序的剖面图。把与布线基板20的焊盘形成面相反一侧的背面吸附固定到用多孔质材料形成了吸附面的载置台27上。在布线基板20的焊盘形成面上形成有焊盘24。此外,与芯片21的元件形成面相反一侧的背面被吸附到工具28上。在该工具28上设置有加热、加压和超声波振动施加机构。布线基板20的焊盘24,被配置为与芯片21焊盘22之上的的突点23对向。
其次,使载置台27和工具28进行位置对准以使突点23和焊盘24对准。然后,使工具28下降并使芯片21面朝下。在该状态下,用加压和超声波施加机构边加压边施加超声波振动。这时,要预先作成为使得工具28维持100℃。此外,继续提供超声波振动使树脂密封用树脂25软化,使突点23完全贯通树脂密封用树脂25。采用进行使突点23与在布线基板20之上形成的焊盘24接触的办法进行接合。为了维持该接合和树脂密封温度,要预先选定可使树脂密封用树脂25充分地熔融,粘度变成为最低的温度(理想的是图5所示的低粘度区域)。这样一来,就可以使突点23从树脂密封用树脂25贯通出来。此外,继续提供超声波振动以使布线基板20之上的焊盘24与芯片21之上的突点23进行接合,在把两者电连起来的同时,使树脂25硬化在芯片21和布线基板20之间形成树脂密封体26。
如上所述,倘采用本实施形态,由于可以借助于突点贯通树脂,故可以减少接触不良。此外,还可以防止芯片-树脂间和布线基板-树脂间的空隙的发生,可以降低可靠性不良。此外,由于可以进行在低温下进行的一揽子连接和密封,故可以减小封装的弯曲。
如上所述,倘采用本发明,由于可以借助于突点贯通树脂,故可以减少接触不良,因可以防止芯片-树脂间和布线基板-树脂间的空隙的发生而可以降低可靠性不良。由于可以进行在低温下进行的一揽子连接和密封,故可以减小封装的弯曲。

Claims (15)

1.一种半导体器件的制造方法,在一揽子地进行通过突点电极把半导体芯片和布线基板电连起来的倒装芯片接合和树脂密封的半导体器件的制造方法中,其特征在于:在借助于超声波振动控制树脂密封用树脂的粘度使上述突点电极贯通上述树脂密封用树脂的同时,用上述超声波振动,把上述突点电极电连到上述半导体芯片或上述布线基板的别的突点电极上,或者电连到上述半导体芯片的连接电极或上述布线基板的连接电极中的任何一者上。
2.一种半导体器件的制造方法,在一揽子地进行通过突点电极把半导体芯片和布线基板电连起来的倒装芯片接合和树脂密封的半导体器件的制造方法中,其特征在于:借助于加热处理控制树脂密封用树脂的粘度,使上述突点电极贯通上述树脂密封用树脂,同时,用上述超声波振动,把上述突点电极电连到上述半导体芯片或上述布线基板的别的突点电极上,或者电连到上述半导体芯片的连接电极或上述布线基板的连接电极中的任何一者上。
3.根据权利要求1或2所述的半导体器件的制造方法,其特征在于:上述树脂密封用树脂的粘度,是0.01Pa·s~100Pa·s。
4.根据权利要求1或2所述的半导体器件的制造方法,其特征在于:上述超声波振动的强度,是100Hz~100kHz。
5.根据权利要求1或2所述的半导体器件的制造方法,其特征在于:上述倒装芯片接合与上述树脂密封,在从20℃到上述树脂密封用树脂的反应率变成为50%的温度的范围内实施。
6.根据权利要求1到5中的任何一者所述的半导体器件的制造方法,其特征在于:在上述半导体芯片上形成的突点电极从芯片表面算起的高度以及上述布线基板的连接电极从布线基板表面算起的高度之和,比上述倒装芯片接合和树脂密封后的密封用树脂的厚度更大。
7.根据权利要求1或2所述的半导体器件的制造方法,其特征在于:上述超声波振动,从上述布线基板一侧施加。
8.根据权利要求1或2所述的半导体器件的制造方法,其特征在于:上述超声波振动,从上述半导体芯片一侧施加。
9.根据权利要求1或2所述的半导体器件的制造方法,其特征在于:上述超声波振动,从上述布线基板侧与上述半导体芯片侧这两方施加。
10.根据权利要求2所述的半导体器件的制造方法,其特征在于:从上述布线基板一侧进行加热。
11.根据权利要求2所述的半导体器件的制造方法,其特征在于:从上述半导体芯片一侧进行加热。
12.根据权利要求2所述的半导体器件的制造方法,其特征在于:从上述布线基板侧与上述半导体芯片侧这两方进行加热。
13.根据权利要求1所述的半导体器件的制造方法,其特征在于:上述突点电极,预先在上述布线基板上形成。
14.根据权利要求1所述的半导体器件的制造方法,其特征在于:上述突点电极,预先上述半导体芯片上形成。
15.根据权利要求1所述的半导体器件的制造方法,其特征在于:上述突点电极,预先在上述布线基板和半导体芯片上形成。
CNA2004100381372A 2003-05-12 2004-05-08 半导体器件的制造方法 Pending CN1551323A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003132674A JP2004335916A (ja) 2003-05-12 2003-05-12 半導体装置の製造方法
JP132674/2003 2003-05-12

Publications (1)

Publication Number Publication Date
CN1551323A true CN1551323A (zh) 2004-12-01

Family

ID=33507449

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2004100381372A Pending CN1551323A (zh) 2003-05-12 2004-05-08 半导体器件的制造方法

Country Status (4)

Country Link
US (1) US20050026326A1 (zh)
JP (1) JP2004335916A (zh)
CN (1) CN1551323A (zh)
TW (1) TW200509218A (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101728289B (zh) * 2008-10-10 2011-12-28 哈尔滨工业大学深圳研究生院 一种面阵封装电子元件的室温超声波软钎焊方法
CN102556940A (zh) * 2010-12-24 2012-07-11 三美电机株式会社 结构体
CN105742198A (zh) * 2014-12-26 2016-07-06 台湾积体电路制造股份有限公司 管芯接合器及其使用方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7262079B2 (en) * 2005-02-10 2007-08-28 Altera Corporation Consolidated flip chip BGA assembly process and apparatus
JP2007172697A (ja) * 2005-12-20 2007-07-05 Fujitsu Ltd フライングリードの接合方法
JP5093482B2 (ja) * 2007-06-26 2012-12-12 ソニーケミカル&インフォメーションデバイス株式会社 異方性導電材料、接続構造体及びその製造方法
WO2009001605A1 (ja) * 2007-06-26 2008-12-31 Sony Chemical & Information Device Corporation 異方性導電材料、接続構造体及びその製造方法
JP5197175B2 (ja) * 2008-06-16 2013-05-15 キヤノン株式会社 インクジェット記録ヘッドおよびその製造方法
CN106575695B (zh) * 2014-09-26 2020-01-21 东芝北斗电子株式会社 发光组件及发光组件的制造方法
KR102152906B1 (ko) * 2018-11-20 2020-09-09 세메스 주식회사 본딩 장치 및 본딩 방법

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6432236B1 (en) * 1991-03-01 2002-08-13 Foster-Miller, Inc. Ultrasonic method of fabricating a thermosetting matrix fiber-reinforced composite structure and the product thereof
JP2000036520A (ja) * 1998-05-15 2000-02-02 Nec Corp フリップチップ実装方法及び装置
JP2000068327A (ja) * 1998-08-20 2000-03-03 Matsushita Electric Ind Co Ltd 部品の実装方法と装置
JP2000339648A (ja) * 1999-05-24 2000-12-08 Tdk Corp 磁気ヘッド装置の製造方法
JP3451373B2 (ja) * 1999-11-24 2003-09-29 オムロン株式会社 電磁波読み取り可能なデータキャリアの製造方法
JP2002151551A (ja) * 2000-11-10 2002-05-24 Hitachi Ltd フリップチップ実装構造、その実装構造を有する半導体装置及び実装方法
JP4330821B2 (ja) * 2001-07-04 2009-09-16 株式会社東芝 半導体装置の製造方法
US6838316B2 (en) * 2002-03-06 2005-01-04 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method using ultrasonic flip chip bonding technique
JP3717899B2 (ja) * 2002-04-01 2005-11-16 Necエレクトロニクス株式会社 半導体装置及びその製造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101728289B (zh) * 2008-10-10 2011-12-28 哈尔滨工业大学深圳研究生院 一种面阵封装电子元件的室温超声波软钎焊方法
CN102556940A (zh) * 2010-12-24 2012-07-11 三美电机株式会社 结构体
CN105742198A (zh) * 2014-12-26 2016-07-06 台湾积体电路制造股份有限公司 管芯接合器及其使用方法
US10475764B2 (en) 2014-12-26 2019-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Die bonder and methods of using the same
US10950572B2 (en) 2014-12-26 2021-03-16 Taiwan Semiconductor Manufacturing Company, Ltd. Die bonder and methods of using the same
US10964663B2 (en) 2014-12-26 2021-03-30 Taiwan Semiconductor Manufacturing Company, Ltd. Die bonder and methods of using the same

Also Published As

Publication number Publication date
US20050026326A1 (en) 2005-02-03
JP2004335916A (ja) 2004-11-25
TW200509218A (en) 2005-03-01

Similar Documents

Publication Publication Date Title
JP4262672B2 (ja) 半導体装置およびその製造方法
KR100352865B1 (ko) 반도체 장치 및 그 제조방법
JP3409957B2 (ja) 半導体ユニット及びその形成方法
US20050110161A1 (en) Method for mounting semiconductor chip and semiconductor chip-mounted board
US20030001286A1 (en) Semiconductor package and flip chip bonding method therein
US20050163982A1 (en) Circuit substrate for packaging semiconductor device, method for producing the same, and method for producing semiconductor device package structure using the same
JP4846633B2 (ja) 部品内蔵基板の製造方法
CN1215921A (zh) 模压球栅阵列型半导体器件及其制造方法
CN103035601A (zh) 在烧结银层上包括扩散焊接层的半导体器件
CN1229330A (zh) 混合模块及其制造方法与其安装方法
CN1299518A (zh) 半导体封装及其倒装芯片接合法
CN1551323A (zh) 半导体器件的制造方法
JP2625654B2 (ja) 半導体装置およびその製造方法
CN101047158A (zh) 半导体器件及其制造方法
CN109473539B (zh) 一种滤波器芯片模组及其制备方法
CN1666334A (zh) 反应焊接材料
CN100352023C (zh) 半导体装置的制造方法以及半导体装置的制造装置
KR20020044093A (ko) 반도체칩의 적층실장방법
EP1369911A1 (en) Method of manufacturing semiconductor device
JP2002368159A (ja) 半導体装置およびその製造方法
CN112714539A (zh) 电子组件及制造电子组件的方法
US6887777B2 (en) Method for connecting an integrated circuit to a substrate and corresponding circuit arrangement
JP3572254B2 (ja) 回路基板
JP3014577B2 (ja) 半導体装置の製造方法
JPH11288975A (ja) ボンディング方法及びボンディング装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication