CN1503987A - 钨硅闸极选择性侧壁氧化期间最小化氧化钨蒸气沉积之方法 - Google Patents

钨硅闸极选择性侧壁氧化期间最小化氧化钨蒸气沉积之方法 Download PDF

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Publication number
CN1503987A
CN1503987A CNA028087208A CN02808720A CN1503987A CN 1503987 A CN1503987 A CN 1503987A CN A028087208 A CNA028087208 A CN A028087208A CN 02808720 A CN02808720 A CN 02808720A CN 1503987 A CN1503987 A CN 1503987A
Authority
CN
China
Prior art keywords
temperature
treatment step
metallization structure
hydrogen
during
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA028087208A
Other languages
English (en)
Chinese (zh)
Inventor
S
S·弗里格
W·科格尔
J·－U·萨奇塞
M·斯塔德特米勒
R·哈伊恩
G·罗特斯
E·肖尔
Б
O·斯托贝克
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Mattson Thermal Products GmbH
Original Assignee
Infineon Technologies AG
Mattson Thermal Products GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG, Mattson Thermal Products GmbH filed Critical Infineon Technologies AG
Publication of CN1503987A publication Critical patent/CN1503987A/zh
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
    • H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
    • H10D64/01308—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal
    • H10D64/01312—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal the additional layer comprising a metal or metal silicide formed by deposition, i.e. without a silicidation reaction, e.g. sputter deposition

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Chemical Vapour Deposition (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CNA028087208A 2001-04-26 2002-04-10 钨硅闸极选择性侧壁氧化期间最小化氧化钨蒸气沉积之方法 Pending CN1503987A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10120523A DE10120523A1 (de) 2001-04-26 2001-04-26 Verfahren zur Minimierung der Wolframoxidausdampfung bei der selektiven Seitenwandoxidation von Wolfram-Silizium-Gates
DE10120523.6 2001-04-26

Publications (1)

Publication Number Publication Date
CN1503987A true CN1503987A (zh) 2004-06-09

Family

ID=7682847

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA028087208A Pending CN1503987A (zh) 2001-04-26 2002-04-10 钨硅闸极选择性侧壁氧化期间最小化氧化钨蒸气沉积之方法

Country Status (8)

Country Link
US (1) US7094637B2 (https=)
EP (1) EP1382062B1 (https=)
JP (1) JP2004526327A (https=)
KR (1) KR20040015149A (https=)
CN (1) CN1503987A (https=)
DE (2) DE10120523A1 (https=)
TW (1) TW550711B (https=)
WO (1) WO2002089190A2 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104269343A (zh) * 2007-09-24 2015-01-07 应用材料公司 改善选择性氧化工艺中氧化物生长速率的方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7020729B2 (en) * 2002-05-16 2006-03-28 Intel Corporation Protocol independent data transmission interface
DE10236896B4 (de) * 2002-08-12 2010-08-12 Mattson Thermal Products Gmbh Vorrichtung und Verfahren zum thermischen Behandeln von Halbleiterwafern
US6774012B1 (en) * 2002-11-08 2004-08-10 Cypress Semiconductor Corp. Furnace system and method for selectively oxidizing a sidewall surface of a gate conductor by oxidizing a silicon sidewall in lieu of a refractory metal sidewall
US7235497B2 (en) * 2003-10-17 2007-06-26 Micron Technology, Inc. Selective oxidation methods and transistor fabrication methods
KR100580118B1 (ko) * 2005-03-09 2006-05-12 주식회사 하이닉스반도체 반도체 소자의 게이트 전극 패턴 형성방법
JP2007123669A (ja) * 2005-10-31 2007-05-17 Elpida Memory Inc 半導体装置の製造方法
KR100650858B1 (ko) * 2005-12-23 2006-11-28 주식회사 하이닉스반도체 플래쉬 메모리 소자의 제조 방법
US8278287B2 (en) * 2008-04-15 2012-10-02 Quark Pharmaceuticals Inc. siRNA compounds for inhibiting NRF2
WO2010026624A1 (ja) * 2008-09-02 2010-03-11 株式会社 東芝 不揮発性半導体記憶装置の製造方法
US8889565B2 (en) * 2009-02-13 2014-11-18 Asm International N.V. Selective removal of oxygen from metal-containing materials
US11456177B2 (en) * 2020-09-22 2022-09-27 Nanya Technology Corporation Method of manufacturing semiconductor device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59132136A (ja) * 1983-01-19 1984-07-30 Hitachi Ltd 半導体装置の製造方法
JPH10223900A (ja) * 1996-12-03 1998-08-21 Toshiba Corp 半導体装置及び半導体装置の製造方法
US5796151A (en) 1996-12-19 1998-08-18 Texas Instruments Incorporated Semiconductor stack having a dielectric sidewall for prevention of oxidation of tungsten in tungsten capped poly-silicon gate electrodes
JP4283904B2 (ja) * 1997-07-11 2009-06-24 株式会社東芝 半導体装置の製造方法
JP2000156497A (ja) * 1998-11-20 2000-06-06 Toshiba Corp 半導体装置の製造方法
US6346467B1 (en) 1999-09-02 2002-02-12 Advanced Micro Devices, Inc. Method of making tungsten gate MOS transistor and memory cell by encapsulating

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104269343A (zh) * 2007-09-24 2015-01-07 应用材料公司 改善选择性氧化工艺中氧化物生长速率的方法

Also Published As

Publication number Publication date
WO2002089190A3 (de) 2003-01-09
EP1382062B1 (de) 2007-11-14
DE10120523A1 (de) 2002-10-31
EP1382062A2 (de) 2004-01-21
TW550711B (en) 2003-09-01
KR20040015149A (ko) 2004-02-18
US7094637B2 (en) 2006-08-22
WO2002089190A2 (de) 2002-11-07
US20040121569A1 (en) 2004-06-24
JP2004526327A (ja) 2004-08-26
DE50211205D1 (de) 2007-12-27

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