CN1502125A - 半导体器件的封装体及其制造方法 - Google Patents

半导体器件的封装体及其制造方法 Download PDF

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CN1502125A
CN1502125A CNA028071484A CN02807148A CN1502125A CN 1502125 A CN1502125 A CN 1502125A CN A028071484 A CNA028071484 A CN A028071484A CN 02807148 A CN02807148 A CN 02807148A CN 1502125 A CN1502125 A CN 1502125A
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electrode
mentioned
semiconductor chip
projected
core
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CN1246891C (zh
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��һ��
寺嶋一彦
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Citizen Watch Co Ltd
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Citizen Watch Co Ltd
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Abstract

本发明涉及具有突起电极的半导体芯片对置地载置在配线基板上的半导体器件的封装体及这样的封装体的制造方法。该半导体器件的封装体由具有突起电极(5)的半导体芯片(20)、和在一个面上形成与上述突起电极(5)的端面接触的对置电极(8)的对置基板(9)、介于半导体芯片(20)和对置基板(9)之间的粘接剂构成。突起电极(5)做成由核心部分(5b)、在该核心部分(5b)的上方形成与该核心部分不是一体的凸状的电极端部(5a)构成的2层结构。

Description

半导体器件的封装体及其制造方法
技术领域
本发明涉及具有突起电极的半导体芯片对置地载置在配线基板上的半导体器件的封装体及这样的封装体的制造方法。
背景技术
在具有突起电极的半导体元件对置地封装在配线基板上时，使热固性的粘接用绝缘树脂介于半导体元件和配线基板之间，将半导体元件的突起电极压紧在配线基板上，由于该配线基板和该配线基板上的电极塑性变形或弹性变形成凹状，因而使半导体元件与配线基板上的电极进行电连接，这在特开平4-82241号公报和特开平11-284022号公报中已公开。该半导体元件的突起电极是使用电镀法在半导体元件上的片状电极(パツド电极)的上面用Au等金属材料形成的。
在形成这样的突起电极中，因为不能调整突起电极前端的形状，所以在配线基板上压紧突起电极时，突起电极前端的形状和压紧该突起电极而发生变形的配线基板上的电极形状要充分地吻合，否则就得不到稳定的电连接。
发明内容
本发明的目的是提供，在具有突起电极的半导体芯片封装在表面设置了对置电极的对置基板上时，不损害该对置电极、能够充分地进行突起电极和对置电极的电连接的、可靠性高的半导体器件的封装体以及其制造方法。
为了实现上述目的，本发明的半导体器件的封装体具备：具有突起电极的半导体芯片、在一面上形成和上述突起电极的端面接触的对置电极的树脂制对置基板、以及介于上述半导体芯片和上述对置基板之间的绝缘性热塑性、热固性或光固性的粘接剂。而且，上述突起电极做成具有核心部分和在该核心部分的上方形成与该核心部分不是一体的凸状的电极端部的2层结构。
构成突起电极的电极端部，通过加热构成电极端部的材料，就能够形成相应该材料用量的圆形，因而能够容易地调整适合于对置基板和对置电极的材质。因此，能够确保突起电极和对置电极的电连接。
附图说明
图1是本发明的第一实施方式的半导体器件封装体的剖面图。
图2是本发明的第二实施方式的半导体器件封装体的剖面图。
图3A～图3D是说明图1所示的半导体封装体的制造方法的图。
图4A～图4D是说明图2所示的半导体封装体的制造方法的图，说明直至将途中的突起电极制成阶梯状前的过程。
图5A～图5C是说明图2所示的半导体封装体的制造方法的图，说明使突起电极形成阶梯状后，直至在该突起电极上形成电极端部和电极保护膜的过程。
具体实施方式
参照图1及图3A-图3D说明本发明的半导体器件封装体的第1实施方式。
在图1中，在厚度0.3至1.0mm左右的硅单晶基片1上形成有源元件或理论电路或电路配线等的半导体集成电路。用基片1、设置在该基片1上的片状电极2和保护膜3构成半导体芯片20。片状电极2使在基片1上形成的半导体集成电路的电源或信号系配线与外部连接。另外，保护膜3在与片状电极2对置的部位具有开口部，保护在基片1上形成的半导体集成电路。
进而，在片状电极2和其外侧周围的保护膜3上形成突起电极5。该突起电极5的上端面，其中央部保持圆形，而形成隆起的凸状(球面的一部分)。
由于在半导体芯片20和由树脂构成的对置基板9之间填充绝缘性粘接剂7，所以该半导体芯片20上的突起电极5与对置基板9的对置电极8进行电连接。在这种状态，如图1所示，对置基板9形成与突起电极5的上端面的凸状对应的凹状。
在制作图1的封装体时，首先在半导体芯片20或对置基板9的任何一个上涂布绝缘性粘接剂7。接着，在对置基板9的材料的玻璃转变温度(Tg)以下、而且在绝缘性粘接剂7的固化温度、使低压接应力保持一定时间的热压接条件下，将半导体芯片20上的突起电极5和对置基板9上的对置电极8粘接在一起。通过该突起电极5粘接在对置电极8上，在该对置基板9和对置电极8上形成对应于突起电极5的端面凸状的凹部。其结果，由于突起电极5的凸状的端面和在对置电极8上形成的凹部发生吻合，半导体芯片20和对置电极8保持电连接。
在形成突起电极5时，首先在阻挡金属层4的上层形成心层5b，然后形成电极端部5a。在心层5b上使用比电极端部5a更高熔点的金属材料。通过使电极端部5a进行选择地熔融，利用其熔融金属的表面张力就能够使突起电极5的端面的形状大致成为球面的一部分。为了使电极端部5a的球面曲率半径变大，在突起电极5的高度不够的情况下，通过增加心层5b的厚度，就能够将突起电极5的高度调整到必要的高度。
进而，在突起电极5的最上层可以形成突起电极覆盖膜5c。利用该突起电极覆盖膜5c，在能够防止突起电极5表面的氧化的同时，能够实现与对置电极8的良好连接。
突起电极5的电极端部5a具有比对置基板9的材料的弹性率大、而且比对置基板9的材料的Tg更高熔点的材料，例如最好使用导电性优良的Au、Ag、Sn、Ni、Pb等金属或含有这些金属的塑性物。在上述加热压接条件下，如果使具有这种材料的电极端部5a的突起电极5相对于对置基板9进行压接，施加在对置电极8上的压接应力就被对置基板9吸收而适度地分散，对置基板9发生塑性变形而形成凹部。其结果，突起电极5在保持其形状的状态下，能够得到与对置电极8之间的良好的电连接。如果使对置基板9上形成的凹部的深度达到5μm左右，即使在突起电极5上存在1～2μm高的波动，也能够弥补此波动。
对置基板9最好由绝缘性和平滑性等优良的热塑性树脂材料或热固性树脂材料构成。进而，对置基板9最好由具有比在突起电极5中所用材料熔点低的Tg的树脂组合物构成。例如可以使用聚碳酸酯或聚醚砜或液晶聚合物等热塑性树脂、或环氧或聚酰亚胺等热固性树脂构成的薄板或薄膜。可以根据需要在这些树脂材料中添加填充剂，也可以在表面设置阻挡气体层。
另外，为了在对置基板9和对置电极8上容易形成对应于突起电极5的端面形状(凸状)的凹部，对于对置电极8的材料来说，例如优先使用导电性和延伸性优良的膜厚10μm以下的Al、Cu、Ni、Au等金属膜或由含有这些金属的组合物构成的单层或者多层膜为佳。进而最好使用在厚度10μm以下的Cu膜上设置膜厚为1μm以下的Au膜的多层膜。
另外，在液晶显示器中使用的透明电极中，最好使用1μm以下的铟锡氧化物(以下称为ITO)的膜作为对置电极。进而，在使用上述ITO膜的情况下，为了使连接电阻低，也可以在上层设置膜厚1μm以下的Al、Cu、Au等金属膜或由含有这些金属的组合物构成的单层或者多层膜。
因为绝缘性粘接剂7使半导体芯片20粘合在对置基板9上，所以希望选择在突起电极5的熔点以下、而且在对置基板9的材料的Tg的加热压接温度就能够充分进行固化的材料。因此，对于绝缘性粘接剂7的材料来说，可以使用热塑性、热固性、光固性等树脂组合物，但希望使用在对置基板9的Tg以下的温度范围能够固化的热固性树脂组合物，具体的最好使用丙烯酸、氨基甲酸乙酯、环氧等树脂组合物。
在使半导体芯片20粘合在对置基板9上中，虽然先前说明了先在半导体芯片20或对置基板9的任一个上涂布绝缘性粘接剂7，然后，使半导体芯片20上的突起电极5相对于对置基板9进行加热压接，但代替这些，也可以在突起电极5压接在对置电极8上之后，填充绝缘性粘接剂7进行固化。
另外，在构成半导体芯片20的片状电极2和突起电极5之间，也可以设置用于防止金属材料相互扩散的阻挡金属层4。
以下，参照图3A～图3D说明图1的半导体器件的封装体制造方法的一例。
1.在基板上的片状电极上形成突起电极的心层和电极端部(图3A)：
在单晶片基片1上形成构成半导体芯片的片状电极2和保护膜3。保护膜3仅露出片状电极2的表面地形成。
首先，在包括保护膜3和片状电极2的表面的全部区域，通过溅射法形成膜厚0.5μm的、是Ti/W组成膜的阻挡金属层4。接着，在该阻挡金属层4的上层，除了片状电极2的上方部分区域，通过光刻法形成电镀抗蚀膜10。
然后，在电镀抗蚀膜10未覆盖的、片状电极2上方的阻挡金属层4的上，利用以该阻挡金属层4作为共同电极膜使用的电镀法，使厚20μm的Cu生长，而形成心层5b。
进而，利用以阻挡金属层4作为共同电极膜使用的电镀法，使具有比心层5b的熔点低的金属Sn/Pb＝6/4的软钎料生长，而形成电极端部5a。
通过上述的过程得到图3A所示的结构体。
2.使突起电极的端面(与对置电极的连接面)变形成为凸状(成为大致球面的一部分的形状)(图3B)：
首先，单晶硅片1在加热到200℃的加热板上放置20秒。这样一来，从单晶硅片1传导来的热只能使突起电极5的电极端部5a熔化，由于其表面张力，电极端部5a的形状成为大致球面的一部分。该电极端部5a的球面曲率半径能够容易通过应该生长的金属电镀量进行调整。也就是说，如果金属电镀量少，曲率半径就变大，能够形成具有坡度小的端面的电极端部5a。另一方面，如果金属的电镀量多，就能够得到电极端部5a的高度，突起电极5的端面曲率半径变小。
再利用电镀法，使0.1μm厚的Au的突起电极覆盖膜5c生长，在电极端部5a的表面形成突起电极覆盖膜5c。
通过上述的过程得到图3B所示的结构体。
3.形成具备突起电极的半导体芯片(图3C)：
首先，用市售的抗蚀膜剥离液去除图3B所示结构体的电镀抗蚀膜10，而露出阻挡金属层4。
接着，用过氧化氢溶液对露出的阻挡金属层4进行蚀刻。
通过上述的过程得到图3C所示的结构体。
4.使突起电极5电连在对置电极8上(图3D)：
首先，在厚度0.2mm的聚碳酸酯树脂构成的对置基板9上，利用溅射法形成厚度0.8μm的ITO膜，再使用光刻法得到所希望形状的对置电极8。
再在对置基板9的表面(被封装面)上供给未固化状态的环氧树脂组合物的绝缘性粘接剂7。
接着，在130℃，以40Kg/cm2将半导体芯片(由片状电极2和保护膜3构成)的突起电极5与对置基板9上的对置电极8进行充分地加热压接，在该状态保持2分钟。其结果，在对置基板9和对置电极8上形成与突起电极5的尖端形状对应的凹部。于是，凸状(成为部分球面的的一部分的形状)的突起电极5与对置电极8的凹部吻合，由此进行两电极5、8可靠的电连接。
与此同时，使绝缘性粘接剂7充分地固化，半导体芯片(片状电极2和保护膜3)和对置基板9被牢固地粘接在一起。
通过上述的过程完成图1所示的封装体。
本发明的封装体的突起电极5，其端面呈现大致球面的一部分形状，因此在半导体芯片上的突起电极5相对于对置基板9上的对置电极8进行加热压接过程的初期阶段，未固化的绝缘性粘接剂7容易从两电极5、8的连接面排出，其结果是，两电极5、8能够直接(不存在粘结剂7)进行连接。
再者，在以上的例子中，向对置基板9的表面(被封装面)供给未固化状态的环氧树脂组合物的绝缘性粘接剂7是在将半导体芯片上的突起电极5粘结在对置基板9上的对置电极8上之前。代替此，使半导体芯片上的突起电极5与对置基板9上的对置电极8粘结后，也可以利用分配器向半导体芯片和对置基板9之间供给未固化的液状绝缘性粘结剂7，此后进行半导体芯片对对置基板9的加热压接过程，使两电极5、8连接。
按照本发明的方法制造半导体器件的封装体中，即使温度、压接应力设定得低，也能够实现良好的电连接。因此，在由树脂构成的对置基板9上封装本发明的半导体器件的封装体时，能够极力抑制对置基板9上的对置电极破损。因此，按照本发明能够提供适应高密度封装的半导体器件的封装体。
参照图2和图4A-图4C和图5A-图5C说明本发明的半导体器件封装体的第2实施方式。
图2所示的半导体的封装体，在突起电极5的心层5b成为阶梯状这点上和图1所示的封装体不同。以下说明其制造方法。
1.在基板的片状电极上形成突起电极的心层(图4A)：
使用和制作图1的封装体时使用的相同的方法形成片状电极2、保护膜3、阻挡金属层4和心层5b。
即，在包括保护膜3和片状电极2的表面的全部区域，利用溅射法形成阻挡金属层4。而，在该阻挡金属层4的上层，除了片状电极2的上方部分的区域，使用光刻法形成电镀抗蚀膜(在图4A中未示出)。然后，在电镀抗蚀膜未覆盖的、片状电极2上方的阻挡金属层4的上面，通过以该阻挡金属层4作为共同电极膜使用的电镀法，使厚度20μm的Cu生长，而形成心层5b。在此后，再使用抗蚀膜剥离液除去电镀抗蚀膜，并且用过氧化氢溶液蚀刻露出的(即心层5b未覆盖)部分的阻挡金属层4，得到图4A的结构体。
2.电镀抗蚀膜的形成(图4B)：
在图4A所示的结构体上用旋转涂布法涂布新的正型抗蚀剂，在保护膜3和心层5b上形成电镀抗蚀膜10，得到图4B所示的结构体。
3.阶梯状的抗蚀膜图案的形成(图4C)：
用Cr材料的光刻掩模(未图示)蚀刻图4B的结构体中的电镀抗蚀膜10。对该光刻掩模照射来自曝光光源的紫外线，利用紫外线光量的程度控制抗蚀膜的分解，电镀抗蚀膜10的
第一区域10a用蚀刻去除，使心层5b完全露出，
第二区域10b被蚀刻至中途，停留在用膜厚薄的电镀抗蚀膜10覆盖心层5b的状态，另外，
第三区域10c是未进行蚀刻的区域。
再有，上述第一区域10a和第二区域10b是心层5b上方的区域，第三区域10c是离开心层5b上方的区域。
4.心层的蚀刻(图5A)：
在图4C的结构体上进行干蚀刻。采用干蚀刻，在露出心层5b的第一区域10a，从干蚀刻的开始阶段开始心层5b的蚀刻，另外，在以膜厚薄的电镀抗蚀膜10覆盖的第二区域10b，用干蚀刻除去这种膜厚薄的电镀抗蚀膜10后，开始蚀刻心层5b。
通过上述的干蚀刻就得到具有阶梯状心层5b的图5A的结构体。
再者，图5A的结构体的心层5b的阶梯数是2，为了在心层5b上赋予3以上的阶梯，只要使用光刻掩模就可以，该光刻掩模具有在3阶梯以上变化紫外线的遮光量的图案。
5.在阶梯状的心层上形成电极端部(图5B)：
如图5B所示，通过电解电镀法使电极端部5a各向同性生长。
6.突起电极覆膜的形成(图5C)：
通过与第一实施方式相同的热处理，使阶梯状心层的电极端部5a形成圆形后，通过电镀法形成突起电极覆膜5c，得到图5C所示的结构体。
如以上所说明，按照本发明，在心层和电极端部的2层上形成半导体芯片上的突起电极，因此能够使半导体芯片上的电极端部的尖端的圆形成为任意的形状，能够容易调整适合于对置基板和对置电极的材质。因此，突起电极和对置电极的可靠的电连接成为可能。
再者，如果在对置电极8的输入侧配置电极端部5a的坡度小的面，就能够将封装体形成时的对置电极8的输入侧的破损限制在最小限度。位于其相反侧的对置电极8即使破损，在半导体器件的驱动上也没有问题。因此，本构造能够适应更高密度的封装，而且对存在由对置基板9的材料和对置电极的材料等引起的突起电极8的破损的危险是特别有效的方式。

Claims (7)

1.一种半导体器件的封装体，其具备：
具有突起电极的半导体芯片、
在一个面上形成与上述突起电极的端面接触的对置电极的树脂制的对置基板，以及
介于上述半导体芯片和上述对置基板之间的绝缘性的热塑性、热固性或光固性的粘接剂；其特征在于：
上述突起电极由核心部分和在该核心部分的上方形成与该核心部分不是一体的凸状的电极端部构成。
2.根据权利要求1所述的半导体器件的封装体，其特征在于，在上述突起电极的电极端部的表面上形成防止突起电极的表面氧化、而且用于谋求与上述对置电极良好连接的突起电极覆膜。
3.根据权利要求1所述的半导体器件的封装体，其特征在于，在构成上述半导体芯片的片状电极和上述突起电极的核心部分之间，使用电镀法设置用于使上述核心部分生长的电极膜。
4.根据权利要求1所述的半导体器件的封装体，其特征在于，上述突起电极的核心部分形成阶梯数是2或者3以上的阶梯状。
5.一种半导体器件的封装体的制造方法，其特征在于，包括以下步骤：
在半导体芯片的片状电极的上方形成突起电极的核心部分，
使用电镀法在上述核心部分的表面上使具有比上述核心部分的熔点低的金属材料镀上规定量，而形成突起电极的电极端部，
加热上述半导体芯片，通过仅使上述突起电极的电极端部熔化，在电极端部赋予为形成该电极端部与所使用的金属材料量相对应的圆形，
在对置基板的被封装面或半导体芯片上供给未固化状态的绝缘性粘接剂，
通过将上述半导体芯片上的突起电极相对于对置基板上的对置电极进行加热压接，并在该状态下保持规定的时间，在对置基板和对置电极上形成凹部，于是通过该对置电极的凹部和突起电极的电极端部的吻合，进行两电极的电连接，以及
保持该状态，使上述绝缘性粘接剂进行充分的固化，将上述半导体芯片和上述对置基板牢固地粘接在一起。
6.一种半导体器件的封装体的制造方法，其特征在于，包括以下步骤：
使用溅射法在半导体芯片的表面上形成阻挡金属层，在该阻挡金属层的上层，在除构成上述半导体芯片的片状电极的上方部分的区域形成电镀抗蚀膜，
在上述电镀抗蚀膜未覆盖的、上述片状电极上方的阻挡金属层的上层，通过使用以该阻挡金属层作为电极膜的电镀法镀上规定的金属，而形成突起电极的核心部分，
通过电镀具有比上述核心部分的熔点低的金属软钎料镀上规定量的软钎料，而形成突起电极的电极端部，
通过将载置上述半导体芯片的基板在加热的加热板上放置规定的时间，利用从上述基板传导的热量仅使上述突起电极的电极端部熔化，从而在电极端部赋予为形成电极端部与使用的金属软钎料量相对应的圆形，
用抗蚀膜剥离液剥离电镀抗蚀膜，使阻挡金属层露出，对露出的阻挡金属层进行蚀刻，
在对置基板的被封装面或半导体芯片上供给未固化状态的绝缘性粘接剂，
通过将上述半导体芯片上的突起电极相对于对置基板上的对置电极进行加热压接，并在该状态下保持规定的时间，在对置基板和对置电极上形成凹部，于是通过该对置电极的凹部和突起电极的电极端部的吻合，进行两电极的电连接，以及
使上述绝缘性粘接剂进行固化，将上述半导体芯片和上述对置基板粘接在一起。
7.一种半导体芯片的突起电极的形成方法，其特征在于，包括以下步骤：
在构成半导体芯片的片状电极的上部形成突起电极的核心部分，
在包含上述核心部分的半导体芯片上形成电镀抗蚀膜，
在应用光刻掩模、在上述电镀抗蚀膜上进行蚀刻时，通过多阶段地变化照射光量，使上述核心部分的上方的电镀抗蚀膜的厚度形成多阶梯状，
通过对上述多阶梯厚度的电镀抗蚀膜进行干蚀刻，使上述核心部分形成阶梯状的形状体，
使用电镀法在做成上述阶梯状的核心部分上形成电极端部，
通过软熔工序使上述电极端部成为圆形，以及
使用电镀法在上述电极端部形成电极覆膜。
CNB028071484A 2001-03-26 2002-03-25 半导体器件的封装体及其制造方法 Expired - Fee Related CN1246891C (zh)

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