CN1462088A - 射频电路制造方法与射频电路 - Google Patents

射频电路制造方法与射频电路 Download PDF

Info

Publication number
CN1462088A
CN1462088A CN02140614A CN02140614A CN1462088A CN 1462088 A CN1462088 A CN 1462088A CN 02140614 A CN02140614 A CN 02140614A CN 02140614 A CN02140614 A CN 02140614A CN 1462088 A CN1462088 A CN 1462088A
Authority
CN
China
Prior art keywords
circuit
radio circuit
metal substrate
radio
cavity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN02140614A
Other languages
English (en)
Inventor
小仓洋
高桥和晃
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of CN1462088A publication Critical patent/CN1462088A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P11/00Apparatus or processes specially adapted for manufacturing waveguides or resonators, lines, or other devices of the waveguide type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P5/00Coupling devices of the waveguide type
    • H01P5/08Coupling devices of the waveguide type for linking dissimilar lines or devices
    • H01P5/10Coupling devices of the waveguide type for linking dissimilar lines or devices for coupling balanced lines or devices with unbalanced lines or devices
    • H01P5/107Hollow-waveguide/strip-line transitions
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/44Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6605High-frequency electrical connections
    • H01L2223/6627Waveguides, e.g. microstrip line, strip line, coplanar line
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01087Francium [Fr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/141Analog devices
    • H01L2924/1423Monolithic Microwave Integrated Circuit [MMIC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15192Resurf arrangement of the internal vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1903Structure including wave guides
    • H01L2924/19032Structure including wave guides being a microstrip line type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0237High frequency adaptations
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/05Insulated conductive substrates, e.g. insulated metal substrate
    • H05K1/056Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0364Conductor shape
    • H05K2201/037Hollow conductors, i.e. conductors partially or completely surrounding a void, e.g. hollow waveguides
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/0969Apertured conductors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227Other objects, e.g. metallic pieces
    • H05K2201/10371Shields or metal cases
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06Lamination
    • H05K2203/063Lamination of preperforated insulating layer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/30Details of processes not otherwise provided for in H05K2203/01 - H05K2203/17
    • H05K2203/308Sacrificial means, e.g. for temporarily filling a space for making a via or a cavity or for making rigid-flexible PCBs
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0058Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H05K3/0061Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10Methods of surface bonding and/or assembly therefor
    • Y10T156/1052Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Waveguides (AREA)

Abstract

本发明揭示了一种具有膜结构的射频电路及其制造方法。该射频电路的电路单元形成在其两面或一面粘合了铜的绝缘材料板上,从而把带空腔的金属基板与形成电路单元的绝缘材料板接合在一起。电路单元装有有源元件,其上粘合带间壁的盖以封装。形成膜结构的金属基板中的空腔由压制机冲切形成。由于金属基板不是湿法蚀刻,所以能容易地对金属基板的空腔作精密的尺度控制。另外,还能缩短对空腔区的加工时间。

Description

射频电路制造方法与射频电路
技术领域
本发明涉及一种用绝缘材料层叠在铜或铝等金属基板上的金属芯基板制造的射频电路,尤其涉及在微波或毫米波段高频范围制造射频电路的方法和这种射频电路。
背景技术
绝缘材料层叠在铜或铝等金属基板上的金属芯基板,是众所周知的一种射频电路基板,已由Mitsubishi Resin公司以Diacore品名出售。用这种金属芯基板制造的射频电路,可从金属基板散热,可将射频电路制成具有高散热特性。在用金属芯基板制造射频电路时,根据与容纳该射频电路的外壳的关系,铜或铝的厚度约为100μm或更大,一般为500μm~3mm。
图1示出一例应用金属芯基板的射频电路。该射频电路由绝缘材料102、传输线103和通孔104构成。绝缘材料102形成与铜或铝等金属基板101上,介质损耗小;传输线103形成于绝缘材料102上;通孔104形成在金属基板101与传输线103之间作电气与热导连接的导体。当在微波或毫米波段高频范围内制作射频电路时,为减小传输线的介质损耗,选用的绝缘材料具有低介质损耗(低介质损耗正切)特性,如聚酰亚胺或聚四氟乙烯。
为了以膜结构制作射频电路,可在金属基板101中形成空腔105,同时可把波导接至空腔105,而该波导发射从天线输入的信号,由此构成的转换器可以把膜结构电路从波导转入平面电路。
然而,在金属基板101中形成空腔105时,通常在基板101上形成一掩膜以进行蚀刻而形成空腔105。一般难以把空腔105形成期望的形状,即空腔105应在形式上各向同性并被蚀刻成有点朝向掩膜内部。另外,当金属基板101厚度为1mm时,若金属基板101上的蚀刻速率为5μm/分钟,加工时间长达3小时20分钟,故不认为该方法是一种有效的加工方法。
另一种方法是在金属基板101中预先设置好空腔105,以便热压绝缘材料102。但在该方法中,绝缘材料102流入金属基板101的空腔105中,难以获得适宜的膜结构。
发明内容
本发明鉴于上述而作出,其目的是提供一种便于制造膜结构型射频电路的方法。
本发明的射频电路制造方法包括下述步骤:第一步,用绝缘材料形成电路,该绝缘材料的两面或一面粘附有铜等金属;第二步,把有空腔的金属基板与第一步骤制作的电路接合在一起;第三步,在电路上安装有源元件;和第四步,把第三步骤制作的电路与带间壁的盖连接起来。
置于盖上的间壁形成于盖外周而包绕射频电路,根据需要,盖内部为真空、充填惰性气体或氮气。
根据需要,金属基板在其内部形成有空腔的凸形突出部分。
绝缘材料较佳地在1GHZ时具有0.003或更小的介电损失正切值。
本发明另一种制造射频电路的方法包括下述步骤:第一步,用膜具冲切金属基板,形成空腔;第二步,对膜具冲切的金属小板用等离子体或臭氧作表面处理或清洁;第三步,把表面处理过的金属小板插入金属基板空腔里;和第四步,把形成电路的绝缘材料配置在金属基板上,再热压接合。
附图说明
图1是使用普通金属芯基板的膜结构射频电路的剖面图;
图2是示出本发明第一实施例的射频电路的剖面图;
图3是本发明第一实施例除去盖的射频电路平面图,其中图3A是从下面观看的盖的平面图,图3B是射频电路除去盖后的平面图;
图4是本发明第一实施例的射频电路盖的透视图;
图5A~5D是示出本发明第一实施例的射频电路的电路制造工艺的剖面图;
图6是本发明第二实施例的射频电路的剖面图;
图7是本发明第三实施例的射频电路的剖面图;
图8是本发明第四实施例的射频电路的剖面图;
图9是本发明第五实施例的射频电路的剖面图;
图10是本发明第五实施例射频电路盖的透视图;
图11是本发明第六实施例射频电路的剖面图;
图12是本发明第六实施例底面侧射频电路的透视图;
图13是本发明第六实施例射频电路与另一射频电路连接后的剖面图;
图14A~14F是示出本发明第七实施例的射频电路制造方法过程的剖面图;
图15A~15F是示出本发明第八实施例的射频电路制造方法过程的剖面图;
图16A~16E是示出本发明第九实施例的射频电路制造方法过程的剖面图;和
图17A~17E是示出本发明第十实施例的射频电路制造方法过程的剖面图;
具体实施方式
下面参照附图示出本发明诸示例实施例。
1.第一示例实施例
图2示出一例用本发明的射频电路制造方法制作的射频电路。金属基板1是铜、含铜合金或铝,厚度为100μm或更大,一般为500μm或更大,上面形成绝缘板2。绝缘板2由低介电损失(约0.05或更小)的绝缘材料形成。在制作用于微波或毫米波段的高频段的射频电路时,在1GHZ测量频率下,作为一种材料特性,绝缘板2的介电损失正切值较佳为约0.003或更小。以介电损失来衡量,若该值很大,就难以构成一种有用的电路作为本发明要应用的用于微波或毫米波段的高频范围的高频电路。例如,称为FR-4的玻璃环氧基绝缘材料是一种普通的电路基板绝缘材料,其介电损失正切值在1GHZ测量频率下约为0.02,作为一种用于在微波或毫米波段上制作高频电路的绝缘材料,不会优选这种材料。因此,为减小传输线上的介电损失,要选用低介电损失特性(低介电损失正切)的材料作为绝缘板2,如聚酰亚胺、聚四氟乙烯、液晶聚合物或苯并环丁烯。
绝缘板2的两面形成有传输线3,如微带线,共面带线、槽线或接地线。同时,绝缘板2还形成有被导体埋置的空腔。这样,形成的通孔4以电气与热导方式在绝缘板2相对两面的传输线3之间作连接。金属基板1的空腔5作为波导提供膜结构。在绝缘板2上表面上,传输线3有一高频电路图案,可在其上安置有源元件6,如MMIC(毫米波(或微波)单块集成电路)、HBT(异质结双极性晶体管)或HEMT(高电子迁移率晶体管)。有源元件6与传输线3通过导线7连接而构成期望的高频电路。盖8接合在绝缘板2上表面的传输线3上,覆盖着整个高频电路起到电磁屏作用。一部分传输线3伸出盖8对外部装置提供连接端子。
图3A是图2的射频电路在除去盖子8后从下面观看该射频电路时的平面图,图3B是射频电路除去盖8后从上面观看的平面图。阴影区示出图2的传输线3,虚线5表示形成于图2金属板1里的空腔5位于绝缘板2下面的区域中。作为波导的空腔5、槽线19与盖8构成波导—平面线转换电路。
图4中,把图3A的盖8示为透视图。在图3A和4中,阴影区是与图3B的射频电路直接接触的区域,该区域构成的间壁9对应于传输线3与有源元件6。间壁9专用于抑制有源元件6辐射的不希望有的无线电波。除了防止不需要的无线电波朝射频电路外面辐射外,还可防止无线电波在有源元件6之间互干扰,因而可提高整个射频电路的可靠性。
而且,尽管未作图示,需要时可在间壁9下表面装上无线电波吸收器,以进一步提高射频电路的可靠性。
现在参照图5A~5D说明图2~4所示射频电路的制造方法。
图5A示出了制造电路基板的工艺,即在低损耗绝缘板2的两面形成传输线3和通孔4,通孔4形成一导体在两面传输线3之间作电气与热导连接。绝缘板2和传输线3使用一种片状材料,市场上称为两面附铜的层压板。通过钻孔、激光或蚀刻,可在对应于通孔4的位置上的穿孔以打通该层压板,再在穿孔中埋置连接导体而形成通孔4。
图5B示出的工艺是把以图5A的工艺制作的电路基板接合到预先形成有空腔5的金属基板1上。在金属基板1中形成空腔5的方法,可以使用铣削或冲压等机械加工,在加工效率方面,冲压法最有效。
把图5A工艺制作的电路基板与金属基板1接合起来的方法,可以应用使用高电导或热导粘结剂或接合剂的接合工艺,或者应用加热与加压直接或通过具有电导率或热导率的热塑或热固膜,把它们接合起来。
通过如此分别制作有空腔5的金属基板1与电路基板再把它们接合在一起,可在短时间内在金属基板中形成期望形状的空腔5。此外,由于不用蚀刻,可以明显减少制作射频电路的时间。
图5C示出的工艺用线焊技术将有源元件6电气连接到传输线3上。顺便提一下,有源元件6与传输线3之间可用倒装片安装法代替引线接合技术实现电气连接。
图5D的工艺可将盖8接合于电路基板。虽然接合方法可以与上述在电路基板与金属基板1之间作接合的方法相似,但是有效的接合方法尤其是用施加器向间壁9(图4中盖8的阴影区)施加膏状环氧基粘结剂,粘合后再热固。
这样,实施例1能以简单的方法制作精密形状的膜结构射频电路,解决了应用金属芯基板所存在的问题,并且还提高了射频电路的制作效率。
用该法制造的射频电路可应用于无线电终端、基站设备、无线电测量设备、雷达设备等,从而可制得可靠的设备。
2.第二示例实施例
图6示出一例本发明实施例2的射频电路剖面结构。实施例2的射频电路是一个传输线3经通孔4对金属基板1接地的例子,它与图2的射频电路的差异是在金属基板1与绝缘板2之间无传输线3。制作方法与实施例1相似,但是用在一面与铜接合的层压板,代替了图5A所示在两面与铜接合的层压板,因而不再重述。
3.第三示例实施例
图7示出一例本发明实施例3的射频电路剖面结构,图7中与图6相同的元件标以同样标号且不再描述。本例中,有源元件6通过导电粘结剂18接合于传输线3上,天线10向外部设备输入输出无线电波。图中与天线10耦合的区域A构成一波导—平面线路转换器,区域A的形式是在空腔5上面有介电材料2。该结构一般称为膜结构。传输线3经通孔4电气连接至作为导体的金属基板1,此时金属基板1作为传输线3的地。同时,有源元件6产生的热通过通孔4释放到金属基板1,而后者作为对外界的散热器,因而具有使微波或毫米波器件包括波导—平面线路转换器冷却的功能。
图7的射频电路若配有接在空腔5区域的天线10,就可构成一个减小全电路尺寸的波导—平面线路转换器。
4.第四示例实施例
图8示出一例本发明实施例4的射频电路剖面结构。该电路近似于图2的电路,差别在于,B区即有源元件6与绝缘材料2下面的传输线3直接接触。图8结构的射频电路可以构成一种散热效果好的射频电路,因为有源元件6产生的热可在传输线3上直接发散或通过金属基板1发散。该射频电路的制造方法与实施例1相似,但是对有源元件6设置的空腔替代了图5A工艺的通孔4,而有源元件6在图5C工艺中设置在空腔里。
根据实施例4,可以简单的方法制作一种散热特性优良的精密形状的膜结构射频电路。
5.第五示例实施例
图9示出一例本发明实施例5的射频电路剖面结构。该电路近似于图2的电路,但在C部分与图2不同。图9与图2的差别在于,绝缘材料21、22为双层形式,传输线301~303为三层形式,形成在盖8上的间壁9具有在盖8整个周边延伸的周边,如图10的透视图所示。
通过把绝缘材料2作成双层结构,被盖8覆盖的内部传输线3可通过通孔41、下层绝缘材料22上的传输线302和通孔42延伸到盖8外面的传输线303,因而延伸至外面时不触及盖8。结果,盖8的整个周边可作为与射频电路直接接合的表面。将盖8的凹槽内部抽成真空或充以氩(Ar)或氮(N2)等惰性气体,射频电路就可与外部空气隔离,从而防止有源元件6因与空气中的氧或潮气反应发生老化而劣化。对于射频电路的制造方法,可以不加变化地应用图5A~5D所示的电路制造方法。
根据实施例5,可以提供一种可靠而精密形状的膜结构射频电路。
6.第六示例实施例
图11示出一例本发明实施例6的射频电路剖面结构。该电路近似于图2的电路,差别在于,在射频电路膜区域的金属基板11中形成一凸部12。图12是图11从底面看的透视图。带凸部12的金属基板11的制造方法,虽然可用切割或蚀刻等加工法实现,但是可应用材料利用率与操作时效俱佳的压制机作深度压延。制造该射频电路的其它工艺类似于图5A~5D的工艺。
图11与12所示具有金属基板11的射频电路,在结构上便于同另一射频电路装置连接。
图13示出一例使图11的射频电路与另一射频电路连接的形式。被连接的射频电路包括天线13和内设波导区15的连接外壳14,将连接外壳14接到金属基板11,使金属基板11的凸部12耦合至外壳14的波导15。这样,对于在天线13输入或输出的无线电波16而言,金属基板11就作为波导的一部分而工作。
在该场合中,对于天线13发射和接收的无线电波16而言,该膜结构电路就作为一个波导—平面电路转换装置,把波导15转换成一种由绝缘材料2、传输线3、通孔4、有源元件与盖8构成的平面电路。
利用这种方式,实施例6有利于与图13实例所示的另一射频元件部分连接,从而缩小整个电路的尺寸。
7.第七示例实施例
图14A~14F示出的一部分射频电路制造方法工艺,用于制造包括波导—平面线路转换器在内的微波或毫米波装置。这样示出的一种工艺用于制造将金属基板与介电材料接合在一起的膜结构。
图14A是只有金属基板21的状况。图14B中,通过用模具压制,在金属板21中形成冲切穿孔22。图14C示出的状况是在冲切的金属小板23在上表面作表面处理而形成表面处理层24。表面处理层24的形成方法是加一硅基或聚四氟乙烯基表面处理材料,或涂布或蒸涂一层聚酰亚胺等有机膜。表面处理的目的在于,在后道工艺在介电材料与金属基板之间接合期间,使得带表面处理层24的金属小板23不易同介电材料接合。图14D示出的工艺是把形成有表面处理层24的金属小板23插入金属基板21的穿孔22。图14E示出的工艺是对介电材料25作热压,并把它接合到金属基板21上。此时,由于存在金属小板23,所以介电材料25在成形时不会流入金属基板21中存在的穿孔22。
由于本发明应用于微波或毫米波段的高频范围,所以本工艺使用的介电材料25必须减小介电损失。要选用低介电损失(低介电损失正切)的材料,如聚酰亚胺、聚四氟乙烯、二者的聚合物、液晶聚合物或苯并环丁烯等。
图14F的工艺是从金属基板21中取出有表面处理层24的金属小板23。金属小板23由于作过表面处理,所以很容易从金属基板21中取出,不会与介电材料25粘合。
通过执行图14A~14F所示的工艺,介电材料25便形成在具有穿孔22的金属基板21上,这样就可制造一种形状合适的膜结构和小型、高功能的微波或毫米波器件。
8.第八示例实施例
图15A~15F示出的第二种方法通过把金属基板21与介电材料25接合起来制作膜结构。图15A和15B的工艺类似于图14A和14B,区别在后道工艺。图15C的工艺是对金属基板21的表面作等离子体清洗或臭氧清洁。等离子体清洁或臭氧清洁在金属基板21的表面上形成处理层26。发明人发现,在金属基板21和介电材料25热压之前作等离子体或臭氧清洁处理,大大提高了热压后在金属基板21与介电材料25之间的粘合力。而且还确认,对介电材料25与金属基板21的接合面也作等离子体或臭氧清洁处理,进一步增大了粘合力。根据这一特点,若只对带穿孔22的金属基板21作等离子体或臭氧清洁处理而不对金属小板23作表面处理,则在图15F的工艺中可有利于使金属小板22与金属基板21分离。
等离子体清洁法包括在空气中直接辐射等离子体的大气压等离子体法、在真空中作等离子体处理的平行板等离子体蚀刻法和反应离子蚀刻法。反应等离子体蚀刻法的清洁效果最大。举例来说,应用反应等离子体蚀刻法的清洁条件包括:O2和CF4气体的混合比为4∶1,气体总流速为50sccm,真空度为20Pa,射频功率(13.56MHZ)为1.2w/cm2,等离子体辐射时间为30秒。在这些条件下,可确保图15E中金属基板21与介电材料25之间的粘合力。可以认为,粘合力提高的原因如下。即,金属基板21表面上因暴露于空气而沉积的碳等污染物,可用等离子体除去。
顺便提一下,除了反应等离子体蚀刻法外,还可应用感应耦合等离子体蚀刻等方法。
除了用等离子体清洁外,用臭氧清洁也有效。臭氧清洁法是在把要清洁的金属基板与介电材料放在充O2气的容器里之后,对O2气辐射紫外光而使O2气臭氧化,由此对它激活,使之与金属基板和介电材料上沉积的碳等发生反应,从而将它们除去。
图15D和后面的图的工艺几乎与图14D和后面的图的工艺相同,图15D是将金属小板23送回金属基板21,图15E是用热压法把金属基板21与介电材料25接合起来,而图15F是取出金属小板23。在图15F中,金属基板21未作等离子体或臭氧清洁处理,因而容易分离而不与介电材料25粘合。
9.第九示例实施例
图16A~16E是本发明实施例9的射频电路制造方法的工艺图。图16A是用实施例7或8的方法制作的膜结构。图16B示出对介电材料25中的通孔形成穿孔27的工艺。穿孔27的形成方法最好应用具有紫外光激光振荡波长的激光加工法,因为直径为0.03mm或更小的通孔很难用钻孔法实现。同时,干法蚀刻的蚀刻速率约为0.5~2μm/min,当介电材料厚100μm时,要加工50~200分钟,还要做掩膜形成处理。因此,这些方法都不认为是实用的形成方法。在激光加工中,可用普通二氧化碳气体激光器加工,其缺点是因是热加工会在介电膜中形成热劣化层。另一方面,在具有紫外光激光振荡波长的激光加工法中,如在受激准分子或YAG激光三次谐波中,由于加工机理以介电材料消融为主,可以抑制对介电材料的热损害。
图16c的工艺用于形成传输线28,包括在穿孔27中形成导体。传输线形成可以组合电镀、金属膜溅射、光刻胶形成/曝光/显影、导电膏形成等方法实现。形成在穿孔27里的导体形成通孔29。
图16D是安装MMIC、HBT或HEMT等有源元件30的工艺。在传输线28(在电气上不与另一传输线连接)上形成导电粘结剂31后,在其上安装有源元件30。导电粘结剂31用热固等方法硬化。通过导线32与另一传输线28作电气连接。
最后,用导电膏粘合用作屏蔽的盖33,如图16E所示
10.第十示例实施例
图17A~17E是一种射频电路制造方法,其工艺与图16A~16E相似,差别在于有源元件30直接装在金属基板21上。
图17A与图16A相同,是一种用实施例7或8的方法制造的膜结构。图17B的工艺用于在介电材料25中为通孔形成穿孔27,并形成安装有源元件30的空间35。穿孔27与空间35的形成方法最好应用具有紫外光激光振荡波长的激光加工,理由与实施例9所述的相同。
图17c的工艺用图16c同样的方法形成传输线28。图17D的工艺将有源元件30直接装在金属基板21上,方法与图16D相同。
通过将有源元件30直接装在金属基板21上,在制作包括波导—平面线路转换器的微波或毫米波装置时,有源元件30发出的热可直接释放到散热性高的金属基板21,从而提供可靠的微波或毫米波装置。同时,通过把有源元件30直接装在金属基板21上,可以明显缩短导线32,例如若介电材料25的厚度为100μm,有源元件30的厚度也为100μm。通过缩短导线32的长度,可抑制电路阻抗调制,从而可制作优质的微波或毫米波装置。
11.第十一示例实施例
在实施例1~10中,金属基板1、11、21若使用铜或含铜合金材料,在环境上是有利的,因为铜便于用氯化铜或氯化铁回收。近年来,已在推进电子器械回收工作,应用便于回收的铜作为金属基板,对于包括波导—平面线路转换器的微波或毫米波装置以及通信终端、基站设备、无线电测量设备与应用这种装置的雷达设备而言,增强了回收能力。
同时,在实施例6中将铜用作金属基板11材料的场合中,由于铜的延压性高,所以便于实现深度压延。

Claims (23)

1.一种具有膜结构的射频电路的制造方法,其特征在于,该制造方法包括以下步骤:
在金属基板中形成一空腔;
在绝缘材料板上形成电路单元,所述绝缘材料板的两面或一面接合有铜;
把具有空腔的金属基板与形成有电路单元的绝缘材料板接合在一起;
在所述电路单元上安装有源元件;和
把具有间壁的盖接合到装有有源元件的电路上。
2.如权利要求1所述的制造射频电路的方法,其特征在于,在绝缘材料板上形成电路单元的步骤包括以下步骤:
在其两面或一面接合有铜的绝缘材料板上形成电路图案;
在对应于通孔的位置形成穿孔;和
在穿孔中埋置连接导体,形成通孔。
3.如权利要求2所述的制造射频电路的方法,其特征在于,还包括在安装有源元件的位置上形成空腔的步骤。
4.如权利要求2所述的制造射频电路的方法,其特征在于,在对应于通孔的位置形成穿孔的步骤,是用紫外光激光加工、钻孔与干法蚀刻之一实现的。
5.如权利要求3所述的制造射频电路的方法,其特征在于,在安装有源元件的位置形成空腔的步骤,是用紫外光激光加工、钻孔与干法蚀刻之一实现的。
6.一种具有膜结构的射频电路的制造方法,其特征在于,该制造方法包括下述步骤:
第一步,用模具冲切金属基板而形成空腔;
第二步,对第一步冲切的金属小板作表面处理;
第三步,把第二步表面处理过的金属小板插入金属基板空腔内;和
第四步,在金属基板上设置绝缘材料,再将它们通过热压而接合在一起。
7.如权利要求6所述的制造射频电路的方法,其特征在于,对金属小板作表面处理的步骤,是施加硅或聚四氟乙烯系的表面处理材料的步骤。
8.如权利要求6所述的制造射频电路的方法,其特征在于,对金属小板作表面处理的步骤,是涂布或蒸涂有机膜的步骤。
9.如权利要求9所述的制造射频电路的方法,其特征在于,对金属小板作表面处理的步骤,是用等离子体或臭氧清洁的步骤。
10.一种膜结构型射频电路,其特征在于包括:
包含传输线的电路图案,所述图案形成在其两面或一面接合了铜的绝缘材料板上;
其有源元件装在电路图案预定位置的电路单元;
其空腔耦合至电路单元的金属基板;和
耦合成覆盖电路单元预定位置的盖。
11.如权利要求10所述的射频电路,其特征在于,所述绝缘材料板有一层或两层或更多层。
12.如权利要求10所述的射频电路,其特征在于,所述盖外周还包括围绕射频电路的间壁。
13.如权利要求10所述的射频电路,其特征在于,所述金属基板是一种带凸出部的形式,凸出部里面有一空腔。
14.如权利要求10所述的射频电路,其特征在于,还包括形成于空腔区的波导和耦合至波导的天线。
15.如权利要求10所述的射频电路,其特征在于,还包括连接至所述射频电路的第二射频电路,所述第二射频电路具有内设天线与波导部件的连接外壳,连接外壳的波导部件连接成与金属基板的凸出部相耦合。
16.如权利要求10所述的射频电路,其特征在于,所述绝缘材料板的介电损失正切在1GHZ时为0.003或更小。
17.如权利要求10所述的射频电路,其特征在于,所述绝缘材料板是液晶聚合物、苯并环丁烯、含聚四氟乙烯聚酰亚胺之一。
18.如权利要求10所述的射频电路,其特征在于,所述金属基板材料是铜或含铜合金。
19.如权利要求10所述的射频电路,其特征在于,所述盖内部为真空态或充有惰性气体或氮气。
20.一种装有膜结构射频电路的无线电终端设备,其特征在于包括:
一种包括传输线的电路图案,所述图案形成在其两面或一面接合了铜的绝缘材料板上;
一种其有源元件装在电路图案预定位置的电路单元;
其空腔耦合至电路单元的金属基板;和
耦合成覆盖住电路单元预定位置的盖。
21.一种装有膜结构型射频电路的无线电基站设备,其特征在于包括:
一种包含传输线的电路图案,所述图案形成在其两面或一面接合了铜的绝缘材料板上;
一种其有源元件装在电路图案预定位置的电路单元;
其空腔耦合至电路单元的金属基板;和
耦合成覆盖住电路单元预定位置的盖。
22.一种装有膜结构型射频电路的无线电测量设备,其特征在于包括:
一种包含传输线的电路图案,所述图案形成在其两面或一面接合了铜的绝缘材料板上;
一种其有源元件装在电路图案预定位置的电路单元;
其空腔耦合至电路单元的金属基板;和
耦合成覆盖住电路单元预定位置的盖。
23.一种装有膜结构型射频电路的雷达设备,其特征在于包括:
一种包含传输线的电路图案,所述图案形成在其两面或一面接合了铜的绝缘材料板上;
一种其有源元件装在电路图案预定位置的电路单元;
其空腔耦合至电路单元的金属基板;和
耦合成覆盖住电路单元预定位置的盖。
CN02140614A 2001-07-05 2002-07-05 射频电路制造方法与射频电路 Pending CN1462088A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2001204331 2001-07-05
JP2001204331 2001-07-05
JP2002103297A JP2003086728A (ja) 2001-07-05 2002-04-05 高周波回路の製作方法及びそれを用いた装置
JP2002103297 2002-04-05

Publications (1)

Publication Number Publication Date
CN1462088A true CN1462088A (zh) 2003-12-17

Family

ID=26618178

Family Applications (1)

Application Number Title Priority Date Filing Date
CN02140614A Pending CN1462088A (zh) 2001-07-05 2002-07-05 射频电路制造方法与射频电路

Country Status (6)

Country Link
US (1) US20030024633A1 (zh)
EP (1) EP1274149A3 (zh)
JP (1) JP2003086728A (zh)
KR (1) KR20030005024A (zh)
CN (1) CN1462088A (zh)
TW (1) TW543118B (zh)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101578697B (zh) * 2007-03-14 2011-12-28 三菱电机株式会社 高频封装件
CN102623416A (zh) * 2012-04-24 2012-08-01 苏州远创达科技有限公司 一种射频功放模块的功率器件无封装结构及其组装方法
CN104078766A (zh) * 2013-03-29 2014-10-01 富士通天株式会社 天线设备和雷达设备
CN105555018A (zh) * 2016-02-16 2016-05-04 广东欧珀移动通信有限公司 一种印刷电路板及电子终端
CN101809818B (zh) * 2007-10-03 2017-02-22 波音公司 具有金属波导板的先进的集成天线印刷线路板
CN107479034A (zh) * 2017-08-18 2017-12-15 华进半导体封装先导技术研发中心有限公司 雷达组件封装体及其制造方法
CN107546181A (zh) * 2017-08-18 2018-01-05 华进半导体封装先导技术研发中心有限公司 雷达组件封装体
CN107548244A (zh) * 2017-08-30 2018-01-05 景旺电子科技(龙川)有限公司 一种双面夹芯铜基板内部铜基之间绝缘的制作方法
US9941242B2 (en) 2012-04-24 2018-04-10 Innogration (Suzhou) Co., Ltd. Unpacked structure for power device of radio frequency power amplification module and assembly method therefor
TWI659518B (zh) * 2017-05-18 2019-05-11 矽品精密工業股份有限公司 電子封裝件及其製法
CN110010485A (zh) * 2018-10-10 2019-07-12 浙江集迈科微电子有限公司 一种具有光路转换功能的密闭型光电模块制作工艺

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004071670A (ja) * 2002-08-02 2004-03-04 Fuji Photo Film Co Ltd Icパッケージ、接続構造、および電子機器
US7336221B2 (en) * 2004-03-26 2008-02-26 Mitsubishi Denki Kabushiki Kaisha High frequency package, transmitting and receiving module and wireless equipment
JP4064403B2 (ja) * 2005-01-18 2008-03-19 シャープ株式会社 半導体装置、表示モジュール、半導体チップ実装用フィルム基板の製造方法、及び半導体装置の製造方法
JP2006253953A (ja) * 2005-03-09 2006-09-21 Fujitsu Ltd 通信用高周波モジュールおよびその製造方法
JP4101814B2 (ja) 2005-03-15 2008-06-18 富士通株式会社 高周波モジュール
JP4503476B2 (ja) * 2005-03-29 2010-07-14 株式会社ホンダエレシス 高周波線路−導波管変換器
JP4394147B2 (ja) * 2006-02-06 2010-01-06 三菱電機株式会社 高周波モジュール
WO2007091329A1 (ja) * 2006-02-10 2007-08-16 Fujitsu Limited 電子部品パッケージ
JP4912716B2 (ja) * 2006-03-29 2012-04-11 新光電気工業株式会社 配線基板の製造方法、及び半導体装置の製造方法
EP1923950A1 (en) 2006-11-17 2008-05-21 Siemens S.p.A. SMT enabled microwave package with waveguide interface
DE102006061248B3 (de) * 2006-12-22 2008-05-08 Siemens Ag Leiterplatte mit einem Hochfrequenzbauelement
DE102007019098B4 (de) * 2007-04-23 2020-02-13 Continental Automotive Gmbh Modul für eine integrierte Steuerelektronik mit vereinfachtem Aufbau
US7855685B2 (en) * 2007-09-28 2010-12-21 Delphi Technologies, Inc. Microwave communication package
JP2009160988A (ja) * 2007-12-28 2009-07-23 Omron Corp 検出装置および方法、並びに、プログラム
EP2315310A3 (en) * 2008-04-15 2012-05-23 Huber+Suhner AG Surface-mountable antenna with waveguide connector function, communication system, adaptor and arrangement comprising the antenna device
EP2159558A1 (en) * 2008-08-28 2010-03-03 Sensirion AG A method for manufacturing an integrated pressure sensor
US8587482B2 (en) * 2011-01-21 2013-11-19 International Business Machines Corporation Laminated antenna structures for package applications
EP2618421A1 (en) * 2012-01-19 2013-07-24 Huawei Technologies Co., Ltd. Surface Mount Microwave System
CN203279336U (zh) * 2013-04-27 2013-11-06 中兴通讯股份有限公司 一种内散热的终端
JP6372113B2 (ja) * 2014-03-17 2018-08-15 富士通株式会社 高周波モジュール及びその製造方法
JP6520281B2 (ja) * 2015-03-24 2019-05-29 富士通株式会社 電子機器筐体
US10470297B2 (en) 2015-10-06 2019-11-05 Sumitomo Electric Printed Circuits, Inc. Printed circuit board and electronic component
US10325850B1 (en) * 2016-10-20 2019-06-18 Macom Technology Solutions Holdings, Inc. Ground pattern for solderability and radio-frequency properties in millimeter-wave packages
DE102018203106A1 (de) 2018-03-01 2019-09-05 Conti Temic Microelectronic Gmbh Radarsystem zur Umfelderfassung eines Kraftfahrzeugs mit einer Kunststoffantenne

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1512605A (en) * 1976-08-05 1978-06-01 Standard Telephones Cables Ltd Microwave integrated printed circuits
DE3129425A1 (de) * 1981-07-25 1983-02-10 Richard Hirschmann Radiotechnisches Werk, 7300 Esslingen Mikrowellenantenne fuer zirkularpolarisation
GB2139818B (en) * 1983-05-12 1986-10-22 Marconi Electronic Devices High frequency transmission device
JPS6271301A (ja) * 1985-09-25 1987-04-02 Matsushita Electric Ind Co Ltd マイクロ波集積回路装置
TW300345B (zh) * 1995-02-06 1997-03-11 Matsushita Electric Ind Co Ltd
DE19805911A1 (de) * 1998-02-13 1999-08-19 Cit Alcatel Übergang von einer Mikrostripleitung zu einem Hohlleiter sowie Verwendung eines solchen Übergangs
EP1221181A4 (en) * 1999-09-02 2003-03-19 Commw Scient Ind Res Org INPUT STRUCTURE FOR ELECTROMAGNETIC SEMICONDUCTORS
JP2001230606A (ja) * 2000-02-15 2001-08-24 Matsushita Electric Ind Co Ltd マイクロストリップ線路と、これを用いたマイクロ波装置

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101578697B (zh) * 2007-03-14 2011-12-28 三菱电机株式会社 高频封装件
US8130513B2 (en) 2007-03-14 2012-03-06 Mitsubishi Electric Corporation Radio-frequency package
CN101809818B (zh) * 2007-10-03 2017-02-22 波音公司 具有金属波导板的先进的集成天线印刷线路板
CN102623416A (zh) * 2012-04-24 2012-08-01 苏州远创达科技有限公司 一种射频功放模块的功率器件无封装结构及其组装方法
WO2013159612A1 (zh) * 2012-04-24 2013-10-31 苏州远创达科技有限公司 一种射频功放模块的功率器件无封装结构及其组装方法
US9941242B2 (en) 2012-04-24 2018-04-10 Innogration (Suzhou) Co., Ltd. Unpacked structure for power device of radio frequency power amplification module and assembly method therefor
CN102623416B (zh) * 2012-04-24 2015-09-02 苏州远创达科技有限公司 一种射频功放模块的功率器件无封装结构及其组装方法
US9491864B2 (en) 2012-04-24 2016-11-08 Innogration (Suzhou) Co., Ltd. Unpacked structure for power device of radio frequency power amplification module and assembly method therefor
US9543643B2 (en) 2013-03-29 2017-01-10 Fujitsu Ten Limited Antenna device and radar device
CN104078766A (zh) * 2013-03-29 2014-10-01 富士通天株式会社 天线设备和雷达设备
CN104078766B (zh) * 2013-03-29 2020-06-09 富士通天株式会社 天线设备和雷达设备
CN105555018A (zh) * 2016-02-16 2016-05-04 广东欧珀移动通信有限公司 一种印刷电路板及电子终端
TWI659518B (zh) * 2017-05-18 2019-05-11 矽品精密工業股份有限公司 電子封裝件及其製法
CN107479034A (zh) * 2017-08-18 2017-12-15 华进半导体封装先导技术研发中心有限公司 雷达组件封装体及其制造方法
CN107546181A (zh) * 2017-08-18 2018-01-05 华进半导体封装先导技术研发中心有限公司 雷达组件封装体
CN107479034B (zh) * 2017-08-18 2019-10-18 华进半导体封装先导技术研发中心有限公司 雷达组件封装体及其制造方法
CN107548244A (zh) * 2017-08-30 2018-01-05 景旺电子科技(龙川)有限公司 一种双面夹芯铜基板内部铜基之间绝缘的制作方法
CN110010485A (zh) * 2018-10-10 2019-07-12 浙江集迈科微电子有限公司 一种具有光路转换功能的密闭型光电模块制作工艺

Also Published As

Publication number Publication date
EP1274149A2 (en) 2003-01-08
US20030024633A1 (en) 2003-02-06
TW543118B (en) 2003-07-21
KR20030005024A (ko) 2003-01-15
JP2003086728A (ja) 2003-03-20
EP1274149A3 (en) 2003-10-01

Similar Documents

Publication Publication Date Title
CN1462088A (zh) 射频电路制造方法与射频电路
CN1224301C (zh) 高频模块
US7504721B2 (en) Apparatus and methods for packaging dielectric resonator antennas with integrated circuit chips
CN1319422C (zh) 混合模块及其制造方法与其安装方法
CN1190113C (zh) 陶瓷叠层器件
US8969132B2 (en) Device package and methods for the fabrication thereof
US20030076663A1 (en) Thermal conductive board, method of manufacturing the same, and power module with the same incorporated therein
CN1623229A (zh) 高频组件及其制造方法
CN1476633A (zh) 高频模件板装置
CN1873666A (zh) 无线ic标签和无线ic标签的制造方法
CN1595649A (zh) 电子元件模件及其制造方法
CN101048863A (zh) 电子部件模块以及无线通信设备
CN1174475C (zh) 用于制造具有声表面波单元的射频模块元件的方法
CN101690442A (zh) 具有屏蔽及散热性的高频模块及其制造方法
CN1770649A (zh) 便携式电话机用高频模块
JP2003197835A (ja) 電力増幅モジュール及び電力増幅モジュール用要素集合体
CN1298080C (zh) 具有内建接地面的多段平面天线
CN100352317C (zh) 电子元件安装板、电子元件模块、制造电子元件安装板的方法及通信设备
CN1252682A (zh) 混合型模块
CN1799164A (zh) 平行平板线型元件、电路板
CN1328710A (zh) 具有包含矩形同轴传输线的平衡变换器的微波混频器
JP2003347460A (ja) 電子装置
US6264785B1 (en) Mounting structure of electric part and mounting method thereof
Hu et al. Advanced development in packaging of antenna-integrated systems for millimeter-wave applications
Amey et al. Ceramic technology for integrated packaging for wireless

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication