CN1444272A - 一种半导体器件和一种制造该器件的方法 - Google Patents

一种半导体器件和一种制造该器件的方法 Download PDF

Info

Publication number
CN1444272A
CN1444272A CN03120225A CN03120225A CN1444272A CN 1444272 A CN1444272 A CN 1444272A CN 03120225 A CN03120225 A CN 03120225A CN 03120225 A CN03120225 A CN 03120225A CN 1444272 A CN1444272 A CN 1444272A
Authority
CN
China
Prior art keywords
film
semiconductor device
metal
ball portion
metal film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN03120225A
Other languages
English (en)
Other versions
CN100339986C (zh
Inventor
中岛靖之
守田俊章
松泽朝夫
友井晴一
川邉直树
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Solutions Technology Ltd
Original Assignee
Hitachi Ltd
Hitachi ULSI Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi ULSI Systems Co Ltd filed Critical Hitachi Ltd
Publication of CN1444272A publication Critical patent/CN1444272A/zh
Application granted granted Critical
Publication of CN100339986C publication Critical patent/CN100339986C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05181—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/05187—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48507—Material at the bonding interface comprising an intermetallic compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48624—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H01L2224/8503—Reshaping, e.g. forming the ball or the wedge of the wire connector
    • H01L2224/85035—Reshaping, e.g. forming the ball or the wedge of the wire connector by heating means, e.g. "free-air-ball"
    • H01L2224/85045—Reshaping, e.g. forming the ball or the wedge of the wire connector by heating means, e.g. "free-air-ball" using a corona discharge, e.g. electronic flame off [EFO]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85203—Thermocompression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H01L2224/85207—Thermosonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0496—6th Group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/201—Temperature ranges
    • H01L2924/20106—Temperature range 200 C=<T<250 C, 473.15 K =<T < 523.15K
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/203—Ultrasonic frequency ranges, i.e. KHz
    • H01L2924/20305—Ultrasonic frequency [f] 100 Khz=<f< 125 KHz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/203—Ultrasonic frequency ranges, i.e. KHz
    • H01L2924/20306—Ultrasonic frequency [f] 125 Khz=<f< 150 KHz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/203—Ultrasonic frequency ranges, i.e. KHz
    • H01L2924/20307—Ultrasonic frequency [f] 150 Khz=<f< 175 KHz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/203—Ultrasonic frequency ranges, i.e. KHz
    • H01L2924/20308—Ultrasonic frequency [f] 175 Khz=<f< 200 KHz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20752—Diameter ranges larger or equal to 20 microns less than 30 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

提供一种半导体器件，该半导体器件包括形成于半导体芯片上的第一金属膜，形成于所述第一金属膜上并由第二金属形成的球部分，以及所述第一金属和所述第二金属的合金层，该合金层在所述第一金属膜和所述球部分之间形成，其中所述合金层达到所述第一金属膜的底部，并且所述球部分用树脂覆盖；以及该半导体器件的制造方法。本发明使得能够改进键合焊盘部分和互连上键合线的球部分之间的粘附，从而提高半导体器件的可靠性。

Description

一种半导体器件和一种制造该器件的方法
技术领域
本发明涉及一种半导体器件和这种半导体器件的一种制造方法，尤其涉及一种技术，当将这种技术应用于具有用于连接半导体芯片(片状器件)和外部接线端子的丝线的半导体器件时是有效的，并且涉及该半导体器件的制造方法。
背景技术
取出电信号的输入和输出以便允许IC(集成电路)芯片起作用是必要的。为了这一目的，可用的是用金丝(键合线)连接IC芯片的键合焊盘部分和引线框架等的外部引线端子，然后用树脂密封IC芯片和金丝的封装方法。
例如，在日本专利申请公开号Hei 1(1989)-215030中公开的是一种防止裂缝(14)出现在半导体器件键合焊盘的下部的技术，这已经通过用连接线连接半导体片状器件和引线框架然后用树脂密封，通过将线端部球部分的厚度(t)和键合宽度(S)的比值(t/S)调节到0.2或更小来获得。
发明内容
本发明者已经致力于半导体器件的研究和发展，并且他们已经采用上述使用金丝和树脂的半导体器件封装方法。
例如，封装通过将金丝的一端熔化并接触键合(第一键合)到键合焊盘部分以便用金丝连接IC芯片来完成，键合焊盘部分是IC芯片Al膜(互连)的最上暴露部分；将金丝的另一端热压键合(第二键合)到布线衬底上的外部接线端子；并且用树脂密封IC芯片，金丝等。
在这种封装方法中，Al膜(互连)和金丝的端部(球部分)通过在键合焊盘部分上，在铝和金之间形成合金来连接。
由于引脚数(外部接线端子数)随LSI(大规模集成电路)功能的多样化而增加，而且趋向于LSI的高集成，这些引脚(外部接线端子)的间距变得日益狭窄。另外，由于LSI的小型化，每个互连趋向于更薄。
当上述键合方法应用于这种具有多样化功能的高集成的器件时，在用于评价(测试)半导体器件耐久性的温度循环试验之后，短路故障频繁发生。
本发明者已经进行关于这种故障的广泛研究，结果发现铝-金合金层中的破裂现象(裂缝)是故障的原因。他们继续进行进一步的研究，因为在键合焊盘部分下部的裂缝占铝-金合金层中破裂现象的主要部分，如在上述日本专利公开号Hei 1(1989)-215030中所示。如随后将详细描述的，铝-金合金层的形态不同于传统的形态。
本发明的一个目的在于改进键合焊盘部分(互连)和球部分之间的粘附，尤其是，维持互连和球部分之间足够的粘附，即使互连的膜厚度很小。
本发明的另一个目的在于通过改进互连和球部分之间的粘附来改进半导体器件的可靠性，并且改进半导体器件的成品率。
本发明的更进一步目的在于提供一种技术，将这种技术当应用于具有以小间距排列的键合焊盘的半导体器件时是合乎需要的，并且提供这种半导体器件的制造方法。
本发明的上述和新的特征将从这里的描述和附图变得明白。
接下来将简要描述由本申请公开的发明的典型。
(1)本发明的一种半导体器件具有形成于半导体芯片上的第一金属膜，形成于第一金属膜上并由第二金属形成的球部分，以及形成于第一金属膜和球部分之间以达到第一金属膜底部的第一金属和第二金属的合金层。球部分可以用树脂覆盖。球部分的高度h和球的最大外径D之间的关系可以满足下面的表达式：9≥D/h≥2。
(2)本发明的一种半导体器件具有形成于半导体芯片上的第一金属膜，形成于第一金属膜上并由第二金属形成的球部分，以及形成于第一金属膜和球部分之间的第一金属和第二金属的合金层。第一金属膜与球部分的接触区的直径d和合金层形成区域的直径g满足下面的表达式：g≥0.8d。第一金属膜与球部分的接触区的直径d和球的最大外径D可以满足下面的表达式：d≥0.8D。
(3)根据本发明的半导体器件的一种制造方法包括，在半导体芯片上的第一金属膜上形成在键合焊盘部分具有开口的绝缘膜，并且将第二金属形成的球部分通过使用具有110kHz或更大频率超声波的超声波热压键合方法粘附到键合焊盘部分上。
(4)根据本发明的半导体器件的一种制造方法包括，在半导体芯片上的第一金属膜上形成在键合焊盘部分具有开口的绝缘膜，并且通过在第一金属膜与球部分的接触区的至少70％中形成第一金属与第二金属的合金层来将形成于第一金属膜上并由第二金属形成的球部分粘附到键合焊盘部分上。在球部分用树脂覆盖或者由树脂覆盖的半导体芯片暴露于高温条件之后，可以测试半导体芯片的特性。由第二金属形成的球部分可以加工成形，使得接触区的直径d和球部分的最大外径D满足下面的表达式：d≥0.8D。
附图说明
图1是衬底的不完整横断面视图，说明根据本发明实施方案的半导体器件的制造步骤；
图2是衬底的不完整横断面视图，说明根据本发明实施方案的半导体器件的制造步骤；
图3是衬底的不完整横断面视图，说明根据本发明实施方案的半导体器件的制造步骤；
图4是衬底的不完整横断面视图，说明根据本发明实施方案的半导体器件的制造方法；
图5是衬底的不完整横断面视图，说明根据本发明实施方案的半导体器件的制造方法；
图6是衬底的不完整横断面视图，说明根据本发明实施方案的半导体器件的制造方法；
图7是衬底的不完整横断面视图，说明根据本发明实施方案的半导体器件的制造步骤；
图8是衬底的不完整横断面视图，说明根据本发明实施方案的半导体器件的制造步骤；
图9是衬底的不完整平面图，说明根据本发明实施方案的半导体器件的制造方法；
图10说明一种毛细管，该毛细管用于根据本发明实施方案的半导体器件的制造步骤中；
图11是衬底(键合焊盘部分)的不完整横断面视图，说明根据本发明实施方案的半导体器件的制造步骤；
图12是衬底(键合焊盘部分)的不完整横断面视图，说明根据本发明实施方案的半导体器件的制造步骤；
图13是显示毛细管运动的曲线图，该毛细管用于根据本发明实施方案的半导体器件的制造步骤中；
图14是衬底(键合焊盘部分)的不完整横断面视图，说明根据本发明实施方案的半导体器件的制造步骤；
图15是半导体器件键合焊盘部分的不完整横断面视图，用于说明本发明实施方案的一个优点；
图16是半导体器件键合焊盘部分的不完整横断面视图，用于说明本发明实施方案的另一个优点；
图17是半导体器件键合焊盘部分的不完整横断面视图，用于说明本发明实施方案更进一步的优点；
图18是根据本发明实施方案的半导体器件制造过程的键合焊盘部分的不完整横断面视图；
图19是半导体器件键合焊盘部分的不完整横断面视图，用于说明本发明实施方案更进一步的优点；
图20是半导体器件键合焊盘部分的不完整横断面视图，用于说明本发明实施方案更进一步的优点；
图21是显示在不同超声波频率，接触键合球部分的直径(μm)和抗剪强度(N)之间关系的曲线图；
图22是显示在不同超声波频率，超声波振幅(μm)和抗剪强度(N)之间关系的曲线图；
图23是显示在不同超声波频率，接触键合球部分的直径(μm)和合金形成区域百分比(％)之间关系的曲线图；
图24是显示键合焊盘部分的间距和Al-Au合金层形成区域的直径g与金球部分B的连接区直径d的比值(g/d)之间关系的曲线图；
图25是衬底(键合焊盘部分)的不完整横断面视图，说明根据本发明实施方案的半导体器件的制造步骤；
图26是说明毛细管运动的曲线图，该毛细管用于根据本发明实施方案的半导体器件的制造步骤中；
图27是衬底的不完整横断面视图，说明根据本发明实施方案的半导体器件的制造步骤；
图28是衬底的透视图，说明根据本发明实施方案的半导体器件的制造步骤；
图29是图28的部分放大图，说明根据本发明实施方案的半导体器件的制造步骤；
图30是衬底的透视图，说明根据本发明实施方案的半导体器件的制造过程。
具体实施方式
本发明的实施方案将在下文基于附图具体地描述。在所有用于描述下述实施方案的附图中，具有相似功能的元件将由相似的参考数字来标识，并且重复的描述将省略。
根据本发明实施方案的半导体器件(半导体集成电路器件)接下来将在它的制造方法之后描述。
如图1中所示，制备在其上形成氧化硅膜11和二级互连M2的半导体衬底1。在氧化硅膜11中，形成半导体元件例如MISFET(金属绝缘半导体场效应晶体管)，一级互连，用于连接元件和一级互连的插塞，随后将描述的用于连接一级互连和二级互连的插塞等。在半导体衬垫1中，由例如氧化硅膜做成的元件隔离根据需要形成，但是它的说明也省略了。
如图2中所示，氧化硅膜12通过CVD(化学汽相沉积)在二级互连M2上沉积作为级间绝缘膜。然后，接触孔C3通过干法刻蚀移除二级互连M2上的氧化硅膜12来形成。在氧化硅膜11上包括接触孔C3的内部，钨(W)膜，例如，通过CVD沉积作为导电膜。在接触孔C3外的W膜通过，例如，CMP(化学机械抛光)移除以便形成插塞P3。
如图3和4中所示，在氧化硅膜12上包括插塞P3顶面，大约50nm厚的TiN(一氮化钛)膜M3a，大约700nm厚的Al(铝)膜M3b和大约50nm厚的TiN膜M3c通过例如溅射依次沉积作为导电膜。在这里使用的术语“Al膜”意味着具有Al作为主要成分的膜，并且它包含Al和另一种金属的合金膜。
TiN膜M3a和M3c形成以便通过1)增强Al膜M3b和绝缘膜例如氧化硅膜12之间的粘附，或者通过2)改进由Al合金形成的二级互连M2的电迁移阻抗来保证互连的可靠性。代替TiN膜，可以使用Ti(钛)膜的单层膜，TiW(钛钨)膜，Ta(钽)膜，W膜或WN(氮化钨)膜，或者它们的复合膜。
用保护膜(没有示出)作为掩膜，TiN膜M3a，Al膜M3b和TiN膜M3c然后干法刻蚀以形成三级互连M3。图4是沿着图3的线A-A(这将同样应用于图6和8)而取的横断面视图(三级互连M3伸展方向的横断面视图)。
如图5和6中所示，氮化硅膜和氧化硅膜通过例如CVD在三级互连M3上依次沉积作为保护膜，以便形成由它们的叠片形成的钝化膜41。这一钝化膜41可以由单层形成。
如图7和8中所示，在希望的位置具有开口部分的聚酰亚胺树脂膜43在钝化膜41上形成。这一聚酰亚胺树脂膜43通过旋涂光敏聚酰亚胺树脂膜以给出大约5μm的厚度，热处理(前烘)膜，曝光并显影所得到的聚酰亚胺树脂膜以形成开口，然后热处理(后烘)膜使其硬化来形成。
用所得到的聚酰亚胺树脂膜43作为掩膜，下面的钝化膜41干法刻蚀，接着是TiN膜M3c的干法刻蚀。结果，Al膜M3b表面的一部分暴露。Al膜M3b这一暴露区称作“键合焊盘部分BP”。图9是衬底(芯片区)的不完整平面图，键合焊盘部分BP在衬底上形成。
至此所描述的步骤经常在通常所说的晶片状态下进行。在这种情况下，具有多个基本上矩形的半导体芯片区的晶片(半导体衬底)切割(切成小块)成各个半导体芯片。
然后，执行将金丝WR粘附(第一键合)到半导体芯片上的键合焊盘部分BP。这一步骤将参考图10～11来描述。
如图10中所示，制备毛细管CA，该毛细管具有沿着它的轴心，用于使金丝WR从中穿过的细孔，并且使金丝WR穿过毛细管的内部。然后，使用电焊枪(没有示出)将来自电极的放电能量施加到从毛细管CA端部露出的金丝WR，从而金丝WR熔化，球MB形成。
如图11和12中所示，熔化的球MB粘附到键合焊盘部分BP上。当从毛细管CA施加压力到熔化的球MB上并且施加超声波到毛细管CA时执行这一粘附步骤。在这一处理过程中，键合焊盘部分BP由加热器加热，加热器没有说明。这种处理方法称作“超声波热压键合方法”。当金丝WR在处理之后拉起时，金丝WR的端部保持粘附于键合焊盘部分BP上。如图12中所示，这样粘附的金丝WR的端部称作“球部分B”或者“金球部分B”。这一金球部分B和键合焊盘部分BP(Al膜M3b)通过在它们之间的接触面上形成Al-Au合金层来键合。
图13显示毛细管CA的高度(Z)和时间(T)之间的关系。如图13中所示，毛细管CA的高度在时间T0开始下降，但是这一下降率在时间T1变小。在T2期间，熔化的球MB固定到键合焊盘部分BP上，并且这一状态维持预先确定的时间(T2～T3)。这一期间称作“键合期”。然后(在时间T3及之后)，毛细管CA的高度呈现增加，并且金丝WR被拉起。如图14中所示，执行这样拉起的金丝WR到例如布线衬底60上的印刷线路(没有示出)上的超声波热压键合(第二键合)。
这里，将描述由本发明者研究的技术。
当金丝WR键合到具有大约700nm厚度(t)的Al膜M3b时，短路故障在温度循环试验之后发生。作为寻找短路位置的结果，发现裂缝在Al-Au合金层50中出现，如图15中所示。随后对Al-Au合金层50的详细分析揭示Al-Au合金层50由三层构成。它们是，从底层开始，AlAu2膜50a，Al2Au5膜50b和AlAu4膜50c(参考图16和17)。同时证实的是，在金球B和接触点部分BP(Al膜M3b)之间的接触面上，存在没有形成Al-Au合金层50的区域53。在构成Al-Au合金层50的AlAu2膜50a，Al2Au5膜50b和AlAu4膜50c中，Al2Au5最稳定。图16和17是图15中画有圆圈的区域E的放大图。
当Al膜M3b具有大约1000nm相对大的厚度时，AlAu4的存在并不确定。因此，假定Al膜M3b(互连)厚度的减小导致Al供给量的减小，从而，具有小的Al组成比的AlAu4膜在金球部分B的一侧上形成。
因此，如图16中所示，Al-Au合金层50形成时，熔合反应的不一致在Al2Au5膜50b和AlAu4膜50c之间出现，并且它变成空隙55。
考虑多个这种已经被温度循环试验扩大的空隙形成如图17中所示的裂缝，导致短路故障。在裂缝中，Al或Au的氧化物Ox形成，这推测是由于包含于密封树脂中的痕量的氧而导致，密封树脂将在随后描述。
作为这种短路的对策，用高压压平金球部分B，从而增加它与Al膜M3b的接触区域的方法可以考虑。但是，用高压压平金球部分B使得保证与相邻接触点或者其上另一个金球之间的短的裕度是不可能的，导致短路故障的增加。当键合焊盘部分BP的间距由于半导体器件的小型化而变得更小时，上述短路故障成为严重的问题。用高压压平金球部分B有时对键合焊盘造成严重的破坏，虽然依赖于键合条件。
基于上述结果，本发明者研究能够维持足够的粘接强度而不导致金球部分B形状的大改变，并且在技术标准内调节它的改变量的金球部分B的形状；以及它的制造方法。
首先，将参考附图18描述金球部分B的形状。如图18中所示，金球部分B的连接区的直径d和金球部分B的最大外径D调节成具有下面的关系：d≥0.8D。术语“连接区Ad”意味着金球部分B与Al膜M3b(互连)的接触区，而术语“连接区的直径d”意味着金球部分B与Al膜M3b(互连)的接触区的直径。
通过满足上述关系，短路裕度，和接触区可以保证。
当通过金球部分B的连接区Ad和由金球部分B的最大边界所定义的区域之间的关系来表示时，上述关系d≥0.8D相当于Ad≥0.64D。当考虑制造时键合焊盘部分的表面状况的起伏或者键合条件的波动时，关系优选地满足下面的表达式：Ad≥0.7AD。
金球部分B的高度(h)优选地落在9≥D/h≥2的范围中。当D是65μm或更小时，高度优选地是5μm或更大，但是不大于15μm。金丝的直径(宽度)WW优选地是25μm或更小。
金球部分B的连接区的直径d和Al-Au合金层50形成区域的直径g设置成满足下面的关系：g≥0.8d。
当上述关系满足时，金球部分B和Al膜M3b(互连)之间由Al-Au合金层50产生的粘接强度可以保证，从而上述空隙或裂缝的影响可以削弱，使得坏连接减少。
当通过金球部分B的连接区Ad和Al-Au合金层50所形成的区域Ag之间的关系来表示时，关系g≥0.8d相当于Ag≥0.64Ad。随后将描述的数据(图23)显示，优选地，关系满足下面的表达式：Ag≥0.7Ad。
即使Al膜M3b的厚度是例如700nm或更小，与其形成的合金(AlAu4)层具有小的Al组成比，粘接强度仍然可以保证。
当Al膜M3b薄时，Al-Au合金层50甚至延伸到Al膜M3b的底部。因此，TiN膜M3a存在于Al-Au合金层50的下面(参考图27)。
在本实施方案中，连接区的直径d，金球部分B的最大外径D和Al-Au合金层50形成区域的直径g每个不必是完美圆的直径，而只是在这些区域中每个区域的中心的线。
相反地，当金球部分键合到薄的Al膜上，使得通过设置键合温度和键合时间，使之与Al膜厚度大并且键合焊盘部分的间距相对大的情况下所研究的相似，改变毛细管和金丝直径以符合所希望的键合焊盘间距(初始的球体积)并调节键合负载和超声波施加输出，来给出所希望的接触键合球直径时，形成如图19中所示的形状。
在上述情况下，金球部分B的连接区的直径d和金球部分B的最大外径D之间的关系满足下面的表达式：d≤0.8D，而金球部分B的连接区的直径d和Al-Au合金层50形成区域的直径g之间的关系满足下面的表达式：g≤0.8d。
因此，维持金球部分B和Al膜M3b(互连)之间由Al-Au合金层50产生的足够的粘接强度变得困难。尤其是，当Al膜薄时，具有小的Al组成比的AlAu4膜形成得厚，并且由于随后将进行的温度循环试验的影响，裂缝易于在AlAu4膜的接触面上出现。
当例如，如图20中所示，键合焊盘部分BP的间距是130μm时，这种现象可能发生。但是，假定在这种情况下，短路故障被避免，因为连接区或Al-Au合金层形成区域的绝对直径维持为大。术语“键合焊盘部分BP的间距”意味着任意两个相邻键合焊盘BP的中心之间的距离。
当如图19中所示的球部分B的尺寸减小，并且应用窄间距(例如，70μm或者更小)时，坏连接出现。如果保证连接区不改变这种形状，金球部分B的连接区的直径d和金球部分B的最大外径D之间过大的差异导致短路故障。
另一方面，如图18所示的根据本实施方案的结构，使得维持金球部分B和Al膜M3b(互连)之间由Al-Au合金层产生的足够的粘接强度成为可能，并且同时，使得维持足够短路裕度成为可能。当应用于窄间距的键合焊盘部分BP或者在薄Al膜(互连)上的键合焊盘部分BP时，本实施方案的结构尤其有效。
然后，将描述形成如图18中所示的金球的键合步骤的一个例子。
例如，在键合期间(图13中的T2～T3)施加110kHz或更高的超声波，在此期间，熔化的球MB固定在键合焊盘部分BP上。
图21说明在各个超声波频率，接触键合球部分的直径(μm)和抗剪强度(N)之间的关系。键合温度设为200℃，初始的球直径设为35±5μm。术语“抗剪强度(N)”意味着当水平施加到球部分B的压力增加时，球部分B的剥落发生时的压力。
如图21中所示，当施加频率120kHz或180kHz的超声波时，抗剪强度变得比当施加频率60kHz的超声波时大。在120kHz和180kHz之间，抗剪强度在后者超声波频率时稍大。在60kHz的频率，当接触键合球直径为大约50nm时，抗剪强度为0.35N，而在180kHz的频率，相同级别(0.35N)的抗剪强度可以获得，即使当接触键合球直径小到大约42μm。
图22说明在各个超声波频率，超声波振幅(μm)和抗剪强度(N)之间的关系。如图22中所示，频率越高，振幅变得越小，呈现点振幅。振幅(μm)的减小产生减小键合损坏的效果。
从如图21中所示的抗剪试验的结果，研究接触键合球部分的直径(μm)和合金形成区域百分比(％)之间的关系。结果在图23中显示，术语“合金形成区域百分比”意味着在作为抗剪试验结果出现在键合焊盘部分BP上的接触键合标记剩余区域L中的合金形成区域的百分比(％)。
如图23中所示，当施加频率120kHz(曲线(b))或180kHz(曲线(c))的超声波时，合金形成区域的百分比比当施加频率60kHz(图(a))的超声波时大。在120kHz和180kHz之间，合金形成区域的百分比在后者超声波频率时大。当施加频率180kHz的超声波时，合金形成区域的百分比(％)达到至少70％，即使接触键合球的直径为大约65μm～50μm，而在120kHz的超声波频率，合金形成区域的百分比(％)达到大约70％，即使接触键合球的直径为大约65μm～55μm。
具有如图18中所示的结构的金球部分B或Al-Au合金层通过增加超声波频率来形成。考虑图25中所示的因素，使得能够调整金球部分B的形状或Al-Au合金层。
例如，与超声波有关的因素包括施加的超声波的频率(f)，振幅(a)和时间(s)。另外的例子包括由毛细管施加的负载(F)和键合焊盘部分BP的加热温度(℃)。
具体可能的方法包括增加超声波频率，在键合期间(T2～T3)通过毛细管逐渐或逐步地增加负载(F)，缩短或延长超声波的施加时间，在键合时间之前开始施加超声波，以及结合地使用这些方法(参考图26)。
图24说明键合焊盘部分的间距(键合焊盘间距)和Al-Au合金层形成区域的直径g与金球部分B的接触区直径d的百分比(g/d)之间的关系。曲线(a)的上区域表示区域Q，其中金球部分B的可靠性可以保证，而曲线(a)的下区域表示区域NQ，其中短路故障发生。Al膜的厚度设为700nm。
如图24中所示，当百分比(g/d)是80％或更大时，可靠性可以保证，即使是60μm或更小的键合焊盘间距。
图27是金丝WR粘附(第一键合)到键合焊盘部分BP上之后，衬底的不完整横断面视图。
如参考图14所描述的，金丝WR被超声波热压键合(第二键合)到布线衬底60例如玻璃环氧树脂上的印刷线路WR(没有说明)。图28说明第二键合之后IC芯片(1)和布线衬底60的状态(透视图)，而图29是图28中画有圆圈的部分的不完整放大图。
然后，如图30中所示，金丝WR和IC芯片在其外围用树脂密封剂64密封。树脂密封剂通过，例如，递压模具方法形成，其中熔化的树脂注入金属模具中，金属模具与布线衬底60的紧紧地固定树脂，然后硬化并密封。例如，包含二氧化硅作为填料的环氧树脂系列热固性树脂可以用作这种树脂。
一旦注入或硬化这一树脂，压力施加到金丝WR或它的球部分B。在本实施方案中，金球部分B的连接区的直径d和Al-Au合金层50形成区域的直径之间的关系设置为g≥0.8d，使得金球部分B和Al膜M3b(互连)之间由Al-Au合金层50产生的的粘接强度可以保证。
在形成树脂密封剂64之后，凸起电极52在布线衬底60的背面上形成。这一凸起电极没有示出，但是连接到形成于布线衬底60背面上的背面电极。
背面电极经由布线衬底60的内部布线与金丝WR电学连接。凸起电极62没有示出，但是出于与封装的衬底电学连接的目的使用该凸起电极，多个电子零件固定在封装衬底上供使用，例如用于方便电话。如图30中所示的封装形式称作“BGA”(球栅阵列)。
然后，为了保证产品寿命，使用没有发货的样品来进行质量试验例如温度循环试验。在这种温度循环试验中，在客户封装时的热过程(260℃×10s×三次)之后，半导体器件暴露于150℃的高温10分钟，然后-55℃的低温10分钟。这一循环重复1000次(1000个循环)。
在这一试验，热形变度在树脂64和IC芯片(1)之间是不同的，反映出树脂64，IC芯片(1)和布线衬底60之间热膨胀系数的不同。结果，压力在每个循环施加到金球部分B上。
但是在本实施方案中，金球部分B的连接区的直径d和Al-Au合金层50形成区域的直径g之间的关系设置为g≥0.8d，使得金球部分B和Al膜M3b(互连)之间由Al-Au合金层50产生的足够的粘接强度可以保证，使得避免因压力而导致的短路。
即使Al膜M3b(互连)形成得薄，并且由于AlAu4膜的形成出现不耐压力的部分，粘接强度仍然可以保证，从而短路可以避免。作为防止AlAu4膜形成的对策，可以考虑在金丝WR的第一键合之前，在键合焊盘部分BP上层积Al膜。但是，在这种情况下，Al膜的层积使得制造过程复杂。另一方面，根据本实施方案，由于层积另一Al膜而导致的步骤的复杂化可以避免。
一般惯例是同时形成键合焊盘和非键合焊盘的布线图。这一实施方案的应用使得获得足够的粘接强度成为可能，即使Al膜足够薄以便对IC芯片上布线宽度的变窄有利。
这使得形成更多的微细图案成为可能，从而提高芯片的集成度，增加每个晶片上可形成的芯片数，并减少生产成本。
即使键合焊盘部分BP随着因半导体器件的小型化或功能多样化而导致的引脚数的增加而变得更小，粘接强度仍然可以保证，并且短路可以避免。
另外，即使键合焊盘部分BP的间距随着因半导体器件的小型化或功能多样化而导致的引脚数的增加而变得更小，粘接强度仍然可以保证，并且短路可以避免。
当金球部分B的连接区的直径d和金球部分B的最大外径D之间的关系设置成满足下面的表达式：d≥0.8D时，金球部分的短路裕度可以保证，即使键合焊盘部分BP的间距随着因半导体器件的小型化或功能多样化而导致的引脚数的增加而变得更小。
由本发明者完成的本发明已基于实施方案具体地描述。本发明不局限于上述实施方案，并且无需说明，它可以在不背离本发明要点的范围内作修改。
特别地，在上述实施方案中，本发明应用于Al膜和金球部分B的键合。它也可以广泛地应用于半导体器件，其中金属互连和金属球部分(其可以是凸起电极)通过在它们的金属之间形成合金层来键合。
本实施方案不仅可以应用于BGA，也可以应用于使用引线框架的半导体器件例如QFP(四线扁平封装)。
下面将简要地描述由本申请所公开的发明的典型可获得的效果。
当形成于半导体芯片上的第一金属膜和由第二金属形成的球部分通过第一金属和第二金属的合金层来键合时，因为第一金属膜与球部分的接触区的直径d和合金层形成区域的直径g设置成满足下面的表达式：g≥08d；并且接触区的直径和球的最大外径D设置成满足下面的表达式：d≥0.8D，具有第一金属膜的互连与球部分之间的粘附可以保证。
另外，半导体器件的可靠性可以提高。
而且，半导体器件的成品率可以提高。
虽然一般惯例是同时形成键合焊盘和非键合焊盘的布线图，但是本实施方案的结构的使用使得能够获得足够的粘接强度，即使当Al膜足够薄以便对IC芯片上布线宽度的变窄有利时。
芯片的集成度可以通过形成更多的微细图案来提高，这可以增加每个晶片可获得的芯片数，并减少生产成本。

Claims (49)

1.一种半导体器件，包括：
(a)形成于半导体芯片上的第一金属膜；
(b)形成于所述第一金属膜上并由第二金属构成的球部分；
(c)所述第一金属和所述第二金属的合金层，该合金层在所述第一金属膜和所述球部分之间形成，
(d)其中所述合金层达到所述第一金属膜的底部，以及
(e)其中所述球部分用树脂覆盖。
2.一种半导体器件，包括：
(a)形成于半导体芯片上并且具有铝(Al)作为主要成分的Al膜；
(b)形成于所述Al膜上并且具有金(Au)作为主要成分的球部分；
(c)形成于所述第一Al膜和所述金球部分之间的铝-金合金层，
(d)其中所述合金层达到所述Al膜的底部，以及
(e)其中所述金球部分用树脂覆盖。
3.根据权利要求2的半导体器件，其中所述合金层包括AlAu4膜。
4.根据权利要求2的半导体器件，其中所述合金层由层叠薄膜组成，并且所述层叠薄膜金组成比相对于铝从低层向高层增加。
5.根据权利要求2的半导体器件，其中所述合金层以从底层开始的顺序，具有AlAu2膜，Al2Au5膜和AlAu4膜。
6.根据权利要求2的半导体器件，其中所述Al膜具有700nm或更小的厚度。
7.根据权利要求2的半导体器件，
其中所述半导体器件具有多个所述Al膜，
其中所述多个Al膜用在每个焊盘区域具有开口的绝缘膜覆盖，
其中任意相邻两个所述焊盘区域之间的最短距离是70μm或更小。
8.根据权利要求2的半导体器件，其中所述金部分具有65μm或更小的最大外径。
9.根据权利要求2的半导体器件，其中所述金球部分的高度h和所述金球部分的最大外径D之间的关系满足下面的表达式：9≥D/h≥2。
10.根据权利要求2的半导体器件，其中所述金球部分的高度是15μm或更小。
11.根据权利要求2的半导体器件，其中所述金球部分的高度是5μm或更大，但不大于15μm。
12.根据权利要求2的半导体器件，其中金丝从所述金球部分的上部延伸到外部接线端子。
13.一种半导体器件，包括：
(a)形成于半导体芯片上的第一金属膜；
(b)形成于所述第一金属膜上并由第二金属构成的球部分；
(c)所述第一金属和所述第二金属的合金层，该合金层在所述第一金属膜和所述球部分之间形成，
(d)其中所述合金层达到所述第一金属膜的底部，
(e)其中所述金球部分的高度h和所述金球部分的最大外径D之间的关系满足下面的表达式：9≥D/h≥2。
14.根据权利要求13的半导体器件，其中所述第一金属膜具有铝(Al)作为主要成分，而所述球部分具有金(Au)作为主要成分。
15.根据权利要求14的半导体器件，其中所述合金层包括AlAu4膜。
16.根据权利要求14的半导体器件，其中所述合金层由层叠薄膜组成，并且所述层叠薄膜中金组成比相对于铝从低层向高层增加。
17.根据权利要求14的半导体器件，其中所述合金层以从底层开始的顺序，具有AlAu2膜，Al2Au5膜和AlAu4膜。
18.根据权利要求14的半导体器件，其中所述Al膜具有700nm或更小的厚度。
19.根据权利要求14的半导体器件，
其中所述半导体器件具有多个所述Al膜，
其中所述多个Al膜用在每个焊盘区域具有开口的绝缘层覆盖，
其中任意相邻两个所述焊盘区域之间的最短距离是70μm或更小。
20.根据权利要求14的半导体器件，其中所述金球部分具有65μm或更小的最大外径。
21.根据权利要求14的半导体器件，其中所述金球部分具有15μm或更小的高度。
22.根据权利要求14的半导体器件，其中所述金球部分具有5μm或更大的高度，但不大于15μm或更小。
23.根据权利要求14的半导体器件，其中从所述金球部分的上部，金丝延伸到外部接线端子。
24.一种半导体器件，包括：
(a)形成于半导体芯片上的第一金属膜；
(b)形成于所述第一金属膜上并由第二金属构成的球部分；
(c)所述第一金属和所述第二金属的合金层，该合金层在所述第一金属膜和所述球部分之间形成，
(d)其中所述第一金属膜与所述球部分的接触区的直径d和所述合金层形成区域的直径g之间的关系满足下面的表达式：g≥0.8d。
25.根据权利要求24的半导体器件，其中所述第一金属膜具有铝(Al)作为主要成分，而所述球部分具有金(Au)作为主要成分。
26.根据权利要求24的半导体器件，其中所述合金层达到所述第一金属膜的底部。
27.根据权利要求24的半导体器件，其中所述接触区的直径d和所述球部分的最大外径D之间的关系满足下面的表达式：d≥0.8D。
28.根据权利要求24的半导体器件，其中所述接触区是由所述球部分的最大周边所定义的区域的至少70％。
29.根据权利要求25的半导体器件，其中所述合金层包括AlAu4膜。
30.根据权利要求25的半导体器件，其中所述合金层由层叠薄膜组成，并且所述层叠薄膜中金组成比相对于铝从低层向高层增加。
31.根据权利要求25的半导体器件，其中所述合金层以从底层开始的顺序，具有AlAu2膜，Al2Au5膜和AlAu4膜。
32.根据权利要求25的半导体器件，其中所述Al膜具有700nm或更小的厚度。
33.根据权利要求25的半导体器件，
其中所述半导体器件具有多个所述Al膜，
其中所述多个Al膜用在每个焊盘区域具有开口的绝缘层覆盖，
其中任意相邻两个所述焊盘区域之间的最短距离是70μm或更小。
34.根据权利要求25的半导体器件，其中具有金(Au)作为主要成分的所述球部分具有65μm或更小的最大外径。
35.根据权利要求25的半导体器件，其中具有金(Au)作为主要成分的所述球部分的高度h和所述金球部分的最大外径D之间的关系满足下面的表达式：9≥D/h≥2。
36.根据权利要求25的半导体器件，其中具有金(Au)作为主要成分的所述球部分具有15μm或更小的高度。
37.根据权利要求25的半导体器件，其中具有金(Au)作为主要成分的所述球部分具有5μm或更大，但不大于15μm的高度。
38.根据权利要求25的半导体器件，其中从具有金(Au)作为主要成分的所述球部分的上部，金丝延伸到外部接线端子。
39.一种半导体器件，包括：
(a)形成于半导体芯片上的第一金属膜；
(b)形成于所述第一金属膜上并由第二金属构成的球部分；
(c)所述第一金属和所述第二金属的合金层，该合金层在所述第一金属膜和所述球部分之间形成，
(d)其中合金层在所述第一金属膜与所述球部分的接触区的至少70％中形成。
40.根据权利要求39的半导体器件，其中所述接触区的直径d和所述球部分的最大外径D之间的关系满足下面的表达式：d≥0.8D。
41.一种半导体器件，包括：
(a)形成于半导体芯片上的第一金属膜；
(b)形成于所述第一金属膜上并由第二金属构成的球部分；
(c)所述第一金属和所述第二金属的合金层，该合金层在所述第一金属膜和所述球部分之间形成，
(d)其中所述第一金属膜与所述球部分的接触区的直径d和所述球部分的最大外径D之间的关系满足下面的表达式：d≥0.8D。
42.一种半导体器件，包括：
(a)形成于半导体芯片上的第一金属膜；
(b)形成于所述第一金属膜上并由第二金属构成的球部分；
(c)所述第一金属和所述第二金属的合金层，该合金层在所述第一金属膜和所述球部分之间形成，
(d)其中所述第一金属膜与所述球部分的接触区是所述球部分的最大周边所定义的区域的至少70％。
43.一种半导体器件制造方法，包括步骤：
(a)在半导体芯片区域上形成第一金属膜；
(b)在所述第一金属膜上形成绝缘膜，该绝缘膜在所述第一金属膜上的焊盘部分具有开口；
(c)通过110kHz或更大超声波频率的超声波热压键合方法将由第二金属形成的球部分粘附到所述焊盘部分上。
44.根据权利要求43的半导体器件制造方法，其中所述步骤(c)通过在施加超声波时增加施加到所述焊盘部分的压力来进行。
45.根据权利要求43的半导体器件制造方法，在所述步骤(c)之后，进一步包括步骤：
(d)用树脂覆盖并密封所述球部分。
46.一种半导体器件制造方法，包括步骤：
(a)在半导体芯片区域上形成第一金属膜；
(b)在所述第一金属膜上形成绝缘膜，该绝缘膜在所述第一金属膜上的焊盘部分具有开口；
(c)通过110kHz或更大超声波频率的超声波热压键合方法将由第二金属形成的球部分粘附到所述焊盘部分上；
(d)用树脂覆盖并密封所述球部分；
(e)在所述步骤(d)之后，制备类似于上面所获得的所述密封半导体芯片的多个密封半导体芯片，并且将所述多个密封半导体芯片中的一些暴露于高温条件，以测试它们的特性。
47.一种半导体器件制造方法，包括步骤：
(a)在半导体芯片区域上形成第一金属膜；
(b)在所述第一金属膜上形成绝缘膜，该绝缘膜在所述第一金属膜上的焊盘部分具有开口；
(c)当由第二金属形成的球部分在所述第一金属膜上形成时，在所述第一金属膜与所述球部分的接触区的至少70％中形成所述第一金属和所述第二金属的合金层，从而将所述球部分粘附到所述焊盘部分上；
(d)用树脂覆盖并密封所述球部分；
(e)在所述步骤(d)之后，制备类似于上面所获得的所述密封半导体芯片的多个密封半导体芯片，并且将所述多个密封半导体芯片中的一些暴露于高温条件，以测试所述半导体芯片的特性。
48.一种半导体器件制造方法，包括步骤：
(a)在半导体芯片区域上形成第一金属膜；
(b)在所述第一金属膜上形成绝缘膜，该绝缘膜在所述第一金属膜上的焊盘部分具有开口；
(c)当由第二金属形成的球部分在所述第一金属膜上形成时，在所述第一金属膜与所述球部分的接触区的至少70％中形成所述第一金属和所述第二金属的合金层，从而将所述球部分粘附到所述第一金属膜上，并且调节所述球部分的形状，使得所述接触区的直径d和所述球部分的最大外径D满足下面的表达式：d≥0.8D；
(d)用树脂覆盖并密封所述球部分。
49.一种半导体器件制造方法，包括步骤：
(a)在半导体芯片区域上形成第一金属膜；
(b)在所述第一金属膜上形成绝缘膜，该绝缘膜在所述第一金属膜上的焊盘部分具有开口；
(c)当由第二金属形成的球部分在所述第一金属膜上形成时，在所述第一金属膜与所述球部分的接触区的至少70％中形成所述第一金属和所述第二金属的合金层，从而将所述球部分粘附到所述第一金属膜上，并且调节所述球部分的形状，使得所述接触区的直径d和最大外径D满足下面的表达式：d≥0.8D；
(d)用树脂覆盖并密封所述球部分；
(e)在所述步骤(d)之后，制备类似于上面所获得的所述密封半导体芯片的多个密封半导体芯片，并且将所述多个密封半导体芯片中的一些暴露于高温条件，以测试它们的特性。
CNB03120225XA 2002-03-07 2003-03-07 一种半导体器件 Expired - Fee Related CN100339986C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002061765A JP3943416B2 (ja) 2002-03-07 2002-03-07 半導体装置の製造方法
JP061765/2002 2002-03-07

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CNB2007100081899A Division CN100508152C (zh) 2002-03-07 2003-03-07 半导体器件制造方法

Publications (2)

Publication Number Publication Date
CN1444272A true CN1444272A (zh) 2003-09-24
CN100339986C CN100339986C (zh) 2007-09-26

Family

ID=27784868

Family Applications (2)

Application Number Title Priority Date Filing Date
CNB03120225XA Expired - Fee Related CN100339986C (zh) 2002-03-07 2003-03-07 一种半导体器件
CNB2007100081899A Expired - Fee Related CN100508152C (zh) 2002-03-07 2003-03-07 半导体器件制造方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
CNB2007100081899A Expired - Fee Related CN100508152C (zh) 2002-03-07 2003-03-07 半导体器件制造方法

Country Status (5)

Country Link
US (2) US20030168740A1 (zh)
JP (1) JP3943416B2 (zh)
KR (1) KR100968008B1 (zh)
CN (2) CN100339986C (zh)
TW (1) TWI290761B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4556436B2 (ja) * 2004-01-23 2010-10-06 住友ベークライト株式会社 半導体装置
US8003515B2 (en) * 2009-09-18 2011-08-23 Infineon Technologies Ag Device and manufacturing method
JP6507374B2 (ja) * 2016-04-21 2019-05-08 パナソニックＩｐマネジメント株式会社 部品圧着装置及び部品圧着方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5469961A (en) * 1977-11-15 1979-06-05 Fujitsu Ltd Production of semiconductor device
JPS6189643A (ja) * 1984-10-09 1986-05-07 Toshiba Corp 半導体装置及びその製造方法
CN1004110B (zh) * 1987-07-30 1989-05-03 昭荣化学工业株式会社 焊线
US5014111A (en) * 1987-12-08 1991-05-07 Matsushita Electric Industrial Co., Ltd. Electrical contact bump and a package provided with the same
JPH02285638A (ja) * 1989-04-27 1990-11-22 Toshiba Corp 半導体装置
JP2593965B2 (ja) * 1991-01-29 1997-03-26 三菱電機株式会社 半導体装置
US5244140A (en) * 1991-09-30 1993-09-14 Texas Instruments Incorporated Ultrasonic bonding process beyond 125 khz
US5486282A (en) * 1994-11-30 1996-01-23 Ibm Corporation Electroetching process for seed layer removal in electrochemical fabrication of wafers
JPH08162507A (ja) * 1994-12-02 1996-06-21 Hitachi Ltd ワイヤボンディング装置
US5578888A (en) * 1994-12-05 1996-11-26 Kulicke And Soffa Investments, Inc. Multi resonance unibody ultrasonic transducer
JP3598564B2 (ja) * 1995-03-16 2004-12-08 富士通株式会社 バンプ形成方法
JP3345541B2 (ja) * 1996-01-16 2002-11-18 株式会社日立製作所 半導体装置及びその製造方法
JP3284055B2 (ja) 1996-06-26 2002-05-20 株式会社東芝 半導体素子、半導体装置、および半導体装置の検査方法
US6065667A (en) * 1997-01-15 2000-05-23 National Semiconductor Corporation Method and apparatus for fine pitch wire bonding
US5976964A (en) * 1997-04-22 1999-11-02 Micron Technology, Inc. Method of improving interconnect of semiconductor device by utilizing a flattened ball bond
JPH11145174A (ja) * 1997-11-10 1999-05-28 Sony Corp 半導体装置およびその製造方法
JPH11233542A (ja) * 1998-02-09 1999-08-27 Sony Corp 半導体装置及びその製造方法
JP2002076051A (ja) * 2000-09-01 2002-03-15 Nec Corp 半導体装置のボンディングパッド構造及びボンディング方法
JP2001308132A (ja) 2000-04-21 2001-11-02 Matsushita Electric Works Ltd 電極の接合方法

Also Published As

Publication number Publication date
JP3943416B2 (ja) 2007-07-11
CN101043012A (zh) 2007-09-26
US7015127B2 (en) 2006-03-21
TWI290761B (en) 2007-12-01
CN100508152C (zh) 2009-07-01
US20040142551A1 (en) 2004-07-22
KR20030074159A (ko) 2003-09-19
JP2003258022A (ja) 2003-09-12
CN100339986C (zh) 2007-09-26
TW200305266A (en) 2003-10-16
US20030168740A1 (en) 2003-09-11
KR100968008B1 (ko) 2010-07-07

Similar Documents

Publication Publication Date Title
US5937279A (en) Semiconductor device, and manufacturing method of the same
CN1177368C (zh) 半导体器件
CN1230882C (zh) 一种半导体器件的制造方法和一种半导体器件
US6291274B1 (en) Resin molded semiconductor device and method for manufacturing the same
CN1790651A (zh) 芯片集成基板的制造方法
CN101064294A (zh) 电路装置及电路装置的制造方法
CN1283002C (zh) 连接端子及其制造方法以及半导体装置及其制造方法
CN1723556A (zh) 可叠置的半导体器件及其制造方法
CN1264923A (zh) 半导体器件及其制造方法
CN1210622A (zh) 半导体装置及其制造方法、电路基板和电子设备
CN1826688A (zh) 半导体器件的制造方法
CN1210794C (zh) 载带自动键合式半导体装置
CN1440064A (zh) 半导体装置及其制造方法、电路板以及电子机器
CN1652314A (zh) 引线框架、半导体芯片封装、及该封装的制造方法
US9147665B2 (en) High bond line thickness for semiconductor devices
CN1536658A (zh) 半导体器件及其制造方法
US7825501B2 (en) High bond line thickness for semiconductor devices
CN1674219A (zh) 半导体器件和用于半导体器件的多层基板
US8471371B2 (en) Semiconductor wiring assembly, semiconductor composite wiring assembly, and resin-sealed semiconductor device
CN100339986C (zh) 一种半导体器件
JP2003068738A (ja) 半導体装置及びその製造方法及び半導体チップ及びその実装方法
TWI501371B (zh) A wiring member for a semiconductor device, a composite wiring member for a semiconductor device, and a resin-sealed type semiconductor device
US5930604A (en) Encapsulation method for fine-pitch chip-on-board
JP2020188083A (ja) 半導体装置、その製造方法、及びモジュール
JP2008283213A (ja) 半導体装置、及び半導体装置の製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20070926

Termination date: 20140307