CN1418372A - 利用高温去光阻以形成高品质的多重厚度氧化物层的方法 - Google Patents

利用高温去光阻以形成高品质的多重厚度氧化物层的方法 Download PDF

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CN1418372A
CN1418372A CN01806877A CN01806877A CN1418372A CN 1418372 A CN1418372 A CN 1418372A CN 01806877 A CN01806877 A CN 01806877A CN 01806877 A CN01806877 A CN 01806877A CN 1418372 A CN1418372 A CN 1418372A
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coating
oxide skin
photoresistance
wafer
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CN1198324C (zh
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A·T·会
小仓寿典
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Cypress Semiconductor Corp
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Advanced Micro Devices Inc
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Abstract

本发明揭示一种藉由消除去光阻所导致的缺陷，以形成高品质的具有不同厚度的氧化物层的方法。该方法包含形成一个氧化物层(2)，以一层光阻层(8)将该氧化物层遮蔽，并将该光阻层加以显影以使该氧化物层的至少一部分(10)外露。然后将基板加热并去光阻以移除导自光阻的显影的任何残渣。此外，亦可于将该基板加热并且去光阻之前先将该光阻层(8)熟化。然后将该氧化物层(2)加以蚀刻，并将残余的光阻(8)剥除，之后再于该基板上生长另一层的氧化物(14)。

Description

利用高温去光阻以形成高品质的多重厚度氧化物层的方法
技术领域
本发明涉及集成电路组件以及其制造过程的领域。本发明尤其涉及在硅晶圆基板上的高品质的多重厚度氧化物层的形成。
背景技术
非挥发性内存组件目前已广泛应用于当电力终止时必须保留信息的电子组件。非挥发性内存组件包含只读存储器(ROM)、可程序化只读存储器(PROM)、可抹除可程序化只读存储器(EPROM)、以及电子可抹除可程序化只读存储器(EEPROM)组件。EEPROM与其它非挥发性内存组件的不同是在于其可作电子程序化以及抹除。快闪EEPROM组件与EEPROM组件类似，其中的存储单元可以作电子程序化以及抹除。但是，快闪EEPROM组件容许使用单一电流脉冲将组件内所有存储单元加以抹除。
诸如程序化及抹除晶体管的高电压电路组件通常是以相对较高厚度的栅极氧化物层形成于硅晶圆基板上。如此的相对较厚的栅极氧化物层通常在如此的高电压环境下，为防止晶体管电路的崩溃，通常是有必要的。另一方面，硅晶圆基板上的低电压电路，是以利用相对较薄的栅极氧化物层加以实施为佳。通常，此种薄栅极氧化物层可以提升具有相对较短栅极长度以及薄氧化物层的此类电路组件的速率，因而通常可提供较高的作业速率。
此外，当制程技术朝向愈来愈短的栅极长度演进，是以更进一步削减栅极氧化物层的厚度为佳，俾以达到更快的作业速率。然而，如此的集成电路组件上所包含的部份电路组件未必可以缩放。
非挥发性内存组件，诸如快闪EEPROM，需要在硅晶圆基板上形成有包含隧道氧化物层的快闪存储单元。此类隧道氧化物层的厚度可以低于晶圆基板上的高电压氧化物层。但是，此类隧道氧化物层通常其厚度无法如低电压氧化物层般予以缩减。此类快闪存储单元，举例来说，如果隧道氧化物层太薄时，通常会有明显的耐久性以及资料保持的问题。
因此，非挥发性内存组件通常可以受惠于在同一晶圆基板上的不同氧化物厚度的形成。具有相对较厚选择栅极氧化物层的晶体管可以容许高电压程序化以及抹除作业，而具有相对较低的厚度的栅极氧化物层的逻辑晶体管则可以随制程技术的朝向较细电路组件大小的演进而产生速率优势。此外，快闪存储单元的隧道氧化层的厚度可予缩放以求可靠度，而无关于高电压以及低电压晶体管的栅极大小以及氧化物层的厚度。
形成高品质多重厚度氧化物层的方法之一包含多重掩模以及氧化物形成步骤。举例来说，是将第一氧化物层，通常其是最厚的氧化物层，首先生长于晶圆基板上。然后，于该第一氧化物层上形成一层光阻。透过光罩将该光阻曝光于该光阻层上形成图样。然后将该光阻显影并且移除，留下一部份外露的氧化物层。之后，将该第一氧化物层加以蚀刻，并且将余留的光阻予以剥除。然后于该硅晶圆基板上长成第二层的氧化物。该第二氧化物层在该硅晶圆基板上形成薄氧化物层，而藉由第一以及第二氧化物层的结合形成较厚的氧化物层。此一过程可予重复以于整个制造流程中形成各种厚度的其它氧化物层。
在光阻层的显影当中以及之后，未予掩模或外露的部份的氧化物层恐已遭污染。举例言之，目视检查无法发现的薄膜，可能会形成在外露的部份的氧化物层之上。此一薄膜可能含括光阻残渣，诸如干燥后的显影剂以及未溶解的光阻残片。因此，通常有必要对该未掩模部份的氧化物层施以清除或去光阻过程以移除该光阻残渣。该未掩模或外露部份的氧化物层通常是在筒状灰化器或下游单一晶圆灰化器中利用O2、O2/N2或O2/N2-H2化学系统作去光阻或清除。
虽然去光阻过程是相对短暂以防止外露的氧化物层的任何表面损伤，但是该去光阻过程本身会在氧化物层上留下污染物。如图1所示，在高分辨率扫描式电子显微镜(SEM)下，该污染物在氧化物层上呈显为黑点。该黑点的分析显示其含括硫化物以及低分子烃类，极可能是光活性化合物，是留存自该光阻的显影。这些外露的氧化物层的表面上的黑点或缺陷干扰后续的加工步骤，导致产生制程问题并且降低可靠度以及良率。
举例来说，当在去光阻之后施行湿式氧化物蚀刻以移除外露部份的氧化物层时，在黑点底下的该氧化物层无法完全去除。因此，该黑点即有如一种微掩模存在于该氧化物层的外露部份之上。由于这些黑点，结果后续生长的氧化物层可能会不均匀，因为其起始氧化物层并未完全去除。
因此，较佳者是应有一种在制程当中用以防止这些黑点或缺陷的形成于氧化物层的方法，以俾能达到一个较高的可接受晶圆的整体产率。
发明内容
本发明揭示一种藉由减少去光阻所导致的缺陷而于半导体基材上形成均匀氧化物层的方法。该半导体基板包含一片晶圆，在该晶圆上的氧化物层，以及在该氧化物层上的经显影的光阻掩模。在一个实施例中，该半导体基板是于去光阻之前进行加热。在另一个实施例中，该光阻掩模是在加热以及去光阻之前将之熟化(cured)。
本发明的其它特色以及优点当可显见于以下的本发明的详细说明。
附图说明
图1是灰化后晶圆基板上的多余黑点的照片；
图2是形成于晶圆基板上氧化物层的部份剖视图；
图3是于氧化物层上形成光阻层之后的基材的部份剖视图；
图4是在光阻经显影以后使氧化物层之一部份外露时的晶圆基板的部份剖视图；
图5是在将氧化物层加以蚀刻之后的晶圆基板的部份剖视图；
图6是在光阻层已予剥除后的晶圆基板的部份剖视图；
图7是在长成新的氧化物层之后的晶圆基板的部份剖视图；
图8是在形成浮置栅极于第一以及第二氧化物层上以后的晶圆基板的部份剖视图；
图9是在形成光阻层并予显影之后，并且该基板已予去光阻之后的晶圆基板的部份剖视图；
图10是在氧化物层经已蚀刻后的晶圆基板的部份剖视图；以及
图11是在第三氧化物层已予长成之后的晶圆基板的部份剖视图。
须知为说明的简明，图中所示各组件未必是依尺寸比例。举例言之，为清楚起见某些组件尺寸相对于其它各组件可能已予特意加大。
具体实施方式
参照图2，有第一氧化物层2，为选择栅极氧化物层，全面覆盖形成于半导体基板4的表面上。较佳者，半导体基板4为单晶硅基板。半导体基板4具有上表面6，事先经加工去除瑕疪以及原有氧化物，以及底表面7。较佳者，第一氧化物层2是在干燥分子氧的存在下于升温下藉由表面6的热氧化所形成。较佳者，该氧化过程是在大约700至大约1500℃的温度下施行。该氧化过程形成氧化硅层，其厚度以在大约50至大约150埃为佳，而以大约100埃为更佳。该氧化过程可以在批式热氧化炉中进行。
形成第一氧化物层之后，对基板作处理以去除任何杂质，并且如图3所示形成光阻层8以全面覆盖第一氧化物层。较佳者为光阻层8是对紫外线敏感并是正型光阻。然后透过光罩以使选定部份的光阻层8曝光。经曝光的光阻然后经显影并予去除，留下一部份10的该氧化物层曝露在外。该光阻层的显影可用一般已知方法，包含但不限于：浸泡、喷涂以及浸置技术。图4说明氧化物层的外露部份10。
在光阻显影之后，通常基板是利用O2化学系统进行去光阻，以移除任何未显影或残余的光阻。在一般的去光阻过程当中晶圆的温度通常是在80至100℃之间。但是，如上述，在去光阻过程之后，氧化物层2之上可能会有黑点或缺陷产生。一般相信，在去光阻过程当中，从光阻的显影残存有光活性化合物黏着在外露部份的氧化物层的「冷点」上，终于导致黑点的形成，如图1所示。
已发现，若在去光阻之前将基板加热，则晶圆上的「冷点」可予去除，因而得以避免黑点的形成于氧化物层的外露区域之上。基板的加热可以采用半导体制程相关技术中任何已为习知的方法。在本发明的较佳实施例中，基板由密闭处理室中的灯加热。在一较佳实施例中，是将晶圆置于功率120伏/1000W(瓦)于80％功率，或是800W(瓦)的卤素灯下24秒。在另一实施例中，是将基板置于密闭处理室内的水平配置的经加热的平台上。较佳者，该经加热的平台其温度是在从200至270℃的温度。基板的底表面7水平躺置于顶针上，这些顶针是穿过平台的开孔。因而，该半导体基板及平台是在平行的水平面内。为将基板加热，将顶针下降以使基板底部抵接于平台的顶部。在一较佳实施例中，该基板维持在平台上2至5秒并经加热到从100至140℃的温度。在另一较佳实施例中，该基板维持在平台上3秒钟而加热至大约130℃。一旦该基板经加热，将顶针升起以使基板底部表面不再与平台表面接触。
加热步骤之后，作基板的去光阻以移除从光阻层的显影所残留下来的任何残渣。能够使用习知的桶形批式灰化器或下流晶圆至晶圆灰化器而施行去光阻处理。在基板经去光阻以后，将外露的氧化物层10加以蚀刻或剥除，如图5所示。该氧化物层可以利用半导体制造相关技术中已为习知的一般湿式或干式法加以蚀刻。可以用来蚀刻该氧化物层的外露区域的干式蚀刻法包含电浆蚀刻、离子打磨、以及反应性离子蚀刻。湿式蚀刻法包含氢氟酸的使用。较佳者，是利用经缓冲的氢氟酸氧化物蚀刻剂、氟化铵以及水来蚀刻该氧化物层的外露部份。
在氧化物层的外露区域经已蚀刻以后，将残余的光阻8剥除，如图6所示。半导体制造相关技术中已为习知的湿式以及干式方法均可用于剥除残余的光阻层8。此类方法包含但不限于，硫酸以及氧化剂溶液的使用，以及一般的O2电浆剥除。然后，在第一氧化物层2及该晶圆基板4上长成另一氧化物层14，即隧道氧化物层，如图7所示，以产生多重厚度氧化物层。
当加热基板时，须注意不可将基板过度加热，因为过度加热会导致光阻层熔化，其进而在后续加工步骤中产生问题。为避免在某些过程中光阻流动，可于加热之前将基板施以紫外线(UV)熟化加工。该UV熟化加工使光阻在加热步骤之前硬化，以确保该光阻可以维持其外形。任何半导体制造相关技术中已为习知的UV熟化方法均可用以熟化该光阻。在一较佳UV熟化过程当中，该基板是置于密闭处理室的UV放射源底下并于40至50秒间加热。详言之，是将基板放置在UV灯底下，设定在「低功率」，1800至2200W(瓦)及100至110mW/cm2(毫瓦/平方厘米)，为时10秒钟，然后将该UV灯的功率升高至「高功率」，4400至4800W(瓦)及275110mW/cm2(毫瓦/平方厘米)，将该基板延长留置于UV灯下另35秒钟。当晶圆是在UV灯下时，该晶圆是在经加热的平台或平板上。在UV熟化过程之前20秒，该经加热的平台其温度是在110℃。然后，在UV熟化过程的最后25秒，该经加热平台的温度是以0.8℃/秒的速率从110℃升温至130℃。如果加热平台的温度升高太快，则光阻可能起皱，膨胀或起泡而破坏所欲的光阻外形。
如上所讨论的诸方法利用以下实施例作更详细说明。须知本发明并不限于这些特定实施例。实施例1
在密闭处理室中，将基板放置在顶针上，这些顶针是在温度200℃的经加热的平台上。降下顶针，使基板底表面与经加热的平台接触3秒钟。然后再将顶针升起，使该基板不再与该经加热的平台接触。最后，将该基板依下列条件作2秒钟的灰化处理进行去光阻：RF＝100W(瓦)；压力＝1200mT(毫托)；O2/N2比例＝2000/200sccm(标准立方厘米)。实施例2
在密闭处理室中，将基板置于顶针上，这些顶针是在温度250℃的经加热的平台上。使该基板经施以如上述的较佳过程作UV熟化。降下顶针，使基板低表面与经加热的平台接触3秒钟。然后再将顶针升起，使该基板不再与该经加热的平台接触。最后将该基板依下列条件作10秒钟的灰化处理进行去光阻：RF＝100W(瓦)；压力＝1200mT(毫托)；O2/N2比例＝2000/200sccm(标准立方厘米)。实施例3
在密闭处理室中，将基板放置于顶针上，这些顶针是在温度270℃的经加热的平台上。将该基板施以如上述的较佳过程以作UV熟化。降下顶针，使基板的底表面与经加热的平台接触3秒钟。然后再将顶针升起，使该基板不再与该经加热的平台接触。最后，将该基板依下列条件作10秒钟的灰化处理进行去光阻：RF＝1100W(瓦)；压力＝1400mT(毫托)；O2＝3550sccm(标准立方厘米)。实施例4
在密闭处理室中，将基板放置于顶针上，这些顶针是在温度270℃的经加热的平台上。将该基板以如上述的较佳过程作UV熟化处理，然后用卤素灯于800W(瓦)加热24秒钟。最后，将该基板依下列条件作10秒钟的灰化处理进行去光阻：RF＝1100W(瓦)；压力＝1400mT(毫托)；O2＝3550sccm(标准立方厘米)。
上述过程可予重复以产生其它各种厚度的氧化物层。举例来说，在长成隧道氧化物层14之后，可将浮置栅极16形成于氧化物层2以及14之上，如图8所示。然后形成光阻层18以覆盖氧化物层2以及14，与门极构造16。如图9所示，该光阻层18是透过光罩曝光，然后经曝光的光在施以显影之后残留有部份15的氧化物层2以及14外露。在该光阻经显影后，将该光阻UV熟化并且加热之后将该基板去光阻。然后，将氧化物层2以及14之外露部份15予以蚀刻去除，并将残余的光阻剥除，如图10所示。如图11所说明，有第三氧化物层20，是外围栅极氧化物层，厚度不同于氧化物层2以及14，长成于晶圆基板4的表面。
如此，已根据本发明揭示一种可以完整提供上述优点的用以于半导体组件中制造出多重均匀氧化物层的方法。虽然此止是利用特定说明例以述说本发明，但并非意味本发明是仅限于那些说明用的实施形态。熟习相关技术者应可认知可以无须背离本发明的精神而作种种变化与修饰。因此本发明理应包含所有诸如此类的变化与修饰，只要其是在所附权利要求范围以及相当部份的范围之内。

Claims (10)

1.一种制造半导体结构的方法，此方法的特征为：
将基板放置于温度在200℃至270℃的表面上2至5秒钟以将该基板加热，该基板的特征包括：
(a)一片晶圆(4)；
(b)在该晶圆上的第一氧化物层(2)；
(c)在该第一氧化物层上的经显影的光阻掩模(8)；以及
(d)在该第一氧化物层上的至少一个外露部份(10)；
并且将该第一氧化物层的该外露部份(10)去光阻。
2.如权利要求1所述的方法，其中该基板的加热进而具以下特征：
将该基板放置于穿过而在该表面的上方的顶针上；降下该基板于该表面上以加热该晶圆；并将该基板上提离开该表面。
3.如权利要求1所述的方法，其特征在于进一步将该第一氧化物层(2)加以蚀刻。
4.如权利要求3所述的方法，其特征在于进一步将该光阻掩模(8)加以移除。
5.如权利要求4所述的方法，其特征在于进一步于该基板上生长第二氧化物层(14)。
6.一种制造半导体结构的方法，此方法的特征为：
将基板放置于卤素灯下15至30秒钟以将该基板加热，该基板的特征包括：
(a)一片晶圆(4)；
(b)在该晶圆上的第一氧化物层(2)；
(c)在该第一氧化物层上的经显影的光阻掩模(8)；以及
(d)在该第一氧化物层上的至少一个外露部份(10)；
并且将该第一氧化物层的外露部份进行去光阻。
7.一种制造半导体基板的方法，此方法的特征为：
将基板放置于温度在200℃至270℃的表面上2至5秒钟以将该基板加热，该基板的特征包括：
(a)一片晶圆(4)；
(b)在该晶圆上的第一氧化物层(2)；
(c)在该第一氧化物层上的经显影并熟化的光阻掩模(8)；以及
(d)该氧化物层的至少一个外露部份(10)；
并且将该氧化物层的外露部份(10)予以去光阻。
8.如权利要求7所述的方法，其中该光阻掩模(8)是经将该基板放置于UV灯下的经加热的平台上40至50秒钟加以熟化。
9.如权利要求8所述的方法，其特征在于进一步将该第一氧化物层(2)加以蚀刻。
10.如权利要求9所述的方法，其特征在于进一步将该光阻掩模(8)剥除并生长第二氧化物层(14)。
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Correction item: Co-patentee

False: Fujitsu Ltd.

Number: 16

Page: 449

Volume: 21

CI03 Correction of invention patent

Correction item: Co-patentee

False: Fujitsu Ltd.

Number: 16

Page: The title page

Volume: 21

COR Change of bibliographic data

Free format text: CORRECT: PATENTEE; FROM: CO-PATENTEE: FUJITSU LIMITED TO: NONE

ERR Gazette correction

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C56 Change in the name or address of the patentee

Owner name: SPANSION CO., LTD.

Free format text: FORMER NAME OR ADDRESS: ADVANCED MICRO DEVICES INC.

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Address after: California, USA

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Effective date of registration: 20160317

Address after: California, USA

Patentee after: CYPRESS SEMICONDUCTOR Corp.

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Patentee before: SPANSION LLC

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Granted publication date: 20050420

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