CN1346516A - 用来降低全局图形密度效应的智能栅层填充方法 - Google Patents
用来降低全局图形密度效应的智能栅层填充方法 Download PDFInfo
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- CN1346516A CN1346516A CN00806056A CN00806056A CN1346516A CN 1346516 A CN1346516 A CN 1346516A CN 00806056 A CN00806056 A CN 00806056A CN 00806056 A CN00806056 A CN 00806056A CN 1346516 A CN1346516 A CN 1346516A
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- 238000000034 method Methods 0.000 title claims abstract description 61
- 230000000694 effects Effects 0.000 title claims description 8
- 238000009792 diffusion process Methods 0.000 claims abstract description 101
- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 103
- 229920005591 polysilicon Polymers 0.000 claims description 80
- 238000004088 simulation Methods 0.000 claims description 51
- 230000003139 buffering effect Effects 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- 229910021332 silicide Inorganic materials 0.000 claims description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 5
- 235000012431 wafers Nutrition 0.000 description 19
- 238000005260 corrosion Methods 0.000 description 10
- 230000007797 corrosion Effects 0.000 description 10
- 230000005611 electricity Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000004308 accommodation Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 102220003641 c.2114-?_5219+?del Human genes 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 201000006549 dyspepsia Diseases 0.000 description 1
- 238000005469 granulation Methods 0.000 description 1
- 230000003179 granulation Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- General Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
Fi | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 | F10 |
图形密度 | 5% | 10% | 15% | 20% | 25% | 30% | 35% | 40% | 45% | 50% |
Claims (31)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/466,988 US6323113B1 (en) | 1999-12-10 | 1999-12-10 | Intelligent gate-level fill methods for reducing global pattern density effects |
US09/466988 | 1999-12-10 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1346516A true CN1346516A (zh) | 2002-04-24 |
CN1187827C CN1187827C (zh) | 2005-02-02 |
Family
ID=23853876
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB008060568A Expired - Fee Related CN1187827C (zh) | 1999-12-10 | 2000-12-07 | 用来降低全局图形密度效应的栅层填充方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US6323113B1 (zh) |
EP (1) | EP1157422A1 (zh) |
JP (1) | JP2003516638A (zh) |
KR (1) | KR100750409B1 (zh) |
CN (1) | CN1187827C (zh) |
WO (1) | WO2001043194A1 (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100539140C (zh) * | 2005-05-16 | 2009-09-09 | 台湾积体电路制造股份有限公司 | 半导体装置及其制造方法、半导体装置结构 |
CN102263018A (zh) * | 2010-05-27 | 2011-11-30 | 上海华虹Nec电子有限公司 | 改善芯片栅极侧墙生长的负载效应的方法 |
CN102412116A (zh) * | 2010-09-19 | 2012-04-11 | 中芯国际集成电路制造(上海)有限公司 | 形成电阻布局图形的方法 |
CN104239612A (zh) * | 2014-08-27 | 2014-12-24 | 上海华力微电子有限公司 | 改善激光退火热分布的方法 |
Families Citing this family (44)
Publication number | Priority date | Publication date | Assignee | Title |
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US6436807B1 (en) | 2000-01-18 | 2002-08-20 | Agere Systems Guardian Corp. | Method for making an interconnect layer and a semiconductor device including the same |
KR100530296B1 (ko) * | 2000-03-07 | 2005-11-22 | 마이크론 테크놀로지, 인크. | 집적 회로 내에 거의 평탄한 유전체막을 제조하는 방법 |
US6528883B1 (en) * | 2000-09-26 | 2003-03-04 | International Business Machines Corporation | Shapes-based migration of aluminum designs to copper damascene |
US6751785B1 (en) * | 2002-03-12 | 2004-06-15 | Ubitech, Inc. | System and method for limiting increase in capacitance due to dummy metal fills utilized for improving planar profile uniformity |
JP2005520336A (ja) * | 2002-03-12 | 2005-07-07 | ユビテック, インコーポレイテッド | 素子整合及び選択的な容量制限の妨害を防ぎながらダミーメタル充填物を位置付けるシステム及び方法 |
US7152215B2 (en) * | 2002-06-07 | 2006-12-19 | Praesagus, Inc. | Dummy fill for integrated circuits |
US7712056B2 (en) * | 2002-06-07 | 2010-05-04 | Cadence Design Systems, Inc. | Characterization and verification for integrated circuit designs |
US7124386B2 (en) * | 2002-06-07 | 2006-10-17 | Praesagus, Inc. | Dummy fill for integrated circuits |
US7774726B2 (en) * | 2002-06-07 | 2010-08-10 | Cadence Design Systems, Inc. | Dummy fill for integrated circuits |
WO2003104921A2 (en) * | 2002-06-07 | 2003-12-18 | Praesagus, Inc. | Characterization adn reduction of variation for integrated circuits |
US7853904B2 (en) * | 2002-06-07 | 2010-12-14 | Cadence Design Systems, Inc. | Method and system for handling process related variations for integrated circuits based upon reflections |
US7363099B2 (en) * | 2002-06-07 | 2008-04-22 | Cadence Design Systems, Inc. | Integrated circuit metrology |
US7393755B2 (en) * | 2002-06-07 | 2008-07-01 | Cadence Design Systems, Inc. | Dummy fill for integrated circuits |
US20030229875A1 (en) * | 2002-06-07 | 2003-12-11 | Smith Taber H. | Use of models in integrated circuit fabrication |
US7328419B2 (en) * | 2002-11-19 | 2008-02-05 | Cadence Design Systems, Inc. | Place and route tool that incorporates a metal-fill mechanism |
US20040098688A1 (en) * | 2002-11-19 | 2004-05-20 | Cadence Design Systems, Inc. | Method, system, and article of manufacture for implementing long wire metal-fill |
US7231624B2 (en) * | 2002-11-19 | 2007-06-12 | Cadence Design Systems, Inc. | Method, system, and article of manufacture for implementing metal-fill with power or ground connection |
US7287324B2 (en) * | 2002-11-19 | 2007-10-30 | Cadence Design Systems, Inc. | Method, system, and article of manufacture for implementing metal-fill on an integrated circuit |
US6693357B1 (en) | 2003-03-13 | 2004-02-17 | Texas Instruments Incorporated | Methods and semiconductor devices with wiring layer fill structures to improve planarization uniformity |
US6905967B1 (en) * | 2003-03-31 | 2005-06-14 | Amd, Inc. | Method for improving planarity of shallow trench isolation using multiple simultaneous tiling systems |
JP4533698B2 (ja) * | 2004-08-12 | 2010-09-01 | 株式会社東芝 | 自動設計システム、自動設計方法及び半導体装置の製造方法 |
US7305643B2 (en) * | 2005-05-12 | 2007-12-04 | Freescale Semiconductor, Inc. | Method of tiling analog circuits that include resistors and capacitors |
US7315054B1 (en) | 2005-07-05 | 2008-01-01 | Advanced Micro Devices, Inc. | Decoupling capacitor density while maintaining control over ACLV regions on a semiconductor integrated circuit |
US7694258B1 (en) * | 2005-08-01 | 2010-04-06 | Cadence Design Systems, Inc. | Method and apparatus for inserting metal fill in an integrated circuit (“IC”) layout |
US8035168B2 (en) * | 2006-02-27 | 2011-10-11 | Synopsys, Inc. | Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance |
US7484198B2 (en) * | 2006-02-27 | 2009-01-27 | Synopsys, Inc. | Managing integrated circuit stress using dummy diffusion regions |
US7600207B2 (en) * | 2006-02-27 | 2009-10-06 | Synopsys, Inc. | Stress-managed revision of integrated circuit layouts |
US7767515B2 (en) * | 2006-02-27 | 2010-08-03 | Synopsys, Inc. | Managing integrated circuit stress using stress adjustment trenches |
KR100780775B1 (ko) * | 2006-11-24 | 2007-11-30 | 주식회사 하이닉스반도체 | 자기 조립 더미 패턴이 삽입된 회로 레이아웃을 이용한반도체 소자 제조 방법 |
US8003539B2 (en) * | 2007-01-04 | 2011-08-23 | Freescale Semiconductor, Inc. | Integrated assist features for epitaxial growth |
US7565639B2 (en) * | 2007-01-04 | 2009-07-21 | Freescale Semiconductor, Inc. | Integrated assist features for epitaxial growth bulk tiles with compensation |
US8741743B2 (en) * | 2007-01-05 | 2014-06-03 | Freescale Semiconductor, Inc. | Integrated assist features for epitaxial growth |
US7470624B2 (en) * | 2007-01-08 | 2008-12-30 | Freescale Semiconductor, Inc. | Integrated assist features for epitaxial growth bulk/SOI hybrid tiles with compensation |
JP2009053763A (ja) * | 2007-08-23 | 2009-03-12 | Nec Electronics Corp | ダミーパターン配置装置、ダミーパターン配置方法 |
US7681166B2 (en) * | 2007-09-28 | 2010-03-16 | Synopsys, Inc. | Method and apparatus for performing dummy-fill by using a set of dummy-fill cells |
US7890906B2 (en) * | 2008-05-09 | 2011-02-15 | International Business Machines Corporation | Method of laying out integrated circuit design based on known polysilicon perimeter densities of individual cells |
US20120256273A1 (en) * | 2011-04-08 | 2012-10-11 | Yu-Ho Chiang | Method of unifying device performance within die |
US8928110B2 (en) | 2011-09-09 | 2015-01-06 | United Microelectronics Corp. | Dummy cell pattern for improving device thermal uniformity |
US9209182B2 (en) * | 2012-12-28 | 2015-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy metal gate structures to reduce dishing during chemical-mechanical polishing |
US20140201694A1 (en) * | 2013-01-15 | 2014-07-17 | Mentor Graphics Corporation | Wrap Based Fill In Layout Designs |
US9092589B2 (en) * | 2013-11-29 | 2015-07-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit design flow with device array layout generation |
US9740092B2 (en) * | 2014-08-25 | 2017-08-22 | Globalfoundries Inc. | Model-based generation of dummy features |
US9640438B2 (en) * | 2014-12-30 | 2017-05-02 | Globalfoundries Singapore Pte. Ltd. | Integrated circuits with inactive gates and methods of manufacturing the same |
KR102458359B1 (ko) * | 2018-01-31 | 2022-10-25 | 삼성전자주식회사 | 적응적 메탈 필을 이용한 레이아웃 설계 방법 및 이에 기반하여 제조되는 반도체 장치 |
Family Cites Families (15)
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JP2507618B2 (ja) * | 1989-07-21 | 1996-06-12 | 株式会社東芝 | 半導体集積回路装置の製造方法 |
JP2803772B2 (ja) * | 1992-04-03 | 1998-09-24 | 東レ株式会社 | 二軸配向積層フイルム |
US5278105A (en) | 1992-08-19 | 1994-01-11 | Intel Corporation | Semiconductor device with dummy features in active layers |
US5636133A (en) | 1995-05-19 | 1997-06-03 | International Business Machines Corporation | Efficient generation of fill shapes for chips and packages |
US5861342A (en) | 1995-12-26 | 1999-01-19 | Vlsi Technology, Inc. | Optimized structures for dummy fill mask design |
US5658833A (en) * | 1996-01-30 | 1997-08-19 | United Microelectronics Corporation | Method and dummy disc for uniformly depositing silicon nitride |
US5639697A (en) | 1996-01-30 | 1997-06-17 | Vlsi Technology, Inc. | Dummy underlayers for improvement in removal rate consistency during chemical mechanical polishing |
US5902752A (en) | 1996-05-16 | 1999-05-11 | United Microelectronics Corporation | Active layer mask with dummy pattern |
JP3311244B2 (ja) | 1996-07-15 | 2002-08-05 | 株式会社東芝 | 基本セルライブラリ及びその形成方法 |
US5790417A (en) * | 1996-09-25 | 1998-08-04 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of automatic dummy layout generation |
JP3495869B2 (ja) * | 1997-01-07 | 2004-02-09 | 株式会社東芝 | 半導体装置の製造方法 |
US5854125A (en) | 1997-02-24 | 1998-12-29 | Vlsi Technology, Inc. | Dummy fill patterns to improve interconnect planarity |
US5923947A (en) | 1997-05-06 | 1999-07-13 | Vlsi Technology, Inc. | Method for achieving low capacitance diffusion pattern filling |
JP3159127B2 (ja) | 1997-06-09 | 2001-04-23 | 日本電気株式会社 | 半導体装置の設計方法 |
TW449900B (en) * | 1998-05-26 | 2001-08-11 | United Microelectronics Corp | Method to define dummy patterns |
-
1999
- 1999-12-10 US US09/466,988 patent/US6323113B1/en not_active Expired - Lifetime
-
2000
- 2000-12-07 KR KR1020017010079A patent/KR100750409B1/ko not_active IP Right Cessation
- 2000-12-07 WO PCT/US2000/033449 patent/WO2001043194A1/en active Application Filing
- 2000-12-07 CN CNB008060568A patent/CN1187827C/zh not_active Expired - Fee Related
- 2000-12-07 JP JP2001543782A patent/JP2003516638A/ja not_active Withdrawn
- 2000-12-07 EP EP00984132A patent/EP1157422A1/en not_active Withdrawn
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100539140C (zh) * | 2005-05-16 | 2009-09-09 | 台湾积体电路制造股份有限公司 | 半导体装置及其制造方法、半导体装置结构 |
CN102263018A (zh) * | 2010-05-27 | 2011-11-30 | 上海华虹Nec电子有限公司 | 改善芯片栅极侧墙生长的负载效应的方法 |
CN102263018B (zh) * | 2010-05-27 | 2013-07-24 | 上海华虹Nec电子有限公司 | 改善芯片栅极侧墙生长的负载效应的方法 |
CN102412116A (zh) * | 2010-09-19 | 2012-04-11 | 中芯国际集成电路制造(上海)有限公司 | 形成电阻布局图形的方法 |
CN102412116B (zh) * | 2010-09-19 | 2013-10-09 | 中芯国际集成电路制造(上海)有限公司 | 形成电阻布局图形的方法 |
CN104239612A (zh) * | 2014-08-27 | 2014-12-24 | 上海华力微电子有限公司 | 改善激光退火热分布的方法 |
CN104239612B (zh) * | 2014-08-27 | 2020-06-09 | 上海华力微电子有限公司 | 改善激光退火热分布的方法 |
Also Published As
Publication number | Publication date |
---|---|
KR100750409B1 (ko) | 2007-08-21 |
EP1157422A1 (en) | 2001-11-28 |
US6323113B1 (en) | 2001-11-27 |
KR20020002388A (ko) | 2002-01-09 |
CN1187827C (zh) | 2005-02-02 |
JP2003516638A (ja) | 2003-05-13 |
WO2001043194A1 (en) | 2001-06-14 |
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