CN113990753A - 一种改善FinFET器件性能的源漏外延形工艺方法 - Google Patents

一种改善FinFET器件性能的源漏外延形工艺方法 Download PDF

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CN113990753A
CN113990753A CN202010729638.4A CN202010729638A CN113990753A CN 113990753 A CN113990753 A CN 113990753A CN 202010729638 A CN202010729638 A CN 202010729638A CN 113990753 A CN113990753 A CN 113990753A
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李勇
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Abstract

本发明提供一种改善FinFET器件性能的源漏外延形工艺方法，提供Fin器件结构，包括：纵向间隔排列且覆盖有薄型氧化层的多个Fin结构；填充于相邻的Fin结构之间的STI区；位于Fin结构上横向间隔排列的多个栅结构；沉积覆盖栅结构和Fin结构的薄型氧化层的侧墙；刻蚀去除栅结构顶部的侧墙及部分Fin结构的侧墙；刻蚀去除被去除侧墙的Fin结构中露出的部分，形成凹槽；刻蚀去除凹槽侧壁的薄型氧化层，以扩大凹槽体积；在凹槽位置形成外延层结构。本发明形成外延层沟槽后，增加刻蚀去除沟槽侧壁氧化物的工艺，使后续生长外延层的体积增大，从而有利于增加应力，同时降低源漏电阻，因而有利于提高器件的性能。

Description

一种改善FinFET器件性能的源漏外延形工艺方法
技术领域
本发明涉及半导体技术领域，特别是涉及一种改善FinFET器件性能的源漏外延形工艺方法。
背景技术
从90nm开始，SiGe源漏外延是提高PMOS器件性能的关键因素，从14nm开始，采用SiP源漏外延技术来提高NMOS的性能，不同的外延轮廓具有不同的应力，进而影响器件性能。传统工艺中，用于外延的沟槽刻蚀使得较厚的氧化层仍留在沟槽中，因此后续生长的外延层的体积会受到很大限制。
然而体积较大的外延层有利于增强应力并且降低电阻，因此如何提高外延层的体积值得探讨。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种改善FinFET器件性能的源漏外延形工艺方法，用于解决现有技术中FinFET器件的外延层沟槽形成后，沟槽侧壁仍然留有较厚氧化层，从而使得生长外延层受限，导致影响器件性能问题。
为实现上述目的及其他相关目的，本发明提供一种改善FinFET器件性能的源漏外延形工艺方法，至少包括：
步骤一、提供Fin器件结构，所述Fin器件结构至少包括：位于基底上纵向间隔排列的多个Fin结构，所述Fin结构外表面以及所述基底上覆盖有薄型氧化层；位于所述薄型氧化层之外并填充于相邻的所述Fin结构之间的STI区；所述STI区的上表面高度低于所述Fin结构顶部的高度，并且高于所述STI区上表面高度的每个所述Fin结构的部分为第一Fin结构；形成于所述基底上、所述纵向间隔排列的多个Fin结构外表面的所述薄型氧化层上横向间隔排列的多个栅结构；
步骤二、沉积覆盖所述多个栅结构外表面和所述多个Fin结构外表面的所述薄型氧化层的侧墙；
步骤三、刻蚀去除所述栅结构顶部的所述侧墙以及多个所述Fin结构中的数个Fin结构上的所述侧墙；
步骤四、刻蚀去除步骤三中被去除侧墙的所述数个Fin结构中每个Fin结构中的所述第一Fin结构，在去除了所述第一Fin结构的位置形成凹槽；
步骤五、刻蚀去除所述凹槽侧壁的所述薄型氧化层，以扩大所述凹槽的体积；
步骤六、在所述数个凹槽的位置形成外延层结构。
优选地，步骤一中的所述栅结构包括：多晶硅层、位于所述多晶硅层上的硬掩膜层、位于所述硬掩膜层上的氧化层。
优选地，步骤一中的所述第一Fin结构的高度为30-90nm。
优选地，步骤三中刻蚀去除所述栅结构顶部的所述侧墙包括：刻蚀去除所述氧化层顶部和所述氧化层顶部以下的一部分侧壁上的所述侧墙。
优选地，步骤五中刻蚀去除所述凹槽侧壁的所述薄型氧化层的同时，与被刻蚀的所述薄型氧化层对应的第一Fin结构两侧的所述STI区也刻蚀形成STI凹槽。
优选地，步骤五中刻蚀所述薄型氧化层的方法为各向异性刻蚀。
优选地，步骤五中刻蚀去除所述凹槽侧壁的所述薄型氧化层的纵向厚度为3-10nm。
优选地，步骤五中刻蚀去除所述凹槽侧壁的所述薄型氧化层的横向深度为2nm。
优选地，步骤六中在所述数个凹槽的位置形成的外延层结构为SiGe或SiP。
如上所述，本发明的改善FinFET器件性能的源漏外延形工艺方法，具有以下有益效果：本发明在FinFET器件的制造过程中，在形成外延层沟槽之后，增加一步刻蚀去除沟槽侧壁氧化物的工艺，使得后续生长外延层的体积增大，外延层体积的增大有利于增加应力，同时降低源漏电阻，因而有利于提高器件的性能，本发明采用的增加刻蚀氧化物的工艺，工艺方法简单有效，并且不损伤其他部位，能够有效提高FinFET器件的性能，节约生产成本。
附图说明
图1显示为本发明的Fin器件结构的三维截面示意图；
图2显示为本发明中刻蚀去除栅结构顶部的侧墙后的三维截面示意图；
图3显示为本发明中刻蚀去除第一Fin结构后的三维结构示意图；
图4显示为去除凹槽侧壁的薄型氧化层后的三维截面示意图；
图5显示为本发明中形成外延层后的三维截面示意图；
图6显示为本发明的改善FinFET器件性能的源漏外延形工艺方法流程图。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1至图6。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
实施例一
本发明提供一种改善FinFET器件性能的源漏外延形工艺方法，如图6所示，图6显示为本发明的改善FinFET器件性能的源漏外延形工艺方法流程图，至少包括以下步骤：
步骤一、提供Fin器件结构，所述Fin器件结构至少包括：位于基底上纵向间隔排列的多个Fin结构，所述Fin结构外表面以及所述基底上覆盖有薄型氧化层；位于所述薄型氧化层之外并填充于相邻的所述Fin结构之间的STI区；所述STI区的上表面高度低于所述Fin结构顶部的高度，并且高于所述STI区上表面高度的每个所述Fin结构的部分为第一Fin结构；形成于所述基底上、所述纵向间隔排列的多个Fin结构外表面的所述薄型氧化层上横向间隔排列的多个栅结构；本发明进一步地，步骤一中的所述栅结构包括：多晶硅层、位于所述多晶硅层上的硬掩膜层、位于所述硬掩膜层上的氧化层。本发明再进一步地，步骤一中的所述第一Fin结构的高度为30-90nm。
如图1所示，图1显示为本发明的Fin器件结构的三维截面示意图，所述Fin器件结构在本实施例中至少包括：位于所述基底01上纵向间隔排列的多个Fin结构02，其中基底为硅材料，所述Fin结构02为刻蚀所述基底得到的多个凸起，本发明中所述多个Fin结构在纵向呈间隔排布，所述纵向规定为图1中三维结构的参考坐标系(X-Y)中的Y方向，亦即所述多个Fin结构的间隔排布方向，而其中每个所述Fin结构在横向(图1中的X方向呈条形的完整结构)；所述Fin结构外表面以及所述基底上覆盖有薄型氧化层03，亦即在所述基底上沉积一层所述薄型氧化层03，该薄型氧化层03将在横向(X方向)呈条形、纵向(Y方向)间隔排布的Fin结构的外表面覆盖，同时覆盖了所述Fin结构之间的基底的上表面。
所述Fin器件结构还包括位于所述薄型氧化层03之外并填充于相邻的所述Fin结构之间的STI区04，如图1所示，所述STI区为浅沟道隔离区，所述STI区将所述Fin结构之间、在所述薄型氧化层外表面的空间进行填充；所述STI区04的上表面高度低于所述Fin结构02顶部的高度，并且高于所述STI区04上表面高度的每个所述Fin结构的部分为第一Fin结构021。如图1所示，填充在所述Fin结构之间的所述STI区的上表面将所述Fin结构的高度分为两部分，其中一部分高出所述STI区的高度，为所述第一Fin结构021。本发明再进一步地，步骤一中的所述第一Fin结构021的高度为30-90nm。
所述Fin器件结构还包括形成于所述基底01上、所述纵向间隔排列的多个Fin结构02外表面的所述薄型氧化层03上横向间隔排列的多个栅结构，如图1所示，所述栅结构的排布方向为X方向；本发明进一步地，步骤一中的所述栅结构包括：多晶硅层051、位于所述多晶硅层051上的硬掩膜层(HM)052、位于所述硬掩膜层052上的氧化层053。
步骤二、沉积覆盖所述多个栅结构外表面和所述多个Fin结构外表面的所述薄型氧化层的侧墙；如图1所示，所述侧墙06不光覆盖了所述栅结构的外表面，同时覆盖了所述Fin结构上的所述薄型氧化层03。
步骤三、刻蚀去除所述栅结构顶部的所述侧墙以及多个所述Fin结构中的数个Fin结构上的所述侧墙；本发明进一步地，步骤三中刻蚀去除所述栅结构顶部的所述侧墙包括：刻蚀去除所述氧化层顶部和所述氧化层顶部以下的一部分侧壁上的所述侧墙。如图2所示，图2显示为本发明中刻蚀去除栅结构顶部的侧墙后的三维截面示意图；在所述栅结构顶部的所述侧墙06被刻蚀，使得所述栅结构顶部的所述氧化层053露出，所述栅结构侧壁的侧墙刻蚀后的高度停留在所述氧化层053侧壁上，亦即刻蚀所述栅结构上的侧墙06将所述氧化层053的顶部和其一部分侧壁露出。该步骤三中刻蚀所述侧墙的同时，所述多个Fin结构中的一部分Fin结构侧壁的所述侧墙也被刻蚀，也就是说，所述多个Fin结构中的一部分(所述数个Fin结构)被刻蚀去除侧墙，而另一部分不需要被刻蚀去除侧墙的所述Fin结构利用光刻胶07将其覆盖。
步骤四、刻蚀去除步骤三中被去除侧墙的所述数个Fin结构中每个Fin结构中的所述第一Fin结构，在去除了所述第一Fin结构的位置形成凹槽；如图3所示，图3显示为本发明中刻蚀去除第一Fin结构后的三维结构示意图。由于所述Fin结构在本实施例中为硅材料，因此当所述第一Fin结构上的所述侧墙被去除后，所述硅材料的第一Fin结构暴露出，因此，该步骤四将暴露出的硅进行刻蚀，因此，被刻蚀去除的位置成为如图3所示的凹槽A。
步骤五、刻蚀去除所述凹槽侧壁的所述薄型氧化层，以扩大所述凹槽的体积；如图4所示，图4显示为去除凹槽侧壁的薄型氧化层后的三维截面示意图。本发明进一步地，步骤五中刻蚀去除所述凹槽侧壁的所述薄型氧化层的同时，与被刻蚀的所述薄型氧化层对应的第一Fin结构两侧的所述STI区也刻蚀形成STI凹槽。由于所述多个Fin结构中数个Fin结构的第一Fin结构被刻蚀去除留下凹槽，而在所述第一Fin结构的侧壁有所述薄型氧化层03，因此在形成的所述凹槽的侧壁亦还有所述薄型氧化层03，该步骤五利用刻蚀的方法将形成所述凹槽A侧壁的所述薄型氧化层03去除，去除后所述凹槽的体积被扩大，以利于后续外延层的生长。
步骤五中刻蚀所述薄型氧化层的方法为各向异性刻蚀。本发明进一步地，步骤五中刻蚀去除所述凹槽A侧壁的所述薄型氧化层的纵向厚度为3-10nm，亦即所述薄型氧化层在如图4中的Y方向上的被刻蚀厚度为3-10nm。由于刻蚀方法为各向异性刻蚀，步骤五中同时刻蚀去除所述凹槽侧壁的所述薄型氧化层的横向(X方向)深度为2nm，以防氧化层损失过大，从而导致外延桥向栅极方向发展。
步骤六、在所述数个凹槽的位置形成外延层结构。如图5所示，图5显示为本发明中形成外延层后的三维截面示意图。本发明进一步地，步骤六中在所述数个凹槽A的位置形成的外延层结构08为SiGe或SiP。
实施例二
本发明的该实施例二中包括：重复实施例一的步骤一和步骤二，不同的是步骤三：将实施例一中已经进行了外延生长的Fin结构用光刻胶覆盖，将实施例一中步骤三中不需要刻蚀去除侧墙的Fin结构不用光刻胶覆盖，将其暴露出来，之后接着刻蚀去除被暴露出来的Fin结构的侧墙，之后重复实施例一的步骤四至步骤六，而步骤六中生长的外延层与实施例一中的外延层不相同，为SiGe或SiP的一种。因此得到同一个FinFET器件结构中既包含有SiGe又包含有SiP的外延层。
综上所述，本发明在FinFET器件的制造过程中，在形成外延层沟槽之后，增加一步刻蚀去除沟槽侧壁氧化物的工艺，使得后续生长外延层的体积增大，外延层体积的增大有利于增加应力，同时降低源漏电阻，因而有利于提高器件的性能，本发明采用的增加刻蚀氧化物的工艺，工艺方法简单有效，并且不损伤其他部位，能够有效提高FinFET器件的性能，节约生产成本。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (9)

1.一种改善FinFET器件性能的源漏外延形工艺方法，其特征在于，至少包括：
步骤一、提供Fin器件结构，所述Fin器件结构至少包括：位于基底上纵向间隔排列的多个Fin结构，所述Fin结构外表面以及所述基底上覆盖有薄型氧化层；位于所述薄型氧化层之外并填充于相邻的所述Fin结构之间的STI区；所述STI区的上表面高度低于所述Fin结构顶部的高度，并且高于所述STI区上表面高度的每个所述Fin结构的部分为第一Fin结构；形成于所述基底上、所述纵向间隔排列的多个Fin结构外表面的所述薄型氧化层上横向间隔排列的多个栅结构；
步骤二、沉积覆盖所述多个栅结构外表面和所述多个Fin结构外表面的所述薄型氧化层的侧墙；
步骤三、刻蚀去除所述栅结构顶部的所述侧墙以及多个所述Fin结构中的数个Fin结构上的所述侧墙；
步骤四、刻蚀去除步骤三中被去除侧墙的所述数个Fin结构中每个Fin结构中的所述第一Fin结构，在去除了所述第一Fin结构的位置形成凹槽；
步骤五、刻蚀去除所述凹槽侧壁的所述薄型氧化层，以扩大所述凹槽的体积；
步骤六、在所述数个凹槽的位置形成外延层结构。
2.根据权利要求1所述的改善FinFET器件性能的源漏外延形工艺方法，其特征在于：步骤一中的所述栅结构包括：多晶硅层、位于所述多晶硅层上的硬掩膜层、位于所述硬掩膜层上的氧化层。
3.根据权利要求1所述的改善FinFET器件性能的源漏外延形工艺方法，其特征在于：步骤一中的所述第一Fin结构的高度为30-90nm。
4.根据权利要求2所述的改善FinFET器件性能的源漏外延形工艺方法，其特征在于：步骤三中刻蚀去除所述栅结构顶部的所述侧墙包括：刻蚀去除所述氧化层顶部和所述氧化层顶部以下的一部分侧壁上的所述侧墙。
5.根据权利要求1所述的改善FinFET器件性能的源漏外延形工艺方法，其特征在于：步骤五中刻蚀去除所述凹槽侧壁的所述薄型氧化层的同时，与被刻蚀的所述薄型氧化层对应的第一Fin结构两侧的所述STI区也刻蚀形成STI凹槽。
6.根据权利要求1所述的改善FinFET器件性能的源漏外延形工艺方法，其特征在于：步骤五中刻蚀所述薄型氧化层的方法为各向异性刻蚀。
7.根据权利要求1所述的改善FinFET器件性能的源漏外延形工艺方法，其特征在于：步骤五中刻蚀去除所述凹槽侧壁的所述薄型氧化层的纵向厚度为3-10nm。
8.根据权利要求7所述的改善FinFET器件性能的源漏外延形工艺方法，其特征在于：步骤五中刻蚀去除所述凹槽侧壁的所述薄型氧化层的横向深度为2nm。
9.根据权利要求1所述的改善FinFET器件性能的源漏外延形工艺方法，其特征在于：步骤六中在所述数个凹槽的位置形成的外延层结构为SiGe或SiP。
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