CN1333441C - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
- Publication number
- CN1333441C CN1333441C CNB038118122A CN03811812A CN1333441C CN 1333441 C CN1333441 C CN 1333441C CN B038118122 A CNB038118122 A CN B038118122A CN 03811812 A CN03811812 A CN 03811812A CN 1333441 C CN1333441 C CN 1333441C
- Authority
- CN
- China
- Prior art keywords
- layer
- nitrogen
- gate electrode
- silicide
- nickel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910021334 nickel silicide Inorganic materials 0.000 title claims abstract description 37
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 title claims abstract description 37
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 90
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 61
- 238000009792 diffusion process Methods 0.000 claims abstract description 49
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 47
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 30
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 26
- 239000010703 silicon Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000010936 titanium Substances 0.000 claims abstract description 22
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052715 tantalum Inorganic materials 0.000 claims abstract description 18
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims abstract description 18
- 238000010438 heat treatment Methods 0.000 claims abstract description 16
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 15
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 12
- 238000000151 deposition Methods 0.000 claims abstract description 12
- 229910021332 silicide Inorganic materials 0.000 claims description 57
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 53
- 239000004065 semiconductor Substances 0.000 claims description 45
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 20
- 125000006850 spacer group Chemical group 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 17
- 239000007943 implant Substances 0.000 claims description 15
- 239000000203 mixture Substances 0.000 claims description 11
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 10
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 10
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 8
- 239000000428 dust Substances 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 8
- 150000003376 silicon Chemical class 0.000 claims description 8
- 238000002513 implantation Methods 0.000 claims description 7
- 150000003608 titanium Chemical class 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 4
- 150000002829 nitrogen Chemical class 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 2
- 230000008901 benefit Effects 0.000 description 17
- 229910052581 Si3N4 Inorganic materials 0.000 description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 229920005591 polysilicon Polymers 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 229910005881 NiSi 2 Inorganic materials 0.000 description 6
- 230000001788 irregular Effects 0.000 description 6
- 230000000149 penetrating effect Effects 0.000 description 6
- 230000008676 import Effects 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 229910005883 NiSi Inorganic materials 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 239000012212 insulator Substances 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 101100373011 Drosophila melanogaster wapl gene Proteins 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000035876 healing Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000001272 nitrous oxide Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000032696 parturition Effects 0.000 description 1
- 210000004483 pasc Anatomy 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/24—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- High Energy & Nuclear Physics (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
透过于下层硅化物(22、26)与硅化镍层(63、64)间形成扩散控制层(61、62)以实现具有显著降低界面不平整的硅化镍(63、64)结构。其包含离子植入氮(31、32)至该基材(20)以与栅电极(22)中,沉积钛或钽薄层(40),沉积镍层(50),并接着加热以于该下层硅化物(22、26)与硅化镍层(63、64)间的接口形成包含氮的扩散控制层(61、62)。
Description
技术领域
本发明是有关于半导体器件的制造,特别是有关于自我校准的硅化物技术及其所产生的半导体器件。更详而言之,本发明是有关可应用于具有深亚微米(deep sub-micron)型态的超大规模集成电路(ULSI)系统。
背景技术
当集成电路呈现几何级数的投入深亚微米型态中,精确的于需要信赖性的半导体基材上形成分离式组件(discreet)器件。高效能微处理器应用要求快速的半导体电路速度。半导体电路的速度随着互连(interconnection)系统的电阻或电容反向的变化。愈高的电阻乘电容的乘积值愈会限制电路运作速度。微小化要求具有小接点以及小断面(cross-section)的长互连(interconnect)。据此,持续减少设计标准进入深亚微米型态要求减少与该互连路径相关联的电阻与电容。因此,低电阻率的互连路径是制造密集、高效能器件的关键。
一种通常用以减少该互连的电阻率至低于单独多晶硅的电阻率,如15至300ohm/sq,的方法包含于掺杂多晶硅层上形成由低电阻材料,如耐火金属硅化物等,所组成的多层结构。此种结构的优点在于,因为多晶硅系直接形成于该栅极氧化物上,故该多晶硅栅极/互连结构可保持多晶硅现有的功能以及高度信赖性的多晶硅/硅氧化物接口。
多种的金属硅化物已应用于硅化物技术中,其可例如为钛、钨与钴等。然而相较于硅化物技术中的其它金属镍提供了特有的优点。于硅化镍中的镍其热预算(thermal budget)要求较低且可于大约摄氏250至600度的相对低的温度下透过单一加热步骤即可予以形成并伴随着减少该基材中硅的消耗,藉此而形成超浅(ultra-shallow)源极/漏极接面的结构。
当导入实验与研究至硅化镍结构的实现时,发现到高电阻硅化镍阶段(NiSi2)系形成掺杂的硅上并于其间产生不期望的不平整接口。此种接口的厚度可介于200至1000埃之间且可延伸如一微米的短距离。如此的界面不平整对于电阻率与电容会造成不利的冲击,且会导致穿入源极/漏极区域中或穿透栅极电介质层。此问题于绝缘层上覆硅结构中会特别的严重,其中如源极/漏极区域的穿入可能会穿透至底部阻障氧化物层并显著的增加接触电阻。
该不平整接口的结构系大略的如第1图所示,其中栅电极11系形成半导体基材10之上,该半导体基材10与栅电极11间则形成栅极电介质层12。电介质侧壁间隔13系形成于该栅电极11的侧表面上。并形成浅源极/漏极延伸部14以及适度的或浓密的源极/漏极区域15。沉积镍层后藉由加热造成硅化以于该源极/漏极区域15与栅电极11上分别产生硅化镍层16与硅化镍层17结构。介于硅化镍层16与基材10间的接口18以及介于该硅化镍层17与栅电极11间的接口19系非常不平整的且可能导致前述包含穿入该基材10与穿透栅极电介质层12等问题。
现有的解决方式系以大约摄氏600度的温度形成该NiSi2,而实际形成温度则为线宽与掺杂类型的函数。然而,当进一步导入实验与研究时,发现NiSi2可在非常低的温度下予以形成,即便该温度低于摄氏450度,如310度亦可予以形成。由于镍扩散的非常快速,因此极难防止NiSi2的形成,并进而造成不平整的接口。
于试图执行镍硅化的过程中已遭遇到额外的问题。于现有的硅化物技术中,在栅电极以及该源极/漏极区域曝露出的表面上沉积金属层后,加热俾使该金属与该下层硅化物反应藉以形成该金属硅化物。接着将未反应的金属自该电介质侧壁间隔移除,并留下与该栅电极的上表面以及源极/漏极区域接触的金属硅化物。于执行硅化物的技术中,复发现利用氮化硅侧壁间隔的优点,由于氮化硅具有高度的保形性并可增强器件的效能,特别对于P型晶体管而言更明显。然而,尽管氮化硅间隔于处理的观点上具有该些优点,却发现产生不具有不期望的硅化镍桥接的栅电极的镍硅化以及源极/漏极区域是极为困难的,且因此于两者间沿着该氮化硅侧壁间隔表面产生短路电路。
据此,目前需要一种具有在硅化镍层与下层硅化物间的接口上降低不平整的硅化镍互连的半导体器件,及其制造方法。此外亦需要在不会于该硅化镍层与源极/漏极间产生桥接的情况下执行硅化镍技术,特别是当利用于该栅电极上的氮化硅侧壁间隔时。
发明内容
本发明的一优点在于提供一种包含硅化镍层并降低介于硅化镍层与下层硅化物间的接口上的不平整的半导体器件。
本发明的另一优点在于提供一种降低介于硅化镍层与下层硅化物间的接口上的不平整的半导体器件制法。
本发明的又一优点在于提供一种具有与栅电极接触的硅化镍以及相关联的源极/漏极区域且不会沿着绝缘侧壁间隔,特别是氮化硅侧壁间隔而于该硅化镍与源极/漏极区域间产生桥接的半导体器件制法。
本发明的再一优点在于提供一种具有与栅电极接触的硅化镍以及相关联的源极/漏极区域且不会沿着绝缘侧壁间隔,特别是氮化硅侧壁间隔而于该硅化镍与源极/漏极区域间产生桥接的半导体器件。
本发明的其它优点与特征的一部分将揭露于本说明书中,而其它的部份则在本领域技术人员在阅读本说明书或通过实施本发明的过程中学习而变得显而易见。依据详细揭露于后述的权利要求本发明的优点可予以实现与取得。
依据本发明,部分前述以及其它的优点可通过一种半导体器件予以实现,该半导体器件包含:具有相对的侧边表面和上表面的硅栅电极,形成在硅半导体基材的上表面上,并且在该硅栅电极与该硅半导体基材的上表面之间具有栅极电介质层;形成于该栅电极的相对侧边上的半导体基材中的源极/漏极区域;形成于该栅电极的相对侧边上的电介质侧壁间隔;形成在该源极/漏极区域上及该栅电极的上表面上的含氮扩散控制层,其阻止镍扩散;以及形成于该含氮扩散控制层上的硅化镍层。
本发明的另一优点系提供一种半导体器件制造方法,该方法包含:在硅半导体基材的上表面上形成具有相对的侧边表面以及上表面的硅栅电极,并且在该硅栅电极与该硅半导体基材的上表面之间具有栅极电介质层;于该栅电极的相对侧边上形成电介质侧壁间隔;于该栅电极的相对侧边上的该半导体基材中形成源极/漏极区域;离子植入氮至该栅电极以及该栅电极的相对侧边上的半导体基材的曝露出的表面中;在该氮植入的栅电极上以及该半导体基材的氮植入的曝露出的表面上沉积钛层或钽层;在该钛层或钽层上沉积镍层;以及加热以形成:在该源极/漏极区域上及该栅电极的上表面上的含氮扩散控制层,其阻止镍扩散;以及在该含氮扩散控制层上的硅化镍层。
本发明的实施例包括离子植入氮至该栅电极与半导体基材中,沉积厚度大约10至50埃的钛层或钽层,沉积厚度大约100至200埃的镍层,以及例如于大约摄氏400至600度的温度下加热。于加热过程中,形成厚度大约10至50埃的扩散控制层,于沉积钛层的情况下,该扩散控制层包含氮硅化钛、氮硅化镍或氮硅化钛与氮硅化镍的混合物,或于沉积钽层的情况下,该扩散控制层包含氮硅化钽、氮硅化镍或氮硅化钽与氮硅化镍的混合物。本发明的实施例还包括于该栅电极的侧边表面以及邻接于该栅电极相对侧边表面的半导体的上表面上形成氧化硅衬里,以及其上形成氮化硅电介质侧壁间隔。
本发明其它的优点可通过以下详细的揭露而为本领域技术人员轻易了解,其中本发明的实施例系通过用以执行本发明的最佳实施例予以简化的揭露。同样须了解到,在所有不违背本发明的内容的情况下,本发明容许其它或不同的实施例,且其中的几个细节可在不同的显而易知的局面中予以修改。
附图说明
第1图用以概略的说明介于硅化镍层与下层硅化物间的接口中表面不平整的问题;以及
第2至7图用以概略的说明依据本发明的实施例的方法的连续阶段,其中相同的组件系以相同的组件符号表示。
具体实施方式
本发明的目的系用以解决当利用镍作为硅化用金属执行现有的硅化技术时所伴生的问题。其问题包括形成于该硅化镍层与下层硅化物间的极度不平整接口,如此的不平整会导致穿入并穿透至源极/漏极区域中,同时会穿透栅极电介质层。其它的问题则包括快速的消耗于栅电极中的硅会破坏现有多晶硅的功能以及高度可信赖的多晶硅/氧化硅接口。附带的问题复包括介于该栅电极上的硅化镍层以及相关联的源极/漏极区域上的硅化镍层间沿着氮化硅侧壁间隔表面产生硅化镍桥接。相信硅化镍桥接系起因于镍与结合于该氮化硅侧壁间隔中悬吊的硅反应所产生的。
本发明系部分起源于发现介于硅化镍层与下层硅化物间的接口不平整乃因NiSi2的结构所致生者,部分是因为快速的镍扩散之故,即使在温度低于期望值得的情况下亦同,特别是当器件呈几何级数的速度更深入的朝向次微米领域发展更为明显。即使是在仅有一微米的短距离中,此种遍布于不同距离的表面不平整的范围可从200至1000埃。NiSi2可在非常低温度下予以形成,此种低温度系伴随着镍的硅化而生的优点,然而不幸的是,因为镍的快速扩散以及NiSi2的形成,而导致不平整接口的产生。因此有需要透过防止NiSi2的形成,特别是肇因于快速的镍扩散,即使钴层亦同。
依据本发明,导致接口不平整问题的镍快速扩散以及NiSi2形成等问题已透过于该硅化镍层与下层硅化物间的接口形成扩散控制层而予以解决。该扩散控制曾阻止镍扩散至硅中并进一步减少硅扩散至上镍层中。
离子植入氮至该栅电极以及该栅电极相对侧边上的半导体基材曝露出的表面中以形成氮植入区域。接着沉积钛层或钽层,再于该钛层或钽层上沉积镍层;之后导入加热程序,于加热过程中在该硅化镍层与下层硅化物间的接口形成含氮扩散控制层。
假定于此所揭露的对象与指导,氮植入、各层的厚度以及加热条件等的理想状况可依据具体的状况而定。举例而言,发现到适合离子植入的植入剂量大约为5×1020至5×1021离子数/平方公分之间而植入能量大约为1至5千电子伏特之间。典型的,该栅电极包含多晶硅而该基材则包含掺杂的单晶硅。渗入至该栅电极中的氮的浓度较佳的浓于渗入于该基材中的浓度。典型的,形成于该基材中的氮植入区域在距离该基材上表面大约50至300埃处具有杂质浓度峰值,而形成于该栅电极中的氮植入区域在距离该栅电极上表面大约100至350埃处具有杂质浓度峰值。
钛或坦的反射(flash)层系沉积于该栅电极与基材的氮植入区域上,该钛或坦的反射层的厚度大约为10至50埃之间,而形成于该钛或坦的反射层上的镍层的厚度大约为100至200埃之间。接着导入的加热,例如其温度大约为摄氏400至600度。于加热过程中,在介于所产生的硅化镍层与下层硅化物之间的接口形成含氮扩散控制层。当沉积钛时,该含氮扩散控制层典型的包含氮硅化钛、氮硅化镍、或氮硅化钛与氮硅化镍的混合物。当沉积钽时,该含氮扩散控制层典型的包含氮硅化钽、氮硅化镍、或氮硅化钽与氮硅化镍的混合物。该扩散控制层典型的形成大约为10至50埃间的厚度,硅化镍层与在下层的扩散控制层所结合的厚度大约为50至300埃之间。
其优点在于,降低镍扩散的该扩散控制层的形成可阻止NiSi2的形成,并因而显著的降低接口的不平整性。此外,于该栅电极中的扩散控制层结构可防止因硅化镍结构以及该栅极电介质层的穿透而导致该栅电极的整体消耗。本发明的另一优点系源于减少因氮植入所导致结合于该氮化硅侧壁间隔的外部表面中硅悬吊的数量,藉以减少介于该栅电极上的硅化镍层以及相关联的源极/漏极区域上的硅化镍层间的硅化镍桥接。
本发明的1实施例大略的显示于第2至7图中,其中相同的组件有相同的组件符号。请参阅第2图,如掺杂有多晶硅的栅电极22系形成于半导体基材20上,该半导体基材20可为N型或P型基材,于该栅电极22与半导体基材20间则形成有栅极绝缘层21。该栅极绝缘层21典型的可为透过热氧化或化学气相沉积(CVD)等技术所形成的二氧化硅。依据本发明的实施例,厚度大约为130至170埃之间的薄氧化硅衬里23系形成于该栅电极22的相对侧边表面上。氧化硅衬里可透过等离子增强化学气相沉积(PECVD)技术利用在大约为50至100sccm流量的硅烷、大约为1000至4000sccm流量的氧化亚氮(N2O)、大约100至300瓦特的射频功率、大约为2.4至3.2托(Torr)的压力以及大约为摄氏380至420度间如400度的温度下予以形成。氧化硅衬里23有利于防止因自该栅电极21侧边表面所产生的硅化而造成的栅电极21消耗。
接续于该氧化硅衬里23形成之后,透过沉积保形层以形成氮化硅侧壁间隔24并随之予以异向性蚀刻。该氮化硅侧壁间隔可透过等离子增强化学气相沉积技术利用在大约为200至400sccm流量间如375sccm的硅烷、大约为2000至4000sccm流量间如2800sccm的氮、大约为2500至4000sccm流量间如3000sccm的氨、大约为250至400瓦特间如350瓦特的高频射频功率、大约为100至200瓦特间如140瓦特的低频射频功率、大约为1.6至2.2托间如1.9托的压力以及大约为摄氏380至420度间如400度的温度下予以形成。该氮化硅侧壁间隔典型的具有大约850至950埃间的厚度。
其次,依据本发明的实施例,如第3图的箭头30所示,离子植入氮至该栅电极22以及该栅电极22相对侧边上的基材20曝露出的表面中。据此,以形成氮植入区域31于该基材20中,并形成氮植入区域32于该栅电极22上表面中。
接着,如第4图所示,钛层或钽层40系沉积于该栅电极与该基材上。如第5图所示的镍层50接着沉积于该钛层或钽层40上。
请参阅第6图,接着导入加热程序,藉此行程含氮扩散控制层61形成于该源极/漏极区域中并于该含氮扩散控制层61上形成硅化镍层63。此外,含氮扩散控制层62该栅电极22上表面中,并于该含氮扩散控制层62上形成硅化镍层64。当该层40为钛层时,该扩散控制层61、62包含氮硅化钛与氮硅化镍的混合物。当该层40为钽层时,该扩散控制层61、62包含氮硅化钽与氮硅化镍的混合物。接着,如第7图所示,该钛层或钽层40与镍层50未反应的部份自该侧壁间隔予以移除。
于另一实施例中,在形成该源极/漏极区域后,溅镀沉积(sputterdeposited)氮化钛层或氮化钽层,透过于溅镀钛或钽时导入氮于该栅电极与基材曝露出的表面上。接着沉积镍层。再导入加热程序以形成包含氮硅化镍与氮硅化钛或氮硅化钽的混合物扩散控制层。
本发明透过策略性的植入氮至该基材与栅电极中,接着沉积钛或钽的反射层,沉积镍层并且然后予以加热。于加热过程中,形成于该基材与栅电极上的含氮扩散控制层可阻止镍扩散,并将硅化镍层与下层硅化物相分离。该扩散控制层相对的平滑并可防止该栅电极因镍所导致的穿入与消耗。因此有助于执行镍在显著的降低介于硅化镍层与下层硅化物间的接口的不平整的情况下予以硅化。此外,氮植入降低介于该栅电极上的硅化镍层以及相关联的源极/漏极区域上的硅化镍层间沿着氮化硅侧壁间隔表面所产生的桥接。
本发明于多种类型的半导体器件制程中具有产业利用性,该半导体器件包括绝缘层上硅(SOI)类型的半导体器件。本发明特别于具有深亚微米型态的设计特征的半导体器件制程中具有产业利用性。
于先前所详细的说明中,本发明的内容系透过参考特定的实施例予以描述。然而须了解到在不脱离后述本发明的申请专利范围中所界定的广泛的精神与范围的情况下予以修饰与变更。因此,于此的说明与图式仅用以例示性说明而非予以限制本发明的范围。应了解到本发明可利用不同的其它组合或环境并可在揭露于此的发明概念范围中予以变更或修饰。
Claims (9)
1.一种半导体器件,其包含:
具有相对的侧边表面和上表面的硅栅电极(22),形成在硅半导体基材(20)的上表面上,并且在该硅栅电极(22)与该硅半导体基材(20)的上表面之间具有栅极电介质层(21);
形成于该栅电极(22)的相对侧边上的半导体基材(20)中的源极/漏极区域(26);
形成于该栅电极(22)的相对侧边上的电介质侧壁间隔(24);
形成在该源极/漏极区域(26)上及该栅电极(22)的上表面上的含氮扩散控制层(61、62),其阻止镍扩散;以及
形成于该含氮扩散控制层(61、62)上的硅化镍层(63、64);
其中该含氮扩散控制层(61、62)包含氮硅化钛与氮硅化镍的混合物或氮硅化钽与氮硅化镍的混合物的其中之一。
2.如权利要求1所述的半导体器件,其中该含氮扩散控制层(61、62)具有10埃至50埃的厚度,而该含氮扩散控制层(61、62)与硅化镍层(63、64)结合的厚度是50埃至300埃。
3.一种半导体器件的制造方法,其包含:
在硅半导体基材(20)的上表面上形成具有相对的侧边表面以及上表面的硅栅电极(22),并且在该硅栅电极(22)与该硅半导体基材(20)的上表面之间具有栅极电介质层(21);
于该栅电极(22)的相对侧边表面上形成电介质侧壁间隔(24);
于该栅电极(22)的相对侧边上的该半导体基材(20)中形成源极/漏极区域(26);
离子植入氮(31、32)至该栅电极(22)以及该栅电极(22)的相对侧边上的半导体基材(20)的曝露出的表面中;
在该氮植入的栅电极(22)上以及该半导体基材(20)的氮植入的曝露出的表面上沉积钛层或钽层(40);
在该钛层或钽层(40)上沉积镍层(50);以及
加热以形成:
在该源极/漏极区域(26)上及该栅电极(22)的上表面上的含氮扩散控制层(61、62),其阻止镍扩散;以及
在该含氮扩散控制层(61、62)上的硅化镍层(63、64)。
4.如权利要求3所述的方法,包含于摄氏400至600度的温度下加热以形成厚度为10埃至50埃的该含氮扩散控制层(61、62)。
5.如权利要求3所述的方法,包含离子植入氮的植入剂量是5×1020至5×1021离子数/平方公分且植入能量是1千电子伏特至5千电子伏特之间。
6.如权利要求3、4或5所述的方法,包含离子植入氮以形成:
该基材(20)中的氮植入区域(31),该氮植入区域(31)在距离该半导体基材(20)的表面50埃至300埃深度处具有杂质浓度峰值;以及
该栅电极(22)中的氮植入层(32),该氮植入层(32)在距离该栅电极(22)的上表面100埃至350埃深度处具有杂质浓度峰值。
7.如权利要求3、4或5所述的方法,包含沉积厚度为10埃至50埃的钛层或钽层(40)。
8.如权利要求3、4或5所述的方法,包含沉积钛层(40),其中该含氮扩散控制层包含氮硅化钛、氮硅化镍,或氮硅化钛与氮硅化镍的混合物。
9.如权利要求3、4或5所述的方法,包含沉积钽层(40),其中该含氮扩散控制层包含氮硅化钽、氮硅化镍,或氮硅化钽与氮硅化镍的混合物。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/157,807 | 2002-05-31 | ||
US10/157,807 US6873051B1 (en) | 2002-05-31 | 2002-05-31 | Nickel silicide with reduced interface roughness |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1656605A CN1656605A (zh) | 2005-08-17 |
CN1333441C true CN1333441C (zh) | 2007-08-22 |
Family
ID=32228405
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB038118122A Expired - Lifetime CN1333441C (zh) | 2002-05-31 | 2003-05-13 | 半导体器件及其制造方法 |
Country Status (9)
Country | Link |
---|---|
US (2) | US6873051B1 (zh) |
EP (1) | EP1509947B1 (zh) |
JP (1) | JP4866549B2 (zh) |
KR (1) | KR101117320B1 (zh) |
CN (1) | CN1333441C (zh) |
AU (1) | AU2003299495A1 (zh) |
DE (1) | DE60304225T2 (zh) |
TW (1) | TWI289328B (zh) |
WO (1) | WO2004040622A2 (zh) |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6440851B1 (en) * | 1999-10-12 | 2002-08-27 | International Business Machines Corporation | Method and structure for controlling the interface roughness of cobalt disilicide |
KR100870176B1 (ko) * | 2003-06-27 | 2008-11-25 | 삼성전자주식회사 | 니켈 합금 샐리사이드 공정, 이를 사용하여 반도체소자를제조하는 방법, 그에 의해 형성된 니켈 합금 실리사이드막및 이를 사용하여 제조된 반도체소자 |
JP2005072264A (ja) * | 2003-08-25 | 2005-03-17 | Seiko Epson Corp | トランジスタの製造方法、トランジスタ、回路基板、電気光学装置及び電子機器 |
US20050056881A1 (en) * | 2003-09-15 | 2005-03-17 | Yee-Chia Yeo | Dummy pattern for silicide gate electrode |
BE1015721A3 (nl) * | 2003-10-17 | 2005-07-05 | Imec Inter Uni Micro Electr | Werkwijze voor het reduceren van de contactweerstand van de aansluitgebieden van een halfgeleiderinrichting. |
JP3879003B2 (ja) * | 2004-02-26 | 2007-02-07 | 国立大学法人名古屋大学 | シリサイド膜の作製方法 |
US7253125B1 (en) | 2004-04-16 | 2007-08-07 | Novellus Systems, Inc. | Method to improve mechanical strength of low-k dielectric film using modulated UV exposure |
US7132352B1 (en) * | 2004-08-06 | 2006-11-07 | Advanced Micro Devices, Inc. | Method of eliminating source/drain junction spiking, and device produced thereby |
JP2006060045A (ja) * | 2004-08-20 | 2006-03-02 | Toshiba Corp | 半導体装置 |
US9659769B1 (en) * | 2004-10-22 | 2017-05-23 | Novellus Systems, Inc. | Tensile dielectric films using UV curing |
JP2006261635A (ja) | 2005-02-21 | 2006-09-28 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
US8889233B1 (en) | 2005-04-26 | 2014-11-18 | Novellus Systems, Inc. | Method for reducing stress in porous dielectric films |
US8980769B1 (en) | 2005-04-26 | 2015-03-17 | Novellus Systems, Inc. | Multi-station sequential curing of dielectric films |
US8454750B1 (en) | 2005-04-26 | 2013-06-04 | Novellus Systems, Inc. | Multi-station sequential curing of dielectric films |
KR100679224B1 (ko) * | 2005-11-04 | 2007-02-05 | 한국전자통신연구원 | 반도체 소자 및 그 제조방법 |
JP5042517B2 (ja) * | 2006-04-10 | 2012-10-03 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP4920310B2 (ja) * | 2006-05-30 | 2012-04-18 | 株式会社東芝 | 半導体装置およびその製造方法 |
WO2008035490A1 (fr) * | 2006-09-20 | 2008-03-27 | Nec Corporation | Dispositif à semi-conducteur et son procédé de fabrication |
US8465991B2 (en) * | 2006-10-30 | 2013-06-18 | Novellus Systems, Inc. | Carbon containing low-k dielectric constant recovery using UV treatment |
US10037905B2 (en) | 2009-11-12 | 2018-07-31 | Novellus Systems, Inc. | UV and reducing treatment for K recovery and surface clean in semiconductor processing |
US20090004851A1 (en) * | 2007-06-29 | 2009-01-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Salicidation process using electroless plating to deposit metal and introduce dopant impurities |
US8211510B1 (en) | 2007-08-31 | 2012-07-03 | Novellus Systems, Inc. | Cascaded cure approach to fabricate highly tensile silicon nitride films |
DE102008035809B3 (de) * | 2008-07-31 | 2010-03-25 | Advanced Micro Devices, Inc., Sunnyvale | Technik zum Verringern der Silizidungleichmäßigkeiten in Polysiliziumgateelektroden durch eine dazwischenliegende Diffusionsblockierschicht |
US9050623B1 (en) | 2008-09-12 | 2015-06-09 | Novellus Systems, Inc. | Progressive UV cure |
US20110001169A1 (en) * | 2009-07-01 | 2011-01-06 | International Business Machines Corporation | Forming uniform silicide on 3d structures |
CN102593173B (zh) * | 2011-01-18 | 2015-08-05 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
CN102593174B (zh) * | 2011-01-18 | 2015-08-05 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
US9607842B1 (en) * | 2015-10-02 | 2017-03-28 | Asm Ip Holding B.V. | Methods of forming metal silicides |
US9847221B1 (en) | 2016-09-29 | 2017-12-19 | Lam Research Corporation | Low temperature formation of high quality silicon oxide films in semiconductor device manufacturing |
EP4199110A4 (en) | 2021-01-14 | 2024-04-10 | Changxin Memory Technologies, Inc. | MANUFACTURING METHOD FOR ONE SEMICONDUCTOR STRUCTURE AND TWO SEMICONDUCTOR STRUCTURES |
CN112864240B (zh) * | 2021-01-14 | 2022-05-31 | 长鑫存储技术有限公司 | 半导体结构的制造方法及两种半导体结构 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5545575A (en) * | 1994-10-24 | 1996-08-13 | Motorola, Inc. | Method for manufacturing an insulated gate semiconductor device |
US5950098A (en) * | 1995-06-26 | 1999-09-07 | Mitsubishi Denki Kabushiki Kaisha | Manufacturing method of a semiconductor device with a silicide layer |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62183180A (ja) * | 1986-02-07 | 1987-08-11 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
US5170242A (en) * | 1989-12-04 | 1992-12-08 | Ramtron Corporation | Reaction barrier for a multilayer structure in an integrated circuit |
US5545574A (en) | 1995-05-19 | 1996-08-13 | Motorola, Inc. | Process for forming a semiconductor device having a metal-semiconductor compound |
US5648287A (en) * | 1996-10-11 | 1997-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of salicidation for deep quarter micron LDD MOSFET devices |
US6180469B1 (en) * | 1998-11-06 | 2001-01-30 | Advanced Micro Devices, Inc. | Low resistance salicide technology with reduced silicon consumption |
US5970370A (en) * | 1998-12-08 | 1999-10-19 | Advanced Micro Devices | Manufacturing capping layer for the fabrication of cobalt salicide structures |
JP2000307110A (ja) * | 1999-04-23 | 2000-11-02 | Mitsubishi Electric Corp | 半導体装置の製造方法及び半導体装置 |
US6228730B1 (en) * | 1999-04-28 | 2001-05-08 | United Microelectronics Corp. | Method of fabricating field effect transistor |
US6281102B1 (en) * | 2000-01-13 | 2001-08-28 | Integrated Device Technology, Inc. | Cobalt silicide structure for improving gate oxide integrity and method for fabricating same |
US6483154B1 (en) * | 2000-10-05 | 2002-11-19 | Advanced Micro Devices, Inc. | Nitrogen oxide plasma treatment for reduced nickel silicide bridging |
US6465349B1 (en) * | 2000-10-05 | 2002-10-15 | Advanced Micro Devices, Ins. | Nitrogen-plasma treatment for reduced nickel silicide bridging |
US6602754B1 (en) * | 2001-02-02 | 2003-08-05 | Advanced Micro Devices, Inc. | Nitrogen implant into nitride spacer to reduce nickel silicide formation on spacer |
US6432805B1 (en) * | 2001-02-15 | 2002-08-13 | Advanced Micro Devices, Inc. | Co-deposition of nitrogen and metal for metal silicide formation |
US6339021B1 (en) * | 2001-05-09 | 2002-01-15 | Chartered Semiconductor Manufacturing Ltd. | Methods for effective nickel silicide formation |
US6495460B1 (en) * | 2001-07-11 | 2002-12-17 | Advanced Micro Devices, Inc. | Dual layer silicide formation using a titanium barrier to reduce surface roughness at silicide/junction interface |
-
2002
- 2002-05-31 US US10/157,807 patent/US6873051B1/en not_active Expired - Lifetime
-
2003
- 2003-05-13 WO PCT/US2003/014982 patent/WO2004040622A2/en active IP Right Grant
- 2003-05-13 AU AU2003299495A patent/AU2003299495A1/en not_active Abandoned
- 2003-05-13 CN CNB038118122A patent/CN1333441C/zh not_active Expired - Lifetime
- 2003-05-13 DE DE60304225T patent/DE60304225T2/de not_active Expired - Lifetime
- 2003-05-13 JP JP2004548264A patent/JP4866549B2/ja not_active Expired - Lifetime
- 2003-05-13 KR KR1020047019537A patent/KR101117320B1/ko active IP Right Grant
- 2003-05-13 EP EP03799782A patent/EP1509947B1/en not_active Expired - Lifetime
- 2003-05-19 TW TW092113429A patent/TWI289328B/zh not_active IP Right Cessation
-
2005
- 2005-01-26 US US11/042,194 patent/US6967160B1/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5545575A (en) * | 1994-10-24 | 1996-08-13 | Motorola, Inc. | Method for manufacturing an insulated gate semiconductor device |
US5950098A (en) * | 1995-06-26 | 1999-09-07 | Mitsubishi Denki Kabushiki Kaisha | Manufacturing method of a semiconductor device with a silicide layer |
Also Published As
Publication number | Publication date |
---|---|
JP4866549B2 (ja) | 2012-02-01 |
US6967160B1 (en) | 2005-11-22 |
KR101117320B1 (ko) | 2012-03-22 |
WO2004040622A3 (en) | 2004-07-22 |
AU2003299495A1 (en) | 2004-05-25 |
KR20050005524A (ko) | 2005-01-13 |
JP2005539402A (ja) | 2005-12-22 |
EP1509947B1 (en) | 2006-03-22 |
WO2004040622A2 (en) | 2004-05-13 |
AU2003299495A8 (en) | 2004-05-25 |
TWI289328B (en) | 2007-11-01 |
CN1656605A (zh) | 2005-08-17 |
US6873051B1 (en) | 2005-03-29 |
DE60304225T2 (de) | 2006-12-14 |
DE60304225D1 (de) | 2006-05-11 |
EP1509947A2 (en) | 2005-03-02 |
TW200403731A (en) | 2004-03-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1333441C (zh) | 半导体器件及其制造方法 | |
US4945070A (en) | Method of making cmos with shallow source and drain junctions | |
EP0109082B1 (en) | Method of manufacturing a semiconductor device comprising a diffusion step | |
CA1203642A (en) | Method for the manufacture of integrated mos-filed effect transistor circuits in silicon gate technology having diffusion zones coated with silicide as low-impedance printed conductors | |
US6713392B1 (en) | Nitrogen oxide plasma treatment for reduced nickel silicide bridging | |
US8178409B2 (en) | Semiconductor device with alternately arranged P-type and N-type thin semiconductor layers and method for manufacturing the same | |
US20070099421A1 (en) | Methods For Forming Cobalt Layers Including Introducing Vaporized Cobalt Precursors And Methods For Manufacturing Semiconductor Devices Using The Same | |
MY136344A (en) | Low temperature formation of backside ohmic contacts for vertical devices | |
US5801086A (en) | Process for formation of contact conductive layer in a semiconductor device | |
JP2003023152A (ja) | Mis型トランジスタ及びその製造方法 | |
US6661067B1 (en) | Nitrogen-plasma treatment for reduced nickel silicide bridging | |
US5712196A (en) | Method for producing a low resistivity polycide | |
KR20050084030A (ko) | 도핑된 고유전 측벽 스페이서들을 구비한 전계 효과트랜지스터의 드레인/소스 확장 구조 | |
JPS615524A (ja) | Cmos装置の製造方法 | |
US6545370B1 (en) | Composite silicon nitride sidewall spacers for reduced nickel silicide bridging | |
JP2003203976A (ja) | 半導体素子の金属配線形成方法 | |
Runovc et al. | Titanium disilicide in MOS technology | |
JP4749654B2 (ja) | ニッケルシリサイドのブリッジを減じるためのシリコン酸化物ライナ | |
JPH0689904A (ja) | 絶縁ゲイト型電界効果半導体装置の作製方法 | |
JP3225696B2 (ja) | 成膜方法 | |
JPH0235720A (ja) | Mos型半導体装置の製造方法 | |
KR100197982B1 (ko) | 모스 전계 효과 트랜지스터의 제조방법 | |
JPH06302682A (ja) | 半導体装置の製造方法 | |
KR100331275B1 (ko) | 티타늄 폴리사이드 게이트전극의 형성방법 | |
KR100356817B1 (ko) | 반도체장치의 콘택 형성방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CX01 | Expiry of patent term | ||
CX01 | Expiry of patent term |
Granted publication date: 20070822 |