CN1326242C - 半导体集成电路器件 - Google Patents

半导体集成电路器件 Download PDF

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Publication number
CN1326242C
CN1326242C CNB031424384A CN03142438A CN1326242C CN 1326242 C CN1326242 C CN 1326242C CN B031424384 A CNB031424384 A CN B031424384A CN 03142438 A CN03142438 A CN 03142438A CN 1326242 C CN1326242 C CN 1326242C
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CN
China
Prior art keywords
circuit
power supply
input
side power
potential side
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB031424384A
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English (en)
Chinese (zh)
Other versions
CN1467844A (zh
Inventor
刘藤佳代子
楠贡
石塚裕康
益田信一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Solutions Technology Ltd
Original Assignee
Hitachi Ltd
Hitachi ULSI Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi ULSI Systems Co Ltd filed Critical Hitachi Ltd
Publication of CN1467844A publication Critical patent/CN1467844A/zh
Application granted granted Critical
Publication of CN1326242C publication Critical patent/CN1326242C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/18—Peripheral circuit regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Manipulation Of Pulses (AREA)
CNB031424384A 2002-06-10 2003-06-09 半导体集成电路器件 Expired - Fee Related CN1326242C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002168680A JP4043855B2 (ja) 2002-06-10 2002-06-10 半導体集積回路装置
JP168680/2002 2002-06-10

Publications (2)

Publication Number Publication Date
CN1467844A CN1467844A (zh) 2004-01-14
CN1326242C true CN1326242C (zh) 2007-07-11

Family

ID=29706811

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB031424384A Expired - Fee Related CN1326242C (zh) 2002-06-10 2003-06-09 半导体集成电路器件

Country Status (5)

Country Link
US (1) US6828842B2 (enExample)
JP (1) JP4043855B2 (enExample)
KR (1) KR20030095349A (enExample)
CN (1) CN1326242C (enExample)
TW (1) TWI286380B (enExample)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100569558B1 (ko) * 2003-11-10 2006-04-10 주식회사 하이닉스반도체 전원 제어 기능을 갖는 불휘발성 강유전체 메모리 장치
US7098717B2 (en) * 2004-06-25 2006-08-29 Altera Corporation Gate triggered ESD clamp
JP4942007B2 (ja) 2004-10-25 2012-05-30 ルネサスエレクトロニクス株式会社 半導体集積回路
US7859301B2 (en) * 2007-04-30 2010-12-28 Altera Corporation Power regulator circuitry for programmable logic device memory elements
US7692975B2 (en) 2008-05-09 2010-04-06 Micron Technology, Inc. System and method for mitigating reverse bias leakage
JP2009283610A (ja) * 2008-05-21 2009-12-03 Elpida Memory Inc Ｅｓｄ保護回路
DE102008034109B4 (de) * 2008-07-21 2016-10-13 Dspace Digital Signal Processing And Control Engineering Gmbh Schaltung zur Nachbildung einer elektrischen Last
US8238067B2 (en) * 2008-12-11 2012-08-07 Ati Technologies Ulc Electrostatic discharge circuit and method
JP2011228372A (ja) * 2010-04-16 2011-11-10 Toshiba Corp 半導体集積回路装置
TWI422008B (zh) 2010-05-24 2014-01-01 Au Optronics Corp 靜電防護電路及採用此種靜電防護電路之顯示裝置
CN101859764B (zh) * 2010-06-03 2012-02-08 友达光电股份有限公司 静电防护电路及采用此种静电防护电路的显示装置
JP5656658B2 (ja) * 2011-01-14 2015-01-21 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 半導体装置
JP2013055102A (ja) 2011-09-01 2013-03-21 Sony Corp 半導体集積回路及び保護回路
JP2014229624A (ja) 2013-05-17 2014-12-08 ソニー株式会社 半導体装置および電子機器
JP5710706B2 (ja) * 2013-07-29 2015-04-30 アギア システムズ エルエルシーＡｇｅｒｅ Ｓｙｓｔｅｍｓ ＬＬＣ 静電気放電保護回路
JP2016035958A (ja) 2014-08-01 2016-03-17 ソニー株式会社 保護素子、保護回路及び半導体集積回路
CN111584490A (zh) * 2015-02-26 2020-08-25 杭州海存信息技术有限公司 分离的三维纵向存储器
US10734806B2 (en) 2016-07-21 2020-08-04 Analog Devices, Inc. High voltage clamps with transient activation and activation release control
JP6623139B2 (ja) 2016-10-24 2019-12-18 株式会社東芝 Ｅｓｄ保護回路
US10861845B2 (en) * 2016-12-06 2020-12-08 Analog Devices, Inc. Active interface resistance modulation switch
US11387648B2 (en) 2019-01-10 2022-07-12 Analog Devices International Unlimited Company Electrical overstress protection with low leakage current for high voltage tolerant high speed interfaces
TWI735909B (zh) * 2019-07-10 2021-08-11 瑞昱半導體股份有限公司 靜電放電保護電路以及運作方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1163483A (zh) * 1996-04-19 1997-10-29 松下电器产业株式会社 半导体集成电路及采用该电路的系统
JPH10243639A (ja) * 1997-02-27 1998-09-11 Hitachi Ltd 電源回路
US5886558A (en) * 1995-08-31 1999-03-23 Sanyo Electric Co., Ltd. Semiconductor unit
US5907464A (en) * 1997-03-24 1999-05-25 Intel Corporation MOSFET-based power supply clamps for electrostatic discharge protection of integrated circuits
US6400546B1 (en) * 1999-09-02 2002-06-04 Ati International Srl I/O pad voltage protection circuit and method

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10303314A (ja) 1997-04-24 1998-11-13 Toshiba Microelectron Corp 半導体集積回路
JPH11243639A (ja) 1998-02-24 1999-09-07 Asahi Kasei Micro Syst Co Ltd 半導体回路
US6181193B1 (en) * 1999-10-08 2001-01-30 International Business Machines Corporation Using thick-oxide CMOS devices to interface high voltage integrated circuits
US6462601B1 (en) * 2001-05-11 2002-10-08 Faraday Technology Corp. Electrostatic discharge protection circuit layout
JP2002344251A (ja) * 2001-05-22 2002-11-29 Oki Electric Ind Co Ltd オフリーク電流キャンセル回路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5886558A (en) * 1995-08-31 1999-03-23 Sanyo Electric Co., Ltd. Semiconductor unit
CN1163483A (zh) * 1996-04-19 1997-10-29 松下电器产业株式会社 半导体集成电路及采用该电路的系统
JPH10243639A (ja) * 1997-02-27 1998-09-11 Hitachi Ltd 電源回路
US5907464A (en) * 1997-03-24 1999-05-25 Intel Corporation MOSFET-based power supply clamps for electrostatic discharge protection of integrated circuits
US6400546B1 (en) * 1999-09-02 2002-06-04 Ati International Srl I/O pad voltage protection circuit and method

Also Published As

Publication number Publication date
JP4043855B2 (ja) 2008-02-06
TWI286380B (en) 2007-09-01
US6828842B2 (en) 2004-12-07
TW200402140A (en) 2004-02-01
KR20030095349A (ko) 2003-12-18
US20030227304A1 (en) 2003-12-11
JP2004014929A (ja) 2004-01-15
CN1467844A (zh) 2004-01-14

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C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CI01 Publication of corrected invention patent application

Correction item: Inventor

Correct: Saito Kayoko

False: Son of the Liu Dynasty

Number: 28

Page: 1202

Volume: 23

CI03 Correction of invention patent

Correction item: Inventor

Correct: Saito Kayoko

False: Son of the Liu Dynasty

Number: 28

Page: The title page

Volume: 23

ERR Gazette correction

Free format text: CORRECT: INVENTOR; FROM: LIUTENG JIADAIZI TO: SAITO CHELDZEL

C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20070711

Termination date: 20110609