CN1326226A - 半导体器件的载体衬底的电极结构 - Google Patents

半导体器件的载体衬底的电极结构 Download PDF

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CN1326226A
CN1326226A CN01116915A CN01116915A CN1326226A CN 1326226 A CN1326226 A CN 1326226A CN 01116915 A CN01116915 A CN 01116915A CN 01116915 A CN01116915 A CN 01116915A CN 1326226 A CN1326226 A CN 1326226A
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semiconductor device
electrode
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水崎学
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Abstract

本发明的目的是提供一种半导体器件的载体衬底的电极结构,其中半导体封装的电极与主衬底的电极之间的结合部分的强度和可靠性得到改进。作为一个载体衬底(102)的电极、传统上是圆柱形的焊接区(103)在其内部可具有一个同心的半球面空心部分,并且在其圆周部分设置一个凸缘部分,凸缘部分的外径对应于传统的圆柱体的外径。在凸缘部分和邻近凸缘部分的焊接区(103)的壁表面的部分中设置两个狭口(104),用于释出空气。在载体衬底(102)中朝向外表面设置一个半球面凹进,并且焊接区(103)固定地与载体衬底(102)相接触,使得焊接区(103)安装在凹进中,并且凸缘部分邻接载体衬底的外表面。

Description

半导体器件的载体衬底的电极结构
本发明涉及一种用于焊接至一个主衬底的半导体器件的电极结构。
为了将例如便携式电话、视频摄像机和个人计算机的个人家用电器制造得小型、紧凑及重量轻，半导体器件的封装已从具有鸥翼(gull-wing)型引导电极的LSI封装改变为紧凑的、重量轻的封装的BGA(ball grid array，球栅阵)型或CSP(chip scale package，芯片尺寸封装)型。图5是一个BGA型封装半导体器件的外形图，(a)是侧视图，(b)是底视图。图6是图5的BGA型封装半导体器件被焊接至一个主衬底的状态的部分侧视图。安装在一个载体衬底502上并且在图中未示出的半导体元件被密封在包括一个树脂部分501和载体衬底502的封装之中，半导体元件的外端通过一个焊接区503连接至外部，该焊接区是一个栅状地设置在载体衬底502上的电极。在半导体器件安装其中的主衬底601中，在对应于半导体器件的载体衬底502的焊接区503的位置设置一个焊接区602，它通过焊料603焊接至半导体衬底的焊接区503。焊接区503和焊接区603两者具有低高度的圆柱形状，它们的上表面通常是平滑的平面，并且该两区的平滑的上表面通过焊料603被焊接。
由于封装的小型化，焊接区的间隔变窄、面积变小，于是，已出现采用焊料而得到的焊接区的结合强度和可靠性变低的问题。
本发明的目的是提供一种半导体器件的载体衬底的电极结构，其中半导体封装的电极与主衬底的电极之间的结合部分的强度和可靠性得到改进。
本发明的一种半导体器件的载体衬底的电极结构是一种用于将所述半导体器件焊接至一个主衬底的半导体器件的载体衬底的电极结构，其中，在所述电极的中心区域形成一个凹进部分，并且所述电极具有一个通过所述凹进部分和围绕所述中心区域的所述凹进部分的一个圆周壁的外部分之间的穿通部分，位于所述圆周壁表面上。
所述电极可以是具有一个凸缘部分的半球形，并且在其内部可具有一个同心的半球面空心部分，所述电极的半球形部分可以安装在设置在所述半导体器件的载体衬底的一个外表面上的半球形凹进部分中，并且所述电极可固定地与所述载体衬底相接触，使得所述凸缘部分邻接所述载体衬底的外表面。通过所述凹进部分和所述壁表面的外部分之间的所述穿通部分可以是至少一个设置在所述凸缘部分和邻近所述凸缘部分的所述电极的壁表面中的狭口。
所述电极可以是具有一个凸缘部分的圆柱形，并且在其内部可具有一个同心的圆柱形空心部分，所述电极的圆柱形部分可以安装在设置在所述半导体器件的载体衬底的一个外表面上的圆柱形凹进部分中，并且所述电极可固定地与所述载体衬底相接触，使得所述凸缘部分邻接所述载体衬底的外表面。通过所述凹进部分和所述壁表面的外部分之间的所述穿通部分可以是至少一个设置在所述凸缘部分和邻近所述凸缘部分至靠近一个底部的所述电极的圆柱形壁表面中的狭口。
所述半导体器件的封装可以是BGA形或CSP型。
通过在电极的中心区域形成一个凹进，焊接区和焊料之间的结合得以增强，并且所述结合是三维的。而且，由于设置有一个连接凹进和壁表面的外部分的穿通部分，其内部的空气释出，并且焊料变湿且在凹进中完全分布，据此，采用少量的焊料就可达到同样的强度结合，并且载体衬底和主衬底之间的间隔可收窄。
图1是示出本发明的第一实施例的半导体器件的载体衬底的电极结构的示意图，并且(a)是一个平面图，(b)是沿(a)的A-A线的侧视剖面图，(c)是沿(a)的B-B线的侧视剖面图；
图2是图1的半导体器件的载体衬底被焊接至一个主衬底的状态的部分侧视图；
图3是示出本发明的第二实施例的半导体器件的载体衬底的电极结构的示意图，并且(a)是一个平面图，(b)是沿(a)的C-C线的侧视剖面图；
图4是图3的半导体器件的载体衬底被焊接至一个主衬底的状态的部分侧视图；
图5是一个BGA型封装半导体器件的外形图，并且(a)是侧视图，(b)是底视图；和
图6是图5的BGA型封装半导体器件被焊接至一个主衬底的状态的部分侧视图。
本发明的目的是改进焊接区的结构，它是用于改进半导体器件的焊料结合部分的可靠性、特别是改进LSI的球栅阵(以下称为BGA)封装和芯片尺寸封装(以下称为CSP)中的焊接区的结构的一种电极。
接着，参照附图对本发明的实施例进行解释。图1是示出本发明的第一实施例的半导体器件的载体衬底的电极结构的示意图，并且(a)是一个平面图，(b)是沿(a)的A-A线的侧视剖面图，(c)是沿(a)的B-B线的侧视剖面图。图2是图1的半导体器件的载体衬底被焊接至一个主衬底的状态的部分侧视图。
参照图1，在第一实施例中，作为一个载体衬底102的电极、传统上是圆柱形的焊接区103在其内部可具有一个同心的半球面空心部分，并且在其圆周部分设置一个凸缘部分，凸缘部分的外径对应于传统的圆柱体的外径。在凸缘部分和邻近凸缘部分的焊接区103的壁表面的的部分中设置两个狭口104，用于释出空气。在载体衬底102中朝向外表面设置一个半球面凹进，并且焊接区103固定地与载体衬底102相接触，使得焊接区103安装在凹进中，并且凸缘部分邻接载体衬底的外表面。
安装在载体衬底102上并且未示出的一个半导体元件被密封在包括一个树脂部分101和载体衬底102的封装之中，半导体元件的外端通过焊接区103连接至外部，该焊接区是一个栅状地设置在载体衬底102上的电极。
如图2所示，在半导体器件安装其中的主衬底201中，在对应于半导体器件的载体衬底102的焊接区103的位置设置一个焊接区202，在主衬底201上已印制有焊料。然后，具有带凹进的半球形焊接区103的BGA和CSP被安装在主衬底201上，使得主衬底201的焊接区202和与之对应的BGA和CSP的焊接区103相匹配。
然后，将这些部件置入一个回流炉以进行焊接，印制的焊料203被熔化，焊料203变湿且开始分布在主衬底201的焊接区202和BGA和CSP的焊接区103上。空气淤塞在BGA和CSP的焊接区103的凹进中，通常，空气防止焊料203进入凹进之中。然而，在本发明的第一实施例中，由于凹进中的空气通过图1所示的狭口104释出，可使焊料203变湿并且完全分布在凹进之中。当从回流炉中取出这些部件时，焊料变硬，载体衬底102的焊接区202被焊接到主衬底201的焊接区202上。
通过将焊接区103的结构从传统的平面改变成凹进，焊料结合区域可以增加，并且结合部分的可靠性可以改进。
在上述解释中，虽然焊接区103的形状是其内部具有一个同心的半球面空心部分的半球形，并且在其圆周部分中设置一个凸缘，但其形状可以是其内部具有一个同心的半球面空心部分的圆柱形，并且可以设置一个用于释出空气的狭口。
接着，参照附图对本发明的第二实施例进行解释。图3是示出本发明的第二实施例的半导体器件的载体衬底的电极结构的示意图，并且(a)是一个平面图，(b)是沿(a)的C-C线的侧视剖面图。图4是图3的半导器件的载体衬底被焊接至一个主衬底的状态的部分侧视图。
参照图3，在第二实施例中，作为一个载体衬底302的电极、传统上是圆柱形的焊接区303在其内部可具有一个同心的半球面空心部分，并且在其上部的圆周部分设置一个凸缘部分，凸缘部分的外径对应于传统的圆柱体的外径。这是类似于穿通孔的结构，并且可通过类似的制造方法形成。在凸缘部分和邻近凸缘部分至靠近底部面的位置的壁表面中设置两个狭口304，用于释出空气。在载体衬底302中朝向外表面设置一个圆柱形凹进，并且焊接区203固定地与载体衬底302相接触，使得焊接区303安装在凹进中，并且凸缘部分邻接载体衬底的外表面。
安装在载体衬底302上并且未示出的一个半导体元件被密封在包括一个树脂部分301和载体衬底302的封装之中，半导体元件的外端通过焊接区303连接至外部，该焊接区是一个栅状地设置在载体衬底302上的电极。
如图4所示，在半导体器件安装其中的主衬底401中，在对应于半导体器件的载体衬底302的焊接区303的位置设置一个焊接区402，在主衬底401上已印制有焊料。然后，具有带空心部分的圆柱形焊接区303的BGA和CSP被安装在主衬底401上，使得主衬底401的焊接区402和与之对应的BGA和CSP的焊接区303相匹配。
然后，将这些部件置入一个回流炉以进行焊接，印制的焊料403被熔化，焊料403变湿且开始分布在主衬底401的焊接区402和BGA和CSP的焊接区303上。空气淤塞在BGA和CSP的焊接区303的空心部分中，通常，空气防止焊料403进入空心部分之中。然而，在本发明的第二实施例中，由于空心部分中的空气通过图3所示的狭口304释出，可使焊料403变湿并且完全分布。当从回流炉中取出这些部件时，焊料变硬，载体衬底302的焊接区303被焊接到主衬底401的焊接区402上。
通过将焊接区303的结构从传统的平面改变成具有空心部分的圆柱形，焊料结合区域可以增加，并且结合部分的可靠性可以改进。
如上所述，本发明产生以下有益效果。
第一个有益效果是可以改进焊料结合部分的强度和可靠性。这是因为焊接区与焊料之间的结合区域增加，并且结合是三维的。
第二个有益效果是，由于焊料结合部分的焊料量减少，安装高度可受到限制。这是因为由于焊接区与焊料之间的结合变成三维的、并且由此焊料进入焊接区的内部，所以通过少量的焊料可以达到同样的强度，并且载体衬底和主衬底之间的间隔可以变窄。

Claims (7)

1.一种半导体器件的载体衬底的电极结构，用于将所述半导体器件焊接至一个主衬底，其中，在所述电极的中心区域设置一个凹进，并且所述电极还具有在位于围绕所述中心区域的一个圆周壁表面上的一个通过在所述壁表面中的围绕所述中心区域的所述凹陷的穿通部分。
2.根据权利要求1所述的半导体器件的载体衬底的电极结构，其特征在于，所述电极是具有一个凸缘部分并且在其内部具有一个同心的半球面空心部分的的半球形结构，其中，所述电极的所述半球形部分安装在设置在所述半导体器件的所述载体衬底的一个外表面上的半球形凹进中，并且所述电极固定地与所述载体衬底相接触，使得所述凸缘部分邻接所述载体衬底的外表面。
3.根据权利要求2所述的半导体器件的载体衬底的电极结构，其特征在于，所述通过所述凹进和所述壁表面的所述外部分之间的穿通部分是至少一个设置在所述凸缘部分和邻近所述凸缘部分的所述电极的所述壁表面中的狭口。
4.根据权利要求1所述的半导体器件的载体衬底的电极结构，其特征在于，所述电极是具有一个凸缘部分并且在其内部具有一个同心的圆柱形空心部分的圆柱形，所述电极的所述圆柱形部分安装在设置在所述半导体器件的载体衬底的一个外表面上的一个圆柱形凹进中，并且所述电极可固定地与所述载体衬底相接触，使得所述凸缘部分邻接所述载体衬底的所述外表面。
5.根据权利要求4所述的半导体器件的载体衬底的电极结构，其特征在于，通过所述凹进和所述壁表面的所述外部分之间的所述穿通部分是至少一个设置在所述凸缘部分和邻近所述凸缘部分至靠近一个底部的所述电极的所述圆柱形壁表面中的狭口。
6.根据权利要求1所述的半导体器件的载体衬底的电极结构，其特征在于，所述半导体器件的封装是球栅阵形。
7.根据权利要求1所述的半导体器件的载体衬底的电极结构，其特征在于，所述半导体器件的封装是芯片尺寸封装型。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1606155B (zh) * 2003-10-09 2010-10-27 先进封装技术私人有限公司 具有柱形结构的管芯及其制造方法
US8027553B2 (en) 2006-08-24 2011-09-27 Hitachi Cable, Ltd. Connected body and optical transceiver module

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6400574B1 (en) * 2000-05-11 2002-06-04 Micron Technology, Inc. Molded ball grid array
JP2003133366A (ja) * 2001-10-25 2003-05-09 Texas Instr Japan Ltd 半導体装置及びその製造方法
US7343535B2 (en) * 2002-02-06 2008-03-11 Avago Technologies General Ip Dte Ltd Embedded testing capability for integrated serializer/deserializers
US7520679B2 (en) * 2003-09-19 2009-04-21 Avago Technologies Fiber Ip (Singapore) Pte. Ltd. Optical device package with turning mirror and alignment post
US20050063431A1 (en) * 2003-09-19 2005-03-24 Gallup Kendra J. Integrated optics and electronics
US20050063648A1 (en) * 2003-09-19 2005-03-24 Wilson Robert Edward Alignment post for optical subassemblies made with cylindrical rods, tubes, spheres, or similar features
US6982437B2 (en) 2003-09-19 2006-01-03 Agilent Technologies, Inc. Surface emitting laser package having integrated optical element and alignment post
US6953990B2 (en) * 2003-09-19 2005-10-11 Agilent Technologies, Inc. Wafer-level packaging of optoelectronic devices
WO2005084378A2 (en) * 2004-03-05 2005-09-15 Board Of Regents Of University Of Texas System Material and device properties modification by electrochemical charge injection in the absence of contacting electrolyte for either local spatial or final states
US20050213995A1 (en) * 2004-03-26 2005-09-29 Myunghee Lee Low power and low jitter optical receiver for fiber optic communication link
JP4798222B2 (ja) * 2006-04-07 2011-10-19 株式会社村田製作所 電子部品の接合構造およびその製造方法
JP2011187484A (ja) * 2010-03-04 2011-09-22 Denso Corp 電子部品の実装構造
US20140264808A1 (en) * 2013-03-15 2014-09-18 Andreas Wolter Chip arrangements, chip packages, and a method for manufacturing a chip arrangement
KR101704260B1 (ko) * 2015-09-14 2017-02-07 엘지전자 주식회사 반도체 모듈 및 그 제조방법

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0562980A (ja) 1991-08-29 1993-03-12 Hitachi Ltd 半導体装置およびその製造方法
JPH0697637A (ja) * 1992-09-14 1994-04-08 Fuji Electric Co Ltd プリント配線板
US5420377A (en) * 1992-12-02 1995-05-30 Motorola, Inc. Circuit assembly with vented solder pads
JP3350152B2 (ja) 1993-06-24 2002-11-25 三菱電機株式会社 半導体装置およびその製造方法
JPH0945805A (ja) * 1995-07-31 1997-02-14 Fujitsu Ltd 配線基板、半導体装置及び半導体装置を配線基板から取り外す方法並びに半導体装置の製造方法
JP3150582B2 (ja) 1995-08-24 2001-03-26 富士機工電子株式会社 エアリア・グリッド・アレイ・パッケージ用基板およびその製造方法
KR100216839B1 (ko) * 1996-04-01 1999-09-01 김규현 Bga 반도체 패키지의 솔더 볼 랜드 메탈 구조
US6139336A (en) * 1996-11-14 2000-10-31 Berg Technology, Inc. High density connector having a ball type of contact surface
JPH10233413A (ja) * 1997-02-21 1998-09-02 Nec Kansai Ltd 半導体装置およびその製造方法並びに配線基板
JP3037222B2 (ja) * 1997-09-11 2000-04-24 九州日本電気株式会社 Ｂｇａ型半導体装置
US5962922A (en) * 1998-03-18 1999-10-05 Wang; Bily Cavity grid array integrated circuit package
US6324754B1 (en) * 1998-03-25 2001-12-04 Tessera, Inc. Method for fabricating microelectronic assemblies
JPH11317470A (ja) 1998-05-06 1999-11-16 Denso Corp バンプを有する電子部品
JP3128064B2 (ja) 1998-05-12 2001-01-29 秉龍 汪 集積回路パッケージ
JP3506211B2 (ja) * 1998-05-28 2004-03-15 シャープ株式会社 絶縁性配線基板及び樹脂封止型半導体装置
US6037667A (en) * 1998-08-24 2000-03-14 Micron Technology, Inc. Socket assembly for use with solder ball
SG78324A1 (en) * 1998-12-17 2001-02-20 Eriston Technologies Pte Ltd Bumpless flip chip assembly with strips-in-via and plating
JP3742732B2 (ja) * 1998-12-18 2006-02-08 シャープ株式会社 実装基板及び実装構造体
DE60023202T2 (de) * 1999-02-15 2006-07-20 Mitsubishi Gas Chemical Co., Inc. Leiterplatte für Plastikhalbleitergehäuse

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1606155B (zh) * 2003-10-09 2010-10-27 先进封装技术私人有限公司 具有柱形结构的管芯及其制造方法
US8027553B2 (en) 2006-08-24 2011-09-27 Hitachi Cable, Ltd. Connected body and optical transceiver module

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