CN1606155B - 具有柱形结构的管芯及其制造方法 - Google Patents

具有柱形结构的管芯及其制造方法 Download PDF

Info

Publication number
CN1606155B
CN1606155B CN2004100347583A CN200410034758A CN1606155B CN 1606155 B CN1606155 B CN 1606155B CN 2004100347583 A CN2004100347583 A CN 2004100347583A CN 200410034758 A CN200410034758 A CN 200410034758A CN 1606155 B CN1606155 B CN 1606155B
Authority
CN
China
Prior art keywords
tube core
column
metal level
constructions
different column
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
CN2004100347583A
Other languages
English (en)
Other versions
CN1606155A (zh
Inventor
金辉·谭
刘世奎
庄汉·沈
巴拉苏布科马尼恩·西瓦格纳姆
罗斯马丽·塔卡普洛特
延元·庞
马·L·南·托伊
林中·信
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanpack Solutions Pte Ltd
Original Assignee
Advanpack Solutions Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=34422426&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=CN1606155(B) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Advanpack Solutions Pte Ltd filed Critical Advanpack Solutions Pte Ltd
Publication of CN1606155A publication Critical patent/CN1606155A/zh
Application granted granted Critical
Publication of CN1606155B publication Critical patent/CN1606155B/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05023Disposition the whole internal layer protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05556Shape in side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05568Disposition the whole external layer protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0605Shape
    • H01L2224/06051Bonding areas having different shapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0612Layout
    • H01L2224/0615Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0612Layout
    • H01L2224/0616Random array, i.e. array with no symmetry
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13012Shape in top view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13012Shape in top view
    • H01L2224/13013Shape in top view being rectangular or square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13012Shape in top view
    • H01L2224/13014Shape in top view being circular or elliptic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/1308Plural core members being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/1308Plural core members being stacked
    • H01L2224/13082Two-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/1357Single coating layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13599Material
    • H01L2224/136Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13655Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13599Material
    • H01L2224/136Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13671Chromium [Cr] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1405Shape
    • H01L2224/14051Bump connectors having different shapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00013Fully indexed content
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01022Titanium [Ti]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01024Chromium [Cr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01061Promethium [Pm]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01327Intermediate phases, i.e. intermetallics compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/146Mixed devices
    • H01L2924/1461MEMS
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/157Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Micromachines (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明公开了一种包括衬底和在所述衬底上以某种图案形成的一个或多个柱形结构的管芯以及形成该管芯的方法。

Description

具有柱形结构的管芯及其制造方法
技术领域
本发明一般地涉及半导体芯片互连的制备,更具体地涉及凸起的制备。
背景技术
提高在功率器件(即大量耗能的器件,例如放大器)上的现有半导体器件的性能的市场需求正在增长。
当前的圆形或类似圆形(如六边形或八边形)的焊料凸起(solderbump)互连已经成为改善电学性能以将电流引导至芯片级以及改善下至PCB的散热能力的瓶颈。例如,Advanced Interconnect Technologies 2002年春季刊中的“Advanced Connections”特别介绍了一种柱形凸起(pillarbump)互连技术,其利用周边或阵列倒装芯片焊垫将集成电路(IC)连接至铜引线框。
Chew等的美国专利No.6,550,666B2公开了一种用于在引线框半导体封装上形成倒装芯片的方法。
Kondoh等的美国专利No.5,448,114公开了一种具有周边壁的半导体倒装芯片封装。
美国专利No.6,297,551B1公开了具有改进的EMI特性的集成电路封装。
Chance等的美国专利No.4,430,690公开了一种具有金属浸渍和焊料棒触点的低电感电容器。
发明内容
因此,本发明的目的是提供一种改进的凸起设计方案。其他目的将在下文介绍。
目前我们已经发现以下面的方式可以实现本发明的上述目的以及其他目的。具体地说,管芯(die)包括衬底和一个或多个以某种图案在该衬底上形成的柱形结构。本发明还包括通过提供衬底,并在该衬底上以某种图案形成一个或多个柱形结构而形成管芯的方法。
附图说明
结合附图,参照下面的描述,可以更清楚地理解本发明的特征和优点,其中相同的标号表示类似的或对应的元件、区域和部分,且其中:
图1-7示意性地示出了形成本发明的柱形结构的方法的优选实施例。
图8是在具有本发明的柱形结构的晶片上的管芯的俯视示意图。
图9A和9B分别是图8中虚线圈“9A”和“9B”内的部分。
图10A-10I是另外具有变化的柱形结构/凸起设计/形状的管芯的俯视示意图。
具体实施方式
初始结构
如图1所示,结构10包括至少一个嵌入的金属结构12和上覆介电层14。
结构10优选是硅衬底,并且应理解为可能包括半导体晶片或衬底、在该晶片内形成的有源器件和无源器件、在该晶片表面上形成的导电层和介电层(例如层间多氧化物(inter-poly oxide,IPO)、金属间电介质(IMD)等)。术语“半导体结构”意在包括在半导体晶片内形成的器件和覆于该晶片上的层。
嵌入的金属结构12可以电连接至在结构10内形成的一个或多个半导体器件,并且优选由铝(Al)、铜(Cu)或金(Au)组成,更优选由铝(Al)组成,这将在下文用于说明的目的。
上覆介电层14优选由氮化物、氮化硅(Si3N4)、氧化硅(SiO2)或聚酰亚胺构成,并且更优选由氮化硅构成,这将在下文用于说明的目的。
如需要,可以对图1的结构进行清洗。
金属层15的形成——图2
如图2所示,金属层15在SiN层14上形成。金属层15优选通过溅射形成。
金属层15被形成/覆盖在整个晶片表面上。金属层15优选包括下金属层16和上金属层18。下金属层16可以是金属阻挡层,并且优选是钛(Ti)或TiW,更优选是Ti。上金属层18优选是铜(Cu)。
掩模层20的形成——图3
如图3所示,掩模层20在金属层15上形成。掩模层20优选由光刻胶组成。
光刻胶层20的图案化——图4
如图4所示,光刻胶层20然后被图案化以形成图案化的光刻胶层20’,该光刻胶层20’具有暴露Cu层18的一部分24的开口22。开口22形成的形状根据柱形结构34的形状来选定。例如,如图所示,开口22是长方形,但是也可以是圆形、环状、棒状或齿状以及其他形状。
在开口22内镀覆金属层26——图5
如图5所示,柱形金属层26在开口22内的Cu层18的暴露部分24上形成,厚度优选约60-120μm,更优选约70-100μm。柱形金属层26优选通过镀覆来形成。柱形金属层26将具有为柱形结构34所选择的形状,例如这些图中所具体示出的长方形,或者圆形、环状、棒状、壁状或齿状或其他形状。
柱形金属层26是无铅的,优选由铜(Cu)构成。柱形金属层26可以涂覆氧化物或另一种诸如铬、镍等的材料。
可选的焊料层28被形成/镀覆在Cu柱形层26上。可选的焊料层28可以与图案化的光刻胶层20’的顶部表面大致等高,并且优选地可以超过约5μm。焊料层28优选由(1)共晶物,约60-70%锡和约30-40%铅(Pb);(2)共晶物,约63%锡和约37%铅(Pb);(3)无铅物,约99-100%锡和Sn3.5Ag;或者(4)无铅物,100%锡组成。并且更优选由(2)共晶物,约63%锡和约37%铅(Pb);或(4)无铅物,100%锡组成。
图案化的掩模层20’的移除——图6
如图6所示,余下的图案化的掩模/光刻胶层20’优选通过剥离从图5的结构中被移除,以暴露Cu柱形层26/焊料层28外侧的Cu层15的部分30。
Cu层15的暴露部分30的蚀刻——图7
如图7所示,Cu柱形层26/焊料层28外侧的Cu层15的暴露部分30优选通过蚀刻被移除,以暴露Cu柱形层26/焊料层28外侧的上覆SiN层14的部分32。
Cu柱形层26/焊料层28的回流(reflow)——图7
还是如图7所示,对晶片进行回流,以使可选的焊料/覆层28回流以形成本发明的柱形结构34。铜柱形层26在焊料覆层28或无铅焊料覆层28的回流温度下不会熔化。覆层28是将管芯/CSP与衬底/引线框/PCB连接的部分。
回流后柱形结构34的总高度优选约60-150μm,更优选约100μm。
柱形结构34的焊料28’封住了Cu柱形层26的顶部,而其侧壁是暴露的。
注意该凸起的高度在管芯内是可以变化的。
柱形结构34用来连接管芯和管芯,管芯和引线框以及/或者管芯和衬底。
管芯设计实例100——图8和9
图8示出了由管芯周边所围住的采用本发明的柱形结构34的设计的管芯设计实例100。如图8所示,管芯100可以包括形状可变化的柱形结构/凸起34。
管芯周边可以用在表面声波(SAW)器件,并提供RF屏蔽,用于降低噪声、载流量和密封屏蔽,并且可以用在RF器件、功率器件和MEM(微型电子机械)中,用于噪声隔离和载流量。
图9A和9B分别是图8中虚线圈“9A”和“9B”内的部分。图9A示出了柱形结构34实例的长、宽以及长方形柱形结构34的间隔。如图9A所示,本发明的柱形结构34可以大致为长方形,长度可以为789.0μm-1289.0μm;宽度42优选为约289.0μm;长度40’和40”分别优选为约789.0μm或1289.0μm;并且在纵向上中心对中心的间隔约500μm,端对端的间隔约211.0μm。如图9B所示,柱形结构34可以是直径约289.0μm的圆形,并且间隔约500μm。
图10A-10I示出了具有其他可允许柱形结构/凸起34的形状和设计的管芯100’。例如,如图10D所示,柱形结构/凸起34可以是圆形的,并且还可以是如管芯100’的中心所示的方形壁状结构34。
例如,本发明的柱形结构可以用在表面声波(SAW)器件和电源开关以及MEM中。
本发明的优点
本发明的一个或多个实施例的优点包括:
1)本发明的柱形结构可以传导更高的电流;
2)使用本发明的柱形结构,板级可靠性更高;
3)该柱形结构的C4(control collapse chip connect,控制塌陷芯片连接)特征保持了管芯和封装之间所需的远离;
4)本发明的柱形结构提供了改进的散热能力;并且
5)在给定的焊垫开口中更大的金属/铜面积提供了更好的可靠性。
虽然这里已经说明并描述了本发明的具体实施例,但并非意在限制本发明。

Claims (48)

1.一种管芯,包括:
衬底;和
在所述衬底上以某种图案形成的两种或更多种不同的柱形结构,所述两种或更多种不同的柱形结构中的至少一个包括下部柱形金属层部分和上部焊料材料部分,所述上部焊料材料部分处于所述下部柱形金属层部分的上方并仅与所述下部柱形金属层部分的上表面牢固接触,
其中,在所述衬底和所述至少一个柱形结构之间设置有金属层,所述金属层包括下金属阻挡层和上金属层,
其中,所述下部柱形金属层部分在用于形成两种或者更多种不同的柱形结构的回流过程中不熔融,
其中,所述两种或更多种不同的柱形结构中的至少一个具有长方形、环形、壁状或齿状形状。
2.如权利要求1所述的管芯,其中所述两种或更多种不同的柱形结构中的至少之一具有长789.0-1289.0μm,宽289.0μm的长方形形状。
3.如权利要求1所述的管芯,其中所述两种或更多种不同的柱形结构中的至少之一具有长789.0μm,宽289.0μm的长方形形状。
4.如权利要求1所述的管芯,其中所述两种或更多种不同的柱形结构中的至少之一具有长1289.0μm,宽289.0μm的长方形形状。
5.如权利要求1所述的管芯,其中所述两种或更多种不同的柱形结构中的至少之一具有长方形形状,并且所述两种或更多种不同的柱形结构在纵向上中心对中心间隔500μm,端对端间隔211.0μm。
6.如权利要求1所述的管芯,其中所述柱形结构图案包括一系列的行和列。
7.如权利要求1所述的管芯,其中所述柱形结构图案包括一系列的行和列;以所述一系列的行和列排列的所述柱形结构在所述列中纵向上中心对中心间隔500μm,端对端间隔211.0μm。
8.如权利要求1所述的管芯,其中所述两种或更多种不同的柱形结构中的至少之一包括至少一个壁状柱形结构。
9.如权利要求1所述的管芯,其中所述两种或更多种不同的柱形结构中的至少之一包括至少一个形成方形的壁状柱形结构。
10.如权利要求1所述的管芯,其中所述下部柱形金属层部分由铜构成。
11.如权利要求1所述的管芯,其中下部柱形金属层部分由涂覆有氧化物、铬或镍的铜构成。
12.如权利要求1所述的管芯,其中所述所述上部焊料材料部分由:
60-70%锡和30-40%铅、
63%锡和37%铅、
99%锡和Sn3.5Ag、或者
100%锡构成。
13.如权利要求1所述的管芯,其中所述上部焊料材料部分由:
63%锡和37%铅、或者
100%锡构成。
14.如权利要求1所述的管芯,其中所述柱形结构每一个的总高度60-150μm。
15.如权利要求1所述的管芯,其中所述柱形结构每一个的总高度100μm。
16.如权利要求1所述的管芯,其中所述管芯用在表面声波器件和微型电子机械器件中。
17.一种管芯,包括:
衬底;和
在所述衬底上以某种图案形成的两种或更多种不同的柱形结构,所述两种或更多种不同的柱形结构具有长方形、环形、壁状或齿状形状,所述两种或更多种不同的柱形结构中的至少一个包括下部柱形金属层部分和上部焊料材料部分,所述上部焊料材料部分处于所述下部柱形金属层部分的上方并仅与所述下部柱形金属层部分的上表面牢固接触,
其中,在所述衬底和所述至少一个柱形结构之间设置有金属层,所述金属层包括下金属阻挡层和上金属层,
其中,所述下部柱形金属层部分在用于形成两种或者更多种不同的柱形结构的回流过程中不熔融。
18.如权利要求17所述的管芯,其中所述两种或更多种不同的柱形结构中的至少之一具有长789.0-1289.0μm,宽289.0μm的长方形形状。
19.如权利要求17所述的管芯,其中所述两种或更多种不同的柱形结构中的至少之一具有长789.0μm,宽289.0μm的长方形形状。
20.如权利要求17所述的管芯,其中所述两种或更多种不同的柱形结构中的至少之一具有长1289.0μm,宽289.0μm的长方形形状。
21.如权利要求17所述的管芯,其中所述两种或更多种不同的柱形结构中的至少之一具有长方形形状,并且所述两种或更多种不同的柱形结构在纵向上中心对中心间隔500μm,端对端间隔211.0μm。
22.如权利要求17所述的管芯,其中所述柱形结构图案包括一系列的行和列。
23.如权利要求17所述的管芯,其中所述柱形结构图案包括一系列的行和列;以所述一系列的行和列排列的所述柱形结构在所述列中纵向上中心对中心间隔500μm,端对端间隔211.0μm。
24.如权利要求17所述的管芯,其中所述两种或更多种不同的柱形结构包括至少一个壁状柱形结构。
25.如权利要求17所述的管芯,其中所述两种或更多种不同的柱形结构包括至少一个形成方形的壁状柱形结构。
26.如权利要求17所述的管芯,其中下部柱形金属层部分由铜构成。
27.如权利要求17所述的管芯,其中所述下部柱形金属层部分由涂覆有氧化物、铬或镍的铜构成。
28.如权利要求17所述的管芯,其中所述上部焊料材料部分由:
60-70%锡和30-40%铅、
63%锡和37%铅、
99%锡和Sn3.5Ag、或者
100%锡构成。
29.如权利要求17所述的管芯,其中所述上部焊料材料部分由:
63%锡和37%铅、或者
100%锡构成。
30.如权利要求17所述的管芯,其中所述柱形结构每一个的总高度60-150μm。
31.如权利要求17所述的管芯,其中所述柱形结构每一个的总高度100μm。
32.如权利要求17所述的管芯,其中所述管芯用在表面声波器件和微型电子机械器件中。
33.一种形成管芯的方法,包括下述步骤:
提供衬底;以及
在所述衬底上以某种图案形成两种或更多种不同的柱形结构,所述两种或更多种不同的柱形结构中的至少一个包括下部柱形金属层部分和上部焊料材料部分,所述上部焊料材料部分处于所述下部柱形金属层部分的上方并仅与所述下部柱形金属层部分的上表面牢固接触,
其中,在所述衬底和所述至少一个柱形结构之间设置有金属层,所述金属层包括下金属阻挡层和上金属层,
其中,所述下部柱形金属层部分在用于形成两种或者更多种不同的柱形结构的回流过程中不熔融,其中,所述两种或更多种不同的柱形结构中的至少一个具有长方形、环形、壁状或齿状的形状。
34.如权利要求33所述的方法,其中所述两种或更多种不同的柱形结构中的至少之一具有长789.0-1289.0μm,宽289.0μm的长方形形状。
35.如权利要求33所述的方法,其中所述两种或更多种不同的柱形结构中的至少之一具有长789.0μm,宽289.0μm的长方形形状。
36.如权利要求33所述的方法,其中所述两种或更多种不同的柱形结构中的至少之一具有长1289.0μm,宽289.0μm的长方形形状。
37.如权利要求33所述的方法,其中所述两种或更多种不同的柱形结构中的至少之一具有长方形形状,并且所述两种或更多种不同的柱形结构在纵向上中心对中心间隔500μm,端对端间隔211.0μm。
38.如权利要求33所述的方法,其中所述柱形结构图案包括一系列的行和列。
39.如权利要求33所述的方法,其中所述柱形结构图案包括一系列的行和列;以所述一系列的行和列排列的所述柱形结构在所述列中纵向上中心对中心间隔500μm,端对端间隔211.0μm。
40.如权利要求33所述的方法,其中所述两种或更多种不同的柱形结构中的至少之一包括至少一个壁状柱形结构。
41.如权利要求33所述的方法,其中所述两种或更多种不同的柱形结构中的至少之一包括至少一个形成方形的壁状柱形结构。
42.如权利要求33所述的方法,其中所述下部柱形金属层部分由铜构成。
43.如权利要求33所述的方法,其中所述下部柱形金属层部分由涂覆有氧化物、铬或镍的铜构成。
44.如权利要求33所述的方法,其中所述上部焊料材料部分由:
60-70%锡和30-40%铅、
63%锡和37%铅、
99%锡和Sn3.5Ag、或者
100%锡构成。
45.如权利要求33所述的方法,其中所述上部焊料部分由:
63%锡和37%铅、或者
100%锡构成。
46.如权利要求33所述的方法,其中所述柱形结构每一个的总高度60-150μm。
47.如权利要求33所述的方法,其中所述柱形结构每一个的总高度100μm。
48.如权利要求33所述的方法,其中所形成的管芯用在表面声波器件和微型电子机械器件中。
CN2004100347583A 2003-10-09 2004-05-12 具有柱形结构的管芯及其制造方法 Ceased CN1606155B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/682,054 US7462942B2 (en) 2003-10-09 2003-10-09 Die pillar structures and a method of their formation
US10/682,054 2003-10-09

Publications (2)

Publication Number Publication Date
CN1606155A CN1606155A (zh) 2005-04-13
CN1606155B true CN1606155B (zh) 2010-10-27

Family

ID=34422426

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2004100347583A Ceased CN1606155B (zh) 2003-10-09 2004-05-12 具有柱形结构的管芯及其制造方法

Country Status (5)

Country Link
US (1) US7462942B2 (zh)
EP (1) EP1709684A1 (zh)
CN (1) CN1606155B (zh)
TW (1) TWI323919B (zh)
WO (1) WO2005034237A1 (zh)

Families Citing this family (83)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6642136B1 (en) 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
US8021976B2 (en) 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
US6815324B2 (en) 2001-02-15 2004-11-09 Megic Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
US8158508B2 (en) * 2001-03-05 2012-04-17 Megica Corporation Structure and manufacturing method of a chip scale package
US6818545B2 (en) 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
TWI313507B (en) 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
US7099293B2 (en) 2002-05-01 2006-08-29 Stmicroelectronics, Inc. Buffer-less de-skewing for symbol combination in a CDMA demodulator
TWI245402B (en) 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
US8129841B2 (en) 2006-12-14 2012-03-06 Stats Chippac, Ltd. Solder joint flip chip interconnection
WO2005048311A2 (en) 2003-11-10 2005-05-26 Chippac, Inc. Bump-on-lead flip chip interconnection
US9029196B2 (en) 2003-11-10 2015-05-12 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US8026128B2 (en) 2004-11-10 2011-09-27 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US8574959B2 (en) 2003-11-10 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming bump-on-lead interconnection
USRE47600E1 (en) 2003-11-10 2019-09-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US20060216860A1 (en) 2005-03-25 2006-09-28 Stats Chippac, Ltd. Flip chip interconnection having narrow interconnection sites on the substrate
US8216930B2 (en) 2006-12-14 2012-07-10 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
US8350384B2 (en) 2009-11-24 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US7394161B2 (en) 2003-12-08 2008-07-01 Megica Corporation Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto
US8067837B2 (en) 2004-09-20 2011-11-29 Megica Corporation Metallization structure over passivation layer for IC chip
US8294279B2 (en) 2005-01-25 2012-10-23 Megica Corporation Chip package with dam bar restricting flow of underfill
US8841779B2 (en) 2005-03-25 2014-09-23 Stats Chippac, Ltd. Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate
US7494924B2 (en) * 2006-03-06 2009-02-24 Freescale Semiconductor, Inc. Method for forming reinforced interconnects on a substrate
US7713782B2 (en) * 2006-09-22 2010-05-11 Stats Chippac, Inc. Fusible I/O interconnection systems and methods for flip-chip packaging involving substrate-mounted stud-bumps
US9847309B2 (en) 2006-09-22 2017-12-19 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming vertical interconnect structure between semiconductor die and substrate
TWI378540B (en) 2006-10-14 2012-12-01 Advanpack Solutions Pte Ltd Chip and manufacturing method thereof
DE102009012643A1 (de) 2008-03-10 2009-10-01 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verbindungsstruktur und Verfahren zur Herstellung einer Verbindungsstruktur
US9524945B2 (en) 2010-05-18 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with L-shaped non-metal sidewall protection structure
US8536458B1 (en) 2009-03-30 2013-09-17 Amkor Technology, Inc. Fine pitch copper pillar package and method
US8841766B2 (en) 2009-07-30 2014-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US8377816B2 (en) 2009-07-30 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming electrical connections
US8324738B2 (en) 2009-09-01 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned protection layer for copper post structure
US8659155B2 (en) * 2009-11-05 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps
US8610270B2 (en) * 2010-02-09 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and semiconductor assembly with lead-free solder
TWI584434B (zh) * 2010-04-20 2017-05-21 瑞鼎科技股份有限公司 晶粒結構及晶粒接合方法
US8441124B2 (en) 2010-04-29 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US9018758B2 (en) 2010-06-02 2015-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall spacer and metal top cap
US8390119B2 (en) 2010-08-06 2013-03-05 Mediatek Inc. Flip chip package utilizing trace bump trace interconnection
US8546254B2 (en) 2010-08-19 2013-10-01 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps using patterned anodes
TWI451546B (zh) 2010-10-29 2014-09-01 Advanced Semiconductor Eng 堆疊式封裝結構、其封裝結構及封裝結構之製造方法
US8492893B1 (en) 2011-03-16 2013-07-23 Amkor Technology, Inc. Semiconductor device capable of preventing dielectric layer from cracking
US8669137B2 (en) * 2011-04-01 2014-03-11 International Business Machines Corporation Copper post solder bumps on substrate
US10096540B2 (en) * 2011-05-13 2018-10-09 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming dummy pillars between semiconductor die and substrate for maintaining standoff distance
US20120313234A1 (en) * 2011-06-10 2012-12-13 Geng-Shin Shen Qfn package and manufacturing process thereof
US8598691B2 (en) 2011-09-09 2013-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacturing and packaging thereof
US9723717B2 (en) * 2011-12-19 2017-08-01 Advanpack Solutions Pte Ltd. Substrate structure, semiconductor package device, and manufacturing method of semiconductor package
US8796841B2 (en) 2012-04-09 2014-08-05 Freescale Semiconductor, Inc. Semiconductor device with embedded heat spreading
US8581390B2 (en) 2012-04-09 2013-11-12 Freescale Semiconductor, Inc. Semiconductor device with heat dissipation
US8884443B2 (en) 2012-07-05 2014-11-11 Advanced Semiconductor Engineering, Inc. Substrate for semiconductor package and process for manufacturing
TWI562295B (en) 2012-07-31 2016-12-11 Mediatek Inc Semiconductor package and method for fabricating base for semiconductor package
US9177899B2 (en) 2012-07-31 2015-11-03 Mediatek Inc. Semiconductor package and method for fabricating base for semiconductor package
US10991669B2 (en) 2012-07-31 2021-04-27 Mediatek Inc. Semiconductor package using flip-chip technology
CN104704682B (zh) 2012-08-22 2017-03-22 安费诺有限公司 高频电连接器
EP2711977B1 (en) 2012-09-19 2018-06-13 ATOTECH Deutschland GmbH Manufacture of coated copper pillars
US8866311B2 (en) 2012-09-21 2014-10-21 Advanced Semiconductor Engineering, Inc. Semiconductor package substrates having pillars and related methods
US8686568B2 (en) 2012-09-27 2014-04-01 Advanced Semiconductor Engineering, Inc. Semiconductor package substrates having layered circuit segments, and related methods
JP6143104B2 (ja) 2012-12-05 2017-06-07 株式会社村田製作所 バンプ付き電子部品及びバンプ付き電子部品の製造方法
JP6066324B2 (ja) 2013-08-23 2017-01-25 株式会社村田製作所 電子装置
US9159682B2 (en) 2013-09-08 2015-10-13 Freescale Semiconductor, Inc. Copper pillar bump and flip chip package using same
CN111641083A (zh) 2014-11-12 2020-09-08 安费诺有限公司 在配合区域中具有阻抗控制的非常高速、高密度电互连系统
US9508671B2 (en) 2015-04-20 2016-11-29 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package
US10006136B2 (en) 2015-08-06 2018-06-26 Dow Global Technologies Llc Method of electroplating photoresist defined features from copper electroplating baths containing reaction products of imidazole compounds, bisepoxides and halobenzyl compounds
TWI608132B (zh) 2015-08-06 2017-12-11 羅門哈斯電子材料有限公司 自含有吡啶基烷基胺及雙環氧化物之反應產物的銅電鍍覆浴液電鍍覆光阻劑限定之特徵的方法
US9932684B2 (en) 2015-08-06 2018-04-03 Rohm And Haas Electronic Materials Llc Method of electroplating photoresist defined features from copper electroplating baths containing reaction products of alpha amino acids and bisepoxides
US10100421B2 (en) 2015-08-06 2018-10-16 Dow Global Technologies Llc Method of electroplating photoresist defined features from copper electroplating baths containing reaction products of imidazole and bisepoxide compounds
US10312638B2 (en) 2016-05-31 2019-06-04 Amphenol Corporation High performance cable termination
CN110088985B (zh) 2016-10-19 2022-07-05 安费诺有限公司 用于超高速高密度电互连的柔性屏蔽件
TWI681524B (zh) * 2017-01-27 2020-01-01 日商村田製作所股份有限公司 半導體晶片
US10510722B2 (en) * 2017-06-20 2019-12-17 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and method for manufacturing the same
US11070006B2 (en) 2017-08-03 2021-07-20 Amphenol Corporation Connector for low loss interconnection system
US10665973B2 (en) 2018-03-22 2020-05-26 Amphenol Corporation High density electrical connector
CN112514175B (zh) 2018-04-02 2022-09-09 安达概念股份有限公司 受控阻抗顺应性线缆终端头
US10931062B2 (en) 2018-11-21 2021-02-23 Amphenol Corporation High-frequency electrical connector
CN117175250A (zh) 2019-01-25 2023-12-05 富加宜(美国)有限责任公司 被配置用于线缆连接到中板的i/o连接器
CN117175239A (zh) 2019-01-25 2023-12-05 富加宜(美国)有限责任公司 插座连接器和电连接器
CN113728521A (zh) 2019-02-22 2021-11-30 安费诺有限公司 高性能线缆连接器组件
US11600590B2 (en) 2019-03-22 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package
US11735852B2 (en) 2019-09-19 2023-08-22 Amphenol Corporation High speed electronic system with midboard cable connector
US11171006B2 (en) 2019-12-04 2021-11-09 International Business Machines Corporation Simultaneous plating of varying size features on semiconductor substrate
US11239167B2 (en) 2019-12-04 2022-02-01 International Business Machines Corporation Cu—Cu bonding for interconnects on bridge chip attached to chips and packaging substrate
WO2021154718A1 (en) 2020-01-27 2021-08-05 Fci Usa Llc High speed, high density direct mate orthogonal connector
TW202135385A (zh) 2020-01-27 2021-09-16 美商Fci美國有限責任公司 高速連接器
CN113258325A (zh) 2020-01-28 2021-08-13 富加宜(美国)有限责任公司 高频中板连接器
USD1002553S1 (en) 2021-11-03 2023-10-24 Amphenol Corporation Gasket for connector

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5448114A (en) * 1992-07-15 1995-09-05 Kabushiki Kaisha Toshiba Semiconductor flipchip packaging having a perimeter wall
CN1180927A (zh) * 1996-10-17 1998-05-06 国际商业机器公司 高性能低成本的多芯片组件封装件
US6297581B1 (en) * 1997-09-11 2001-10-02 Murata Manufacturing Co., Ltd. Piezoelectric element and electronic component including same
CN1326226A (zh) * 2000-05-12 2001-12-12 日本电气株式会社 半导体器件的载体衬底的电极结构
CN1338779A (zh) * 2000-08-11 2002-03-06 Iep技术株式会社 半导体器件
CN1355935A (zh) * 1999-06-10 2002-06-26 东洋钢钣株式会社 用于形成半导体装置用内插器的复层板、半导体装置用内插器以及它们的制造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4430690A (en) 1982-10-07 1984-02-07 International Business Machines Corporation Low inductance MLC capacitor with metal impregnation and solder bar contact
US5251806A (en) * 1990-06-19 1993-10-12 International Business Machines Corporation Method of forming dual height solder interconnections
US6642136B1 (en) * 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
JP2000243765A (ja) 1999-02-19 2000-09-08 Shinko Electric Ind Co Ltd 半導体チップの実装構造及び半導体チップの実装方法
JP3570271B2 (ja) 1999-02-22 2004-09-29 オムロン株式会社 半導体センサ及びその製造方法
US6578754B1 (en) * 2000-04-27 2003-06-17 Advanpack Solutions Pte. Ltd. Pillar connections for semiconductor chips and method of manufacture
US7057292B1 (en) * 2000-05-19 2006-06-06 Flipchip International, Llc Solder bar for high power flip chips
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US20030006062A1 (en) * 2001-07-06 2003-01-09 Stone William M. Interconnect system and method of fabrication
US6550666B2 (en) 2001-08-21 2003-04-22 Advanpack Solutions Pte Ltd Method for forming a flip chip on leadframe semiconductor package
TWI245402B (en) * 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5448114A (en) * 1992-07-15 1995-09-05 Kabushiki Kaisha Toshiba Semiconductor flipchip packaging having a perimeter wall
CN1180927A (zh) * 1996-10-17 1998-05-06 国际商业机器公司 高性能低成本的多芯片组件封装件
US6297581B1 (en) * 1997-09-11 2001-10-02 Murata Manufacturing Co., Ltd. Piezoelectric element and electronic component including same
CN1355935A (zh) * 1999-06-10 2002-06-26 东洋钢钣株式会社 用于形成半导体装置用内插器的复层板、半导体装置用内插器以及它们的制造方法
CN1326226A (zh) * 2000-05-12 2001-12-12 日本电气株式会社 半导体器件的载体衬底的电极结构
CN1338779A (zh) * 2000-08-11 2002-03-06 Iep技术株式会社 半导体器件

Also Published As

Publication number Publication date
EP1709684A1 (en) 2006-10-11
TW200527562A (en) 2005-08-16
TWI323919B (en) 2010-04-21
CN1606155A (zh) 2005-04-13
US7462942B2 (en) 2008-12-09
US20050077624A1 (en) 2005-04-14
WO2005034237A1 (en) 2005-04-14

Similar Documents

Publication Publication Date Title
CN1606155B (zh) 具有柱形结构的管芯及其制造方法
US8461679B2 (en) Method for fabricating circuit component
KR101380712B1 (ko) 퓨즈형 i/o 상호연결 시스템 및 기판 장착 스터드범프를포함하는 플립칩 패키징 방법
CN100474539C (zh) 晶片级涂覆的铜柱状凸起
US6762117B2 (en) Method of fabricating metal redistribution layer having solderable pads and wire bondable pads
US7056818B2 (en) Semiconductor device with under bump metallurgy and method for fabricating the same
JP5629580B2 (ja) 二重ポスト付きフリップチップ相互接続
US9269683B2 (en) Integrated circuit chip with pyramid or cone-shaped conductive pads for flexible C4 connections and a method of forming the integrated circuit chip
US7691681B2 (en) Chip scale package having flip chip interconnect on die paddle
US7358174B2 (en) Methods of forming solder bumps on exposed metal pads
JP2017022408A (ja) 2重エッチングフリップチップコネクタ又は多重エッチングフリップチップコネクタを有する超小型電子パッケージ及び対応する製造方法
TWI280641B (en) Chip structure
JP2008517475A (ja) 電気接点を有する基板及びその製造方法
KR101037832B1 (ko) 반도체 디바이스 및 그 제조 방법
US20170084556A1 (en) Semiconductor device
US6956293B2 (en) Semiconductor device
US7088004B2 (en) Flip-chip device having conductive connectors
TWI380425B (en) Fine pitch bump structure and its manufacturing process
CN117393510A (zh) 封装结构及其形成方法
JP2005159050A (ja) 半導体素子及びその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
IW01 Full invalidation of patent right
IW01 Full invalidation of patent right

Decision date of declaring invalidation: 20200317

Decision number of declaring invalidation: 43615

Granted publication date: 20101027