CN1180927A - 高性能低成本的多芯片组件封装件 - Google Patents

高性能低成本的多芯片组件封装件 Download PDF

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CN1180927A
CN1180927A CN97118489A CN97118489A CN1180927A CN 1180927 A CN1180927 A CN 1180927A CN 97118489 A CN97118489 A CN 97118489A CN 97118489 A CN97118489 A CN 97118489A CN 1180927 A CN1180927 A CN 1180927A
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丹尼斯·F·克劳彻尔
格伦·G·戴维斯
比德·M·伊莱纽斯
约塞夫·J·里索夫斯基
约塞夫·M·萨利文
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International Business Machines Corp
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Abstract

一种高性能、低成本的多芯片组件封装件,它用热沉作为衬底,用薄膜技术或多层布线技术将组件表面上的各芯片互连起来并用焊柱网格阵列或焊球网格阵列互连到下一层封装(即刷电路板)。焊柱或焊球在电路板和组件之间产生一个空间,使各芯片处于此空间中,并提供所需的互连密度。

Description

高性能低成本的多芯片组件封装件
本发明一般涉及到半导体芯片封装，更确切地说是涉及到多芯片封装件以及用薄膜或内部衬底引线对封装中各芯片进行互连。
在半导体封装业中，对高性能、低成本、小尺寸多芯片组件封装技术存在着需求。诸如有机芯片载体、陶瓷芯片载体或硅衬底上的硅芯片之类的现有解决方法都存在与小尺寸相关的限制(如在四方扁平封装中，对下一级的互连围绕着周边并占据很大的空间)、有限的散热能力(使大功率芯片冷却的能力)，或带有复杂的高成本的装配工序(使用独立的基底或加强板、盖子、罩子和散热片)，或三种情况都存在。
图1示出了一种常规的组件封装件，其中示出了多芯片“芯片向上(chip up)”封装件的剖面(只一个芯片)。示出了带有内部或表面引线(集成引线)的一个有机或陶瓷衬底1和一个硅芯片2。盖子3覆盖着衬底1和芯片2。导热粘合剂4将铸铝或挤压铝构成的散热片5固定在盖子3上。用芯片2和盖子3之间的导热油脂7可使芯片2到盖子3的热传送变得容易。在衬底1下面有互连管脚6。也可用柱或球(未示出)来代替管脚。这种封装件的装配工序相当复杂，用到三种部件：衬底/芯片载体、盖子和散热片。
图2示出了一个本技术领域也熟知的空腔向下的组件封装件。向下的腔体13制作在衬底11的一个窗口中。热导率良好的棒块14铸入衬底且跨越腔13的宽度。芯片15固定在棒块14的与导热粘合剂12相反的一侧上。盖子16跨越腔的长度且在腔的侧面上固定于衬底11。如在图1所述的“芯片向上”封装件中那样，互连管脚17固定于衬底的底部。用散热片粘合剂12将铸铝或挤压铝组成的散热片18固定于衬底11的反侧。这种封装件的装配工序也相当复杂，也用到多个部件：衬底/芯片载体、盖子、导热棒块和散热片。
图3A、3B和3C分别示出了本技术领域熟知的硅基外延硅多芯片组件的俯视图、正面图和侧面图。芯片21被引线连接或倒装片连接于硅衬底22。硅衬底在其顶表面23上有薄膜布线电路，各个芯片连接于其上，使各芯片得到互连。待要连接到装配件下一层的电路被引到硅衬底的周边，然后用引线连接24跳至带有四方扁平封装26那样的周边表面安装接触(如图3C所示)或管脚27(如图3B所示)的加强板/载体基底25。然后可用盖子以及有要求时用散热片29覆盖整体封装件。还可用导热油脂30来增强导热。
这种封装件不仅装配工序复杂，用到多个部件，而且在装配件的下一层占据大量空间。本发明的目的是提供一种能保持或改善现有技术的热学与电性能同时又具有较小尺寸和较低成本的组件封装件设计。
在同时用作衬底的散热片上用布线连接技术已开发了单芯片组件。例如见IBM Technical Disclosure Bulletin，Vo.131，No.11，1989年4月。由于它未说明如何实现芯片间布线，故此技术不能用于多芯片组件。使用管脚在多芯片生产中不能为密集的互连结构提供方便。此技术也不利用倒装片和薄膜互连技术。
因此，需要一种既能增加尽量少的成本就能改进现有技术散热片效率又能适应各种芯片互连工艺的多芯片组件设计。
因此，本发明的一个目的是提供一种封装工艺，用它可获得低成本、高性能(热学与电学)的高密度多芯片封装件。
本发明的另一目的是提供一种相对于现有技术来说制造简单(步骤更少，部件更少)且尺寸小的封装工艺。
根据本发明，提供了将常规散热片处理成芯片载体封装件的能力，并为下一层装配提供了普通的表面可安装组件，而对现有工业标准实践不带有成本、尺寸或性能影响。基底衬底是一个铸造或浇铸的氮化铝、碳化硅或可用作散热片与衬底的其它材料的散热片/加固板。对下一层封装的互连是通过焊球或焊柱来实现。芯片互连是通过引线连接或通过焊球或柱互连或对全凸起引线/接头连接芯片的热压焊接工序的倒装片芯片，使倒装芯片和引线/接头芯片可处于同一个衬底而无需高成本的引线连接/接头芯片的重新分配和倒装芯片隆起。金凸起物方便地被热压连接到衬底或与焊料连结。组件上各芯片之间的互连以及到输入/输出连接的互连(焊球或柱)是通过位于散热片/衬底顶面上的薄膜布线或通过层叠在散热片/衬底顶层中的多层陶瓷布线。组件的电路/芯片一侧用环氧树脂或相似材料保护。在这种结构中，部件的数目和这些部件的装配被大大简化了。
一个变通方法是使硅、金刚石、铝或其它恰当衬底材料上的薄膜的基底衬底连接于具有相匹配的热膨胀系数的散热片/加强板上。其互连与基底衬底是散热片/加强板的情况是相同的。在这种结构中，不仅部件较少和装配工艺更简单，而且得到的组件较小。
参照附图，从本发明最佳实施例的下列详细描述中，可更好地理解上述的和其它的目的、情况和优点。在这些附图中：
图1是现有技术中所知的芯片向上衬底的剖面图；
图2是现有技术中所知的腔向下衬底的剖面图；
图3A、3B和3C分别是现有技术中所知的硅上硅多芯片组件的俯视图、正面图和侧面图；
图4是本发明的结构的剖面图；
图5是本发明的结构的仰视图。
再参照附图，具体地说是图4，其中示出了本发明的结构的侧面剖面图。由铸铝或挤压铝或其它恰当材料组成的散热片41也起衬底的作用。互连引线位于散热片/衬底41的底表面42上。用倒装片、焊球或金凸互连或管心连接/引线连接将多芯片43直接安装在散热片/衬底41上。焊接互连44阵列(焊柱、焊球或金凸)围绕着芯片43固定于散热片/衬底41的同一侧，以便在散热片/衬底41和下一层封装(印刷电路板，未示出)之间产生一个空间，并用作对下一层封装的互连。
图5示出了图4中多芯片结构的仰视图。此图更清楚地示出了固定于散热片/衬底的各种不同尺寸的芯片43。当需要加强连接和保护芯片时，可使用底层填料或塑料。
在常规技术和本发明中，都是用下列工业标准选项将各芯片固定且电互连于下一层封装。
引线连接
芯片背面通过使用管心连接粘合剂或冶金(例如焊料)接合而被连接于衬底。然后在芯片上的焊点与衬底上的焊点之间连接细金线或铝线，从而形成电互连。衬底上的焊点通过电路连接到其它芯片。组件上的引线可以是诸如印刷电路板或多层陶瓷衬底中的表面和/或内部布线，或者是淀积成多层而层间带有隔离的薄膜，相似于芯片上的互连电路，或是直接在衬底上或转移到衬底作为一种“移画印花”。到下一层封装的互连可以是从封装件各边延伸出来的表面安装接头或管脚，或在最佳实施例中那种在封装件底面上成阵列格式的焊接或焊柱。
倒装片
倒装片通常在芯片的电路侧或芯片电路侧周边附近的图形中有一个小焊点阵列。互连“球”被固定于这些焊点。这些球可由焊料、金或其它材料制成。衬底有一组相匹配的焊点，芯片可置于其上，然后利用焊接、热压或粘合剂将芯片固定于其上。芯片要固定于其上的衬底上的焊点以相似于上述的引线连接工序被互连和连接于下一层封装。
用先进的硅基外延硅(或诸如铝或金刚石之类的其它衬底材料)多芯片组件封装件，各芯片被管心连接/引线连接或倒装片固定到衬底上，在芯片之间互连并通过上述薄膜布线互连到下一层互连。由于硅、金刚石、氧化铝或其它衬底的机械强度不高，故通常将它们连接到提供机械增强和通过边缘接头或管脚到下一封装件的互连的陶瓷载体或插入件。为了将带有芯片的衬底电互连到载体，在衬底上焊点和载体上焊点之间进行周边引线连接。然后通常用盖子覆盖衬底/载体组装件，若有需要则再覆盖一个加于盖子的散热片(见图4)。
此公开的封装件不需要操作衬底到载体周边引线连接，因为焊球或焊柱在芯片周围直接固定衬底已提供了此功能。由于可通过直接在衬底上的环氧树脂或塑料包封而保护芯片(由于芯片将在衬底与下一层装备印刷电路板之间且不面对遭受触摸损伤，故这是可能的)，而且所公开的加强板/载体也是散热片，从而也免去了盖子和散热片装配操作。
在所有的情况下，由于各芯片将安装在与下一层互连同侧的衬底/芯片载体上，故它们将位于芯片载体和印刷电路板之间。若要求增强热学性能，则可在芯片背面(如在倒装片工艺中那样)和印刷电路板之间提供一个经由金属“弹簧”或导热弹性体或其它已知的导热增强技术的热通路。
本发明的独特之处是结合了用于芯片至芯片的薄膜布线以及用焊柱或焊球对下一层装备互连的输入/输出互连，从而可使用标准散热片作为一个单一的封装元件。作为变通，本发明允许使用其它散热片材料，包括但不局限于铸造的氮化铝、分层铸造多层陶瓷衬底、铸造或挤压散热片或陶瓷、铝、或其它恰当材料、硅、金刚石或层叠到恰当散热片材料的其它衬底材料。
此结合提供了一种独特的、低成本、小尺寸、高性能的多芯片组件封装件，在电子封装工业中有大量需求的潜力。
虽然用最佳实施例已描述了本发明，但本技术领域的熟练人员公认本发明也可在所附权利要求的构思与范围之内的作修改后加以实施。

Claims (11)

1.一种高性能的多芯片组件封装件，它包含：
一个组合热沉与衬底，上述热沉衬底组合包括集成布线；
一个连接于上述热沉衬底组合以连接到下一层封装件的互连阵列；以及
连接于上述热沉衬底组合的芯片互连。
2.权利要求1所述的高性能多芯片组件封装件，其特征是上述集成布线包含上述热沉衬底组合上的表面布线，上述表面布线将上述互连阵列与上述芯片互连互连起来。
3.权利要求2所述的高性能多芯片组件封装件，其特征是上述芯片互连用倒装片连接来连接。
4.权利要求2所述的高性能多芯片组件封装件，其特征是上述芯片互连被引线连接。
5.权利要求2所述的高性能多芯片组件封装件，其特征是上述芯片互连选自倒装片和引线连接。
6.权利要求1所述的高性能多芯片组件封装件，其特征是上述集成布线包含上述热沉衬底组合中的埋置布线，上述埋置布线将上述互连阵列与上述芯片互连互连起来。
7.权利要求6所述的高性能多芯片组件封装件，其特征是上述芯片互连用倒装片连接来连接。
8.权利要求6所述的高性能多芯片组件封装件，其特征是上述芯片互连用引线连接。
9.权利要求6所述的高性能多芯片组件封装件，其特征是上述芯片互连选自倒装片及引线连接。
10.权利要求1所述的高性能多芯片组件封装件，其特征是上述热沉衬底组合包含一个粘结于衬底的热沉，上述集成布线是上述衬底的一部分。
11.权利要求1所述的高性能多芯片组件封装件，其特征是还包含一个用来连接于下一层封装的互连阵列，此阵列为在其中接纳芯片提供空间。
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