CN1316579C - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN1316579C
CN1316579C CNB200410059869XA CN200410059869A CN1316579C CN 1316579 C CN1316579 C CN 1316579C CN B200410059869X A CNB200410059869X A CN B200410059869XA CN 200410059869 A CN200410059869 A CN 200410059869A CN 1316579 C CN1316579 C CN 1316579C
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semiconductor device
diaphragm
wiring pattern
adhesive sheet
area
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CN1577782A (zh
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谷口润
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Seiko Epson Corp
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Abstract

本发明提供了一种半导体装置,包括:具有电极的半导体元件;形成配线的基板;形成为在装载了半导体元件的第一区域以外的第二区域中覆盖配线图案的保护膜;以及粘接半导体元件和基板的粘接片。保护膜具有形成为向装载了所述半导体元件的第一区域变薄的端部。粘接片形成为至少从基板的第一区域达到保护膜的端部上。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置及其制造方法。
背景技术
随着近年来电子设备的小型化,要求适应于高密度安装的半导体装置的封装(package)。由此,开发出如BGA(Ball Grid Array)和CSP(ChipScale/Size Package)这样的表面安装型封装。在表面安装型封装中,有时使用形成了与半导体元件连接的配线图案的基板。
在现有的表面安装型封装中,已知在基板的配线图案上用各向异性导电膜(ACF(Anisotropic Conductive Film))、或NCF(Non Conductive Film)等粘接片固定半导体元件的半导体装置(例如,参照特开2001-21333号公报)。
在现有的半导体装置中,当用粘接片覆盖基板的配线图案时,会有在基板上的保护膜和粘接片之间潜入空气而形成气泡的可能性。并且,当为使粘接片硬化或回流(reflow)而加热时,由于气泡的膨胀而导致粘接片很容易剥离,所以很难防止移动(migration)。
发明内容
本发明的目的在于,提供一种既是用粘接片覆盖保护膜的结构,而可靠性又高的半导体装置及半导体装置的制造方法。
(1)本发明的半导体装置,其中包括:具有电极的半导体元件;形成了配线图案的基板;形成为在装载所述半导体元件的第一区域以外的第二区域中覆盖所述配线图案的保护膜;和粘接所述半导体元件和所述基板的粘接片,所述电极与所述配线图案电接触,所述保护膜具有形成为向装载了所述半导体元件的第一区域变薄的端部,所述粘接片形成为至少从所述基板的第一区域达到所述保护膜的所述端部。根据本发明,当将粘接片插在半导体元件和基板之间而粘接半导体元件和基板时,可用基板的第一区域和向该第一区域变薄的端部构成粘接片的粘贴面。即,可以在没有很大阶差的光滑面上粘贴粘接面。若这样构成,则在粘接片和基板之间不潜入空气,很难产生气泡(还称为空隙void)。
(2)在该半导体装置中,所述端部可以具有倾斜面。若朝向第一区域沿保护膜的厚度方向变薄的端部为倾斜面,则其可以是凸形,也可以是凹形。由此,可达到与上述同样的作用、效果。
(3)在该半导体装置中,所述端部也可以具有倾斜面和从所述配线图案立起的立起面。
(4)在该半导体装置中,所述保护膜的所述端部也可以在所述保护膜的厚度方向上至少形成两级或其以上的台阶形状。
(5)在该半导体装置中,也可以形成所述倾斜面的倾斜角,使其大于0度小于60度。
(6)在该半导体装置中,也可以形成所述倾斜面的倾斜角,使其大于30度小于45度。
(7)在该半导体装置中,所述立起面的高度也可以形成为,从配线图案开始大于0微米小于10微米。由于粘接片的粘接剂具有挠性,所以即使有一些阶差,也可密接基板和保护膜。
(8)在该半导体装置中,所述台阶形状也可以至少包括两个或其以上的立起面,各个所述立起面的高度分别形成为大于0微米小于10微米。
(9)该半导体装置,也可以将导电粒子分散到所述粘接片中,利用所述导电粒子电连接所述配线图案和所述电极。
(10)在该半导体装置中,所述粘接片也可以是绝缘片。
(11)在该半导体装置中,也可以至少在所述第二区域上实施对保护膜形成材料的亲液处理。
(12)本发明的半导体装置的制造方法,包括:在基板上形成配线图案的步骤;在所述基板的装载半导体元件的第一区域以外的第二区域上形成保护膜,使其覆盖所述配线图案的步骤;和在至少包括装载所述半导体元件的第一区域和所述保护膜的端部范围内设置粘接片,通过所述粘接片将所述半导体元件粘接到所述基板上,通过加压而实现所述半导体元件的电极与所述配线图案之间的电接触的步骤,所述保护膜形成为具有向所述第一区域变薄的端部。根据本发明,当将粘接片插在半导体元件和基板之间而粘接半导体元件和基板时,可通过基板的第一区域和向该第一区域变薄的端部构成粘接片的粘贴面。即,可以在没有很大阶差的光滑面上粘贴粘接面。若这样构成,则不会在粘接片和基板之间潜入空气,很难产生气泡(也称为空隙)。
(13)在该半导体装置的制造方法中,也可将所述保护膜形成为在所述端部上具有倾斜面。
(14)在该半导体装置的制造方法中,也可将所述保护膜形成为在所述端部上具有倾斜面和从所述配线图案立起的立起面。
(15)在该半导体装置的制造方法中,也可在所述保护膜的所述端部上沿所述保护膜的厚度方向至少形成两级或其以上的台阶形状。
(16)在该半导体装置的制造方法中,也可将所述倾斜面的倾斜角形成为大于0度小于60度。
(17)在该半导体装置的制造方法中,也可将所述倾斜面的倾斜角形成为大于30度小于45度。
(18)在该半导体装置的制造方法中,也可将所述立起面的高度形成为从配线图案开始大于0微米小于10微米。
(19)在该半导体装置的制造方法中,所述台阶形状也可至少包括两个或其以上的立起面,各个所述立起面的高度形成为分别大于0微米小于10微米。
(20)在该半导体装置的制造方法中,也可将导电粒子分散到所述粘接片中,利用所述导电粒子来电连接所述配线图案和所述电极。
(21)在该半导体装置的制造方法中,所述粘接片也可以是绝缘片。
(22)在该半导体装置的制造方法中,在保护膜形成工序之前,对所述配线图案上的至少所述第二区域实施相对保护膜形成材料的亲液处理。
附图说明
图1是本发明的实施方式的半导体装置的剖面图。
图2A~图2D是说明本发明的实施方式的半导体装置的制造方法的图。
图3是表示安装本发明的实施方式的半导体装置而构成的电路基板的图。
图4是表示具有本发明的实施方式的半导体装置的电子设备的图。
图5是表示具有本发明的实施方式的半导体装置的电子设备的图。
图6是表示本发明的实施方式的半导体装置的变形例的图。
图7是表示本发明的实施方式的半导体装置的变形例的图。
具体实施方式
下面,参照附图说明本发明的实施方式。
(半导体装置)
图1是本发明的实施方式的半导体装置的剖面图。在图1中进行说明。
本发明的实施方式的半导体装置具有基板10。基板10在至少一个面上形成有配线图案12。基板10可以是由挠性基板等有机系材料形成,由金属系基板等无机系材料形成,两者的组合中的其中一种。作为挠性基板,可以使用带状载体(tape carrier)。在基板10上形成有贯通孔14。配线图案12跨越贯通孔14而形成。另外,作为配线图案12的一部分,在贯通孔14上设有焊盘(land)16,用于形成外部电极。
在基板10上形成有保护膜30。保护膜30覆盖配线图案12,承担保护配线图案12免受水分等侵害的任务。例如,使用焊料抗蚀剂。
形成保护膜30,使得在用来装载半导体元件20的基板10上除第一区域26之外的第二区域28上覆盖配线图案12。配线图案12也可在第一区域26上具有连接半导体元件20的电极22的连接用焊盘(未图示)。一般,第一区域26形成为比半导体元件20具有电极22的面24的面积大。
另外,在基板10的第二区域28中,保护膜30具有由平面构成的第一面32,具有端部34。保护膜30的端部34形成为:朝向装载半导体元件20的第一区域26,从具有由平面构成的第一面32部分的厚度开始(例如,约20微米),前端变薄。
保护膜30的端部34也可如图1所示那样地倾斜。若端部34形成为前端部变薄,则其表面也可以是倾斜面36,也可以具有一部分倾斜。倾斜面36可以是凸形、也可以是凹形。另外,倾斜面36也可通过曲面连接作为平面的第一面32或基板的第一1区域26的面。
本发明的实施方式的半导体装置具有粘接片40。粘接片40通过插在半导体元件20和配线图案12之间,而将半导体元件20固定在基板10上。粘接片40可以是各向异性导电膜(ACF(Anisotropic Conductive Film),还称为各向异性导电片)或NCR(Non Conductive Film)等。
各向异性导电膜可以将导电粒子(导电填料)分散到粘接剂(粘接料bonding)中。另外,有时也添加分散剂。由于将导电粒子分散到各向异性导电膜中,所以可通过导电粒子电连接配线图案12和电极22。另外,即使使用不含有导电粒子的粘接片(例如,NCF(Non Conductive Film)),也可通过加压,而电连接配线图案12和电极22。
作为粘接片40的粘接剂,可以使用以环氧系为代表的热固化型粘接剂,也可使用以环氧系或丙稀酸酯系为代表的光固化型粘接剂。进一步,也可使用电子线固化型、热可塑(热粘接)型的粘接剂。
粘接片40也可预先形成为片状。粘附粘接片40,使其从基板10的第一区域26开始达到保护膜30的端部34之上。粘接片40也可覆盖保护膜30的端部34整体,也可仅覆盖端部34的一部分。也可粘附粘接片40,使其从基板10的第一区域26开始,以超过第一区域26和保护膜30端部34的边界。另外,粘接片40也可设置在半导体元件20侧后,粘附在基板10上。
这样,若将粘接片40粘附到由大致平面的第一区域26和倾斜面36构成而形成的平缓面38(没有大阶差的面),则很难在面38和粘接片40之间潜入空气。即,由于没有大的阶差,所以可很难形成气泡。这时,也可将倾斜面36的倾斜角形成为大于0度小于60度。最好将倾斜面36的倾斜角形成为大于30度小于45度。
本发明的实施方式的半导体装置具有半导体元件20。将半导体元件20设置在粘接片40之上。半导体元件20朝向粘接片40设置具有电极22的面24。另外,也可配置电极22,使其位于配线图案12的电极连接用焊盘(未图示)上。电极22也可由半导体元件20的Al垫片(pad)和设置在其上的金属或焊锡等凸块(bump)构成。另外,也可在配线图案12上形成金属或焊锡等凸块,也可蚀刻配线图案12形成凸块。
如图1所示,也可在基板10上设置焊锡球18,例如使其从贯通孔14突出。焊锡球18为外部电极。
这样得到的半导体装置1将粘接片40插在半导体元件20和基板10之间,而粘接半导体元件20和基板10。另外,由基板10的第一区域26和向第一区域26变薄的端部34(具有倾斜面)构成粘附粘接片40的面。即,通过没有很大阶差的平滑面38粘附粘接片40。若这样构成,则粘接片40和基板10之间不会潜入空气,很难形成气泡(还称为空隙)。即使为了粘接片40的固化或软溶而加热,由于没有气泡,所以可防止因气泡的膨胀而产生的粘接片40的裂缝、因水分潜入裂缝而产生的配线图案12的移动。另外,由于还增加了粘接面积,所以还可确保半导体元件20和基板10的粘接强度。
根据本发明的实施方式,如上所述,虽然为通过粘接片40覆盖保护膜的结构,但是可提供可靠性高的半导体装置。
(半导体装置的制造方法)
图2A~图2D是说明本发明的实施方式的半导体装置的制造方法的图。
(1)在本实施方式中,如图2A所示,可使用在至少一个面上形成配线图案12的基板10(详细如上所述)。
(2)在基板10上形成保护膜30。作为保护膜30,可以使用焊料抗蚀剂。可通过用树脂油墨的印刷法(例如丝网印刷法)等形成保护膜30,使其在第二区域28覆盖配线图案12。一般,将第一区域26形成得比具有半导体元件20的电极22的面24的面积大。
形成保护膜30,使其具有由平面构成的第一面32,具有端部34。将端部34形成为向装载半导体元件20的第一区域26变薄。
另外,也可至少在形成保护膜30的第二区域28上实施对保护膜30的形成材料的亲液处理。若对形成保护膜30的区域实施亲液处理,则保护膜30的形成材料和基板10的润湿性提高,可在保护膜30的端部34形成平缓的倾斜面36。
另外,也可分多次进行利用树脂油墨的丝网印刷。这时,优选通过一点一点地移动丝网印刷的掩膜来进行丝网印刷。此外,也可用通常的丝网印刷法形成保护膜30,其后,通过机械加工进行端部34的接面严实组装工序、倒角工序。
这样,如图2A所示,倾斜地形成保护膜30的端部34。若将端部34形成为前端部变薄,则可以是整体为倾斜面36,也可以部分具有倾斜面。倾斜面36可以是凸形,也可以是凹形。另外,也可以通过曲面连接作为平面的第一面32或基板的第一区域26和倾斜面36。
(3)在形成了如上所述保护膜30的基板10上粘附粘接片40。在本实施方式中,粘附粘接片40,使其从第一区域26开始达到保护膜30的端部34上。这时,粘接片40可以覆盖保护膜30的端部34整体,也可以仅覆盖端部34的一部分(前端)。也可以粘附粘接片40,使其从第一区域26开始,超过第一区域26和保护膜30的端部34的边界。另外,也可将粘接片40设置在半导体元件20上后粘附在基板10上。若这样形成,则可通过平缓面38粘接粘接片40,从而可防止空气的潜入。
(4)接着,在粘接片40上装载半导体元件20。这时,具有半导体元件20的电极22的面24向着粘接片40。也可配置半导体元件20,使得电极22位于配线图案12的电极连接用焊盘(图中未示出)上。也可在半导体元件20装载前,将粘接片40设置在基板10上,也可将其预先设置在具有半导体元件20的电极22的面24上。
(5)并且,将夹具50压在与具有半导体元件20的电极22的面24相对的面25上,而向基板10的方向加压半导体元件20。或者,将压力加到半导体元件20和基板10之间。通过该工序,半导体元件20的电极22、配线图案12经粘接片40的导电粒子电导通。另外,使用内置在夹具50中的加热器52,来加热半导体元件20。粘接片40使用例如以环氧系为代表的热固化型粘接剂来作为粘接剂。因此,通过该工序,粘接片40在其与半导体元件20接触的区域中固化,从而可粘接、固定半导体元件20和基板10(参照图2B)。
另外,在向粘接片40的比半导体元件20大的部分加热时,夹具50也可具有比半导体元件20的平面积大的平面积。因此,可以容易加热到半导体元件20的周围,粘接剂的固化和半导体元件20的固定更为可靠。
(6)接着,形成外部电极。例如,如图2C所示,可以在基板10的贯通孔14内及其附近设置焊锡17。焊锡17可例如使用胶状焊锡,通过印刷法来设置。另外,也可将预先形成的焊锡球装载在上述位置上。接着,在软溶工序中加热焊锡17,而如图2D所示,形成焊锡球18。焊锡球18成为外部电极。在该软溶工序中,不仅加热焊锡17,还加热粘接片40。通过该加热,粘接片40的未固化区域也固化了。如上所述,根据本实施方式,虽然为通过粘接片40覆盖保护膜30的结构,但是可以提供可靠性高的半导体装置。
(电路基板、电子设备)
图3表示安装了本实施方式的半导体装置1的电路基板1000。另外,作为具有半导体装置1的电子设备,图4中表示了笔记本型个人计算机2000。图5中表示了移动电话3000。
(变形例)
图6~图7是本发明的实施方式的半导体装置的剖面图。在图6所示的例子中,保护膜60的端部64具有倾斜面66和从基板10立起的立起面68。在端部64的上部形成倾斜面66。立起面68形成为从基板10的配线图案12开始,大于0微米小于10微米。
当通过丝网印刷法形成保护膜60时,图6所示的形状可通过对每个部分改变相当于保护膜60的端部64的丝网印刷掩膜的网孔,通过调整端部64的树脂油墨量来形成。另外,也可分多次进行利用树脂的丝网印刷来形成。另外,也可通过通常的丝网印刷法来形成保护膜60,之后通过机械加工进行端部64的端部34的接面严实组装工序、倒角工序,从而形成倾斜面66。
下面,如上述半导体装置1那样,粘附粘接片40。由于粘接片40的粘接剂具有挠性,所以即使有0微米到10微米的高度阶差,也可使粘接剂进入该阶差而以密封状态来进行粘接。
在图7所示的例子中,保护膜80的端部84形成为在保护膜80的厚度方向上至少有2级或其以上的台阶形状86。另外,该台阶形状86至少包括两个或其以上的立起面88,各个上述立起面88的高度分别形成为大于0微米小于10微米。
例如,在通过丝网印刷法形成保护膜80时,图7所示的台阶形状86通过分多次进行由树脂油墨进行的丝网印刷,并按每进行一次印刷偏移印刷掩膜来形成。
下面,如上述的半导体装置1那样,粘附粘接片40。由于粘接片40的粘接剂具有挠性,所以即使有0微米到10微米的高度阶差,也可进入阶差、而以封闭状态来粘接。
在该变形例中,虽然也为通过粘接片覆盖保护膜的结构,但是可提供可靠性高的半导体装置。另外,通过上述实施方式中的说明所说明的内容也可适用于本变形例。
本发明并不限于上述实施方式,可以有各种变形。例如,本发明包括与实施方式中所说明的结构本质上为相同结构(例如,功能、方法和结果为相同的结构、或目的和结果为相同的结构)。另外,本发明包括置换本实施方式中所说明的结构的非本质部分。另外,本发明包括可实现与本实施方式中所说明的结构有同一作用效果的结构或达到同一目的的结构。另外,本发明包括将公知技术添加到实施方式所说明的结构中的构成。

Claims (20)

1.一种半导体装置,其特征在于,包括:
具有电极的半导体元件;
形成配线图案的基板;
形成为在装载了所述半导体元件的第一区域以外的第二区域中覆盖所述配线图案的保护膜;和
粘接所述半导体元件和所述基板的粘接片,
所述电极与所述配线图案电接触,
所述保护膜具有形成为向装载所述半导体元件的第一区域变薄的端部,
所述粘接片形成为至少从所述基板的第一区域达到所述保护膜的所述端部上。
2.根据权利要求1所述的半导体装置,其特征在于:所述端部具有倾斜面。
3.根据权利要求1所述的半导体装置,其特征在于:所述端部具有倾斜面和从所述配线图案立起的立起面。
4.根据权利要求1所述的半导体装置,其特征在于:形成所述保护膜的所述端部,使其在所述保护膜的厚度方向上至少形成两级或其以上的台阶形状。
5.根据权利要求2或3所述的半导体装置,其特征在于:所述倾斜面的倾斜角形成为大于0度小于60度。
6.根据权利要求2或3所述的半导体装置,其特征在于:形成所述倾斜面的倾斜角,使其大于30度小于45度。
7.根据权利要求3所述的半导体装置,其特征在于:所述立起面形成的高度为从配线图案开始大于0微米小于10微米。
8.根据权利要求4所述的半导体装置,其特征在于:所述台阶形状至少包括两个或其以上的立起面,各个所述立起面的高度分别形成为大于0微米小于10微米。
9.根据权利要求1~4中任一项所述的半导体装置,其特征在于:所述粘接片是绝缘片。
10.根据权利要求1或2所述的半导体装置,其特征在于:至少对所述第二区域实施相对保护膜形成材料的亲液处理。
11.一种半导体装置的制造方法,其特征在于,包括:
在基板上形成配线图案的步骤;
在所述基板的装载半导体元件的第一区域以外的第二区域上形成保护膜,使其覆盖所述配线图案的步骤;
在至少包括装载了所述半导体元件的第一区域和所述保护膜的端部的范围内设置粘接片,通过所述粘接片将所述半导体元件粘接到所述基板上,通过加压而实现所述半导体元件的电极与所述配线图案之间的电接触的步骤;
形成所述保护膜,使其具有向所述第一区域变薄的端部。
12.根据权利要求11所述的半导体装置的制造方法,其特征在于:将所述保护膜形成为所述端部具有倾斜面。
13.根据权利要求11所述的半导体装置的制造方法,其特征在于:形成所述保护膜,使得所述端部上具有倾斜面和从所述配线图案立起的立起面。
14.根据权利要求11所述的半导体装置的制造方法,其特征在于:在所述保护膜的所述端部上沿所述保护膜的厚度方向至少形成两级或其以上的台阶形状。
15.根据权利要求12或13所述的半导体装置的制造方法,其特征在于:将所述倾斜面的倾斜角形成为大于0度小于60度。
16.根据权利要求12或13所述的半导体装置的制造方法,其特征在于:形成所述倾斜面的倾斜角,使其大于30度小于45度。
17.根据权利要求13所述的半导体装置的制造方法,其特征在于:形成所述立起面的高度,使其从配线图案开始大于0微米小于10微米。
18.根据权利要求14所述的半导体装置的制造方法,其特征在于:所述台阶形状至少包括两个或其以上的立起面,将各个所述立起面的高度分别形成为大于0微米小于10微米。
19.根据权利要求11~14中任一项所述的半导体装置的制造方法,其特征在于:所述粘接片是绝缘片。
20.根据权利要求11或12所述的半导体装置的制造方法,其特征在于:在保护膜形成工序之前,对所述配线图案上的至少所述第二区域实施相对保护膜形成材料的亲液处理。
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4641783B2 (ja) * 2004-10-27 2011-03-02 三井金属鉱業株式会社 ディスプレイ装置
JP2007220740A (ja) * 2006-02-14 2007-08-30 Elpida Memory Inc 半導体装置及びその製造方法
JP6179215B2 (ja) * 2013-06-19 2017-08-16 大日本印刷株式会社 タッチパネル用のカバー部材及び当該カバー部材の製造方法
JP6927665B2 (ja) * 2015-12-25 2021-09-01 日東電工株式会社 配線回路基板
CN107484323B (zh) * 2016-06-07 2019-09-20 鹏鼎控股(深圳)股份有限公司 多层柔性电路板及其制作方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1175089A (zh) * 1996-07-25 1998-03-04 夏普公司 一种装配半导体元件到衬底上的构件及其装配方法
US6097610A (en) * 1998-03-27 2000-08-01 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
CN1273695A (zh) * 1998-07-01 2000-11-15 精工爱普生株式会社 半导体装置及其制造方法、电路基板和电子装置
CN1294756A (zh) * 1999-02-18 2001-05-09 精工爱普生株式会社 半导体装置、安装基板及其制造方法、电路基板和电子装置
US6489687B1 (en) * 1999-10-01 2002-12-03 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, manufacturing device, circuit board, and electronic equipment

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05335359A (ja) * 1992-05-28 1993-12-17 Matsushita Electric Works Ltd 半導体実装基板
JPH0982760A (ja) * 1995-07-07 1997-03-28 Toshiba Corp 半導体装置、半導体素子およびその半田接続部検査方法
JP2000022329A (ja) * 1998-06-29 2000-01-21 Toshiba Corp 配線基板および電子ユニットおよび電子部品実装方法
JP4369582B2 (ja) * 2000-01-06 2009-11-25 京セラ株式会社 半導体装置およびその製造方法
JP3554533B2 (ja) * 2000-10-13 2004-08-18 シャープ株式会社 チップオンフィルム用テープおよび半導体装置
JP3536023B2 (ja) * 2000-10-13 2004-06-07 シャープ株式会社 Cof用テープキャリアおよびこれを用いて製造されるcof構造の半導体装置
US6756671B2 (en) * 2002-07-05 2004-06-29 Taiwan Semiconductor Manufacturing Co., Ltd Microelectronic device with a redistribution layer having a step shaped portion and method of making the same
JP4056424B2 (ja) * 2003-05-16 2008-03-05 シャープ株式会社 半導体装置の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1175089A (zh) * 1996-07-25 1998-03-04 夏普公司 一种装配半导体元件到衬底上的构件及其装配方法
US6097610A (en) * 1998-03-27 2000-08-01 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
CN1273695A (zh) * 1998-07-01 2000-11-15 精工爱普生株式会社 半导体装置及其制造方法、电路基板和电子装置
CN1294756A (zh) * 1999-02-18 2001-05-09 精工爱普生株式会社 半导体装置、安装基板及其制造方法、电路基板和电子装置
US6489687B1 (en) * 1999-10-01 2002-12-03 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, manufacturing device, circuit board, and electronic equipment

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