CN1315055A - 通孔凸块接触 - Google Patents
通孔凸块接触 Download PDFInfo
- Publication number
- CN1315055A CN1315055A CN99810060A CN99810060A CN1315055A CN 1315055 A CN1315055 A CN 1315055A CN 99810060 A CN99810060 A CN 99810060A CN 99810060 A CN99810060 A CN 99810060A CN 1315055 A CN1315055 A CN 1315055A
- Authority
- CN
- China
- Prior art keywords
- stopper
- hole
- opening
- circuit
- width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- 229910000679 solder Inorganic materials 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000011159 matrix material Substances 0.000 claims description 43
- 230000004888 barrier function Effects 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 14
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 239000010931 gold Substances 0.000 claims description 7
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 claims description 4
- 229910052763 palladium Inorganic materials 0.000 claims description 4
- 239000004642 Polyimide Substances 0.000 claims description 2
- 229920000728 polyester Polymers 0.000 claims description 2
- 229920001721 polyimide Polymers 0.000 claims description 2
- 229910045601 alloy Inorganic materials 0.000 claims 2
- 239000000956 alloy Substances 0.000 claims 2
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 238000000034 method Methods 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 8
- 238000005538 encapsulation Methods 0.000 description 7
- 238000005728 strengthening Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000004907 flux Effects 0.000 description 5
- 238000005452 bending Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- 238000009417 prefabrication Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 238000004100 electronic packaging Methods 0.000 description 2
- 239000002313 adhesive film Substances 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000013536 elastomeric material Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000006261 foam material Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 210000001503 joint Anatomy 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000006386 neutralization reaction Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Abstract
一线路包括一基体,该基体包括一具有一第一表面和一第二表面的绝缘层。一导电层形成在第一表面。在基体的绝缘层中形成一斜面通孔。该通孔有一在第一表面中的具有第一宽度的第一开口,一在第二表面中的具有比第一宽度宽的第二宽度的第二开口。一导电塞子连接于导电层。该塞子形成在通孔中,并从相邻的第一开口朝第二开口延伸,终止在靠近第二开口的一塞子接头表面。一导电焊球连接于塞子接头表面并延伸至从第二表面伸出。
Description
背景技术
本发明总的涉及焊球电子互连,尤其涉及一种强化斜面通孔中的焊球连接的通孔塞子适配器。
若干线路层之间的垂直互连是众所周知的。美国专利3,541,222公开了一种连接器丝网(connector screen),用于互连相邻线路板或模板的对齐电极。连接器丝网包括嵌入一非导体支承材料中的若干相隔的导电连接器元件的阵列,其中导电连接器元件从支承材料的两侧伸出。要选择连接器元件的尺寸和间距,使得连接器丝网设置在诸线路板或模板之间,能够在电极之间提供所需的互连,而不需要使连接器丝网与线路板或模板对齐。制作连接器丝网的一较佳方法包括形成一具有在非导电基板中的排成网格阵列的突起部的导电模具。然后将导电材料浇铸在突起部之间,随后取下模具的选定部分,形成非导电材料的网状物,以支承从网状物的两侧伸出的隔开的导电元件的阵列。
美国专利4,830,264公开了一种形成焊料终端的方法,该焊料终端用于一无管脚模板、最好是用于一种无管脚的金属化陶瓷模板。方法由如下步骤构成:形成一基体,该基体具有形成在其顶表面上的导体阵列以及从顶表面延伸到底表面的预成形通孔;在基体底表面的预成形通孔开口的至少一个中施加一小滴焊剂,以通过毛细管作用用焊剂填充通孔,并在底部的开口中形成一团焊剂;施加一焊料预制品,例如在每一团焊剂上的焊球,即焊球粘结于焊剂上,预制品的体积基本上等于通孔的内体积加上要形成的凸块的体积;加热,使得焊料预制品的焊料回流,以用焊料填充通孔和眼孔的内体积;以及,将焊料冷却到熔点以下,使得熔化的焊料凝固,在通孔中形成焊料终端,同时在通孔中形成焊料柱体。最终的无管脚金属化陶瓷模板具有在与下一层的封装(即印刷线路板)对接的模板的I/O之间的若干连接,这些连接由一体的焊料终端构成。每一一体的焊料终端包括一在金属化陶瓷基体的通孔中的柱体、在基体顶表面的小丘状焊料以及在底表面上的用于与下一层的封装互连的球形状焊料凸块。
在美国专利5,401,913中,一多层线路板包括在多层板的相邻线路板之间的电互连。设置一穿过线路板层的通孔。该通孔充填有通孔金属。该通孔金属镀有低熔点金属。一粘结剂薄膜堆积在线路板层上。多层线路板的相邻层叠堆在一起并对齐。这些层在热量和压力下层压在一起。低熔点金属在相邻层之间提供一种电气互连。
美国专利5,491,303公开一种连接两个或多个印刷线路板的插入件,印刷线路板上包括一载有线路的基体,基体的任一侧有两个或多个焊料衬垫。每一焊料衬垫连接于一在基体中的导电通道,提供了从一侧到另一侧的电互连。每一焊料衬垫上有一焊料凸块。将在插入件的一侧上的焊料凸块焊接到在一印刷线路板上的对应焊料衬垫,就制成一线路组件。类似地,将在插入件另一侧上的焊料凸块焊接到一第二印刷线路板的对应焊料衬垫。
美国专利5,600,884公开了一种电连接件,其一个表面连接于一第一电路件的一连接部分,其另一表面连接于一第二电路件的一连接部分。电连接件包括一由一种电绝缘件所形成的固定件。该固定件有多个凹陷的孔。连接件也包括多个设置在电绝缘件中的导电件,它们彼此绝缘。导电件的一端暴露在要连接于第一电路件连接部分的固定件的一个表面。导电件的另一端暴露在要连接于第二电路件的连接部分的固定件的另一表面。
美国专利5,726,497公开了一种制造在一硅半导体基体上的半导体装置的方法,该方法包括:形成一在半导体基体上的第一强化层(stress layer);形成一在第一强化层上面的互连层;形成一在互连层上的第二强化层;形成一在第二强化层上面的金属间绝缘(inter-metal dielectric)(IMD)层;布置和蚀刻一穿过金属间绝缘层和第二强化层的通道开口,暴露一在金属互连层的表面上的接触区域,以及在一足以使金属互连层挤入通道中的温度加热所述装置。
美国专利5,757,078公开了一种半导体装置,它包括一半导体芯片,该芯片有若干电极衬垫、一由多个绝缘膜构成的并通过粘结剂粘结到半导体芯片上的封装。封装包括置于多个绝缘膜之间的布线阵列。借助通孔,布线阵列的一端有选择地连接于电极衬垫,另一端连接于多个导电突起。半导体装置还包括多个借助设置在最外面绝缘薄膜中的通孔从最外布线阵列伸出的导电凸起。
日本申请JP10-41356公开了一种带式载体(tape carrier),当半导体元件粘结到一用于BGA场合的基体板外面部分时,它被用作粘结媒质。一绝缘薄膜包括具有直的或非倾斜的壁的通孔。在通孔中形成一导电焊盘,焊球具有与通孔焊盘内侧结合的一侧。各焊球的其余部分伸出绝缘薄膜。
在IC封装中使用柔性线路具有增长势头已有多年了,其中,在带式网格阵列(Tape Grid Array)(TBGA)IC封装的应用中采用了穿过柔性线路绝缘体的通孔连接,最近又应用于芯片尺度封装(Chip Scale Packaging)(CSP)中。在球网格阵列(BGA)应用中,通孔互连传统地使用一焊球,该焊球首先回流以通过通孔接触柔性线路,然后用传统的表面安装组件的做法再回流到印刷线路板。
这种焊球连接必须从柔性线路到印刷线路板有一可靠的电子互连。这种可靠性往往直接与连接到柔性线路的焊料面积有关,因为这种互连的一个通常失灵的形式是在最小横截面处的焊料的焊球剪断。因此,希望用较大的孔来增加分布剪切应力的面积,以满足焊球互连最小可靠性要求。
相反,对于较小的电子封装和较高的输入/输出(I/O),需要增加布线密度,包括较小的通孔尺寸,使得电子迹线能够布线在焊球通孔区之间。通孔小要求通孔收集衬垫也小,这样,允许印刷线路板互连通孔之间有较大的空间来布置电子迹线。
传统上,在绝缘体中的通孔经冲孔而形成,留下一个通过绝缘体的具有直壁的通孔。其它的方法包括化学溶解绝缘体和激光钻孔,以暴露柔性线路的金属导体。将焊球直接连接到这些通孔中的任何一个方法都是通过通孔的尺寸来控制焊球互连的可靠性,这样,通孔的直径通常必须大于0.200毫米,以满足电子封装的最小可靠性最小要求。
因此,需要一种装置和方法,能够使焊球坚固而可靠地连接于具有小直径通孔和通孔收集衬垫的柔性线路,从而允许有较大的空间布置较多的电子迹线。
发明概要
因此,一个实施例提供了一连接于具有小直径通孔的柔性线路的增强焊球,这样改进了柔性线路的布线,解决了基于BGA封装应用中的较高的I/O和较精细的间距弯曲。为此,一线路包括一基体,该基体包括一具有第一表面和第二表面的绝缘层。在第一表面上有一导电层。一斜面通孔形成在绝缘层中,并在第一表面中有一具有第一宽度的第一开口,在第二表面中有一具有比第一宽度宽的第二宽度的第二开口。一导电塞子形成在通孔中,连接于导电层,并从相邻的第一开口朝第二开口延伸。该塞子终止在靠近第二开口的一塞子接头表面。一导电焊球连接于塞子接头表面并延伸至从第二表面伸出。
该实施例的一主要优点是,通孔适配器塞子能够用小通孔(小于0.200毫米直径)使焊球可靠地连接于柔性线路。由于使用通孔塞子适配器概念,焊球互连的可靠性肯定不会受到威胁,从而容许基于IC封装应用的高的I/O、精细间距弯曲(fine pitch flex)的布线要求。对于柔性线路,由于使用一般设计的规定,一较小的通孔容许一较小的收集衬垫,因此,在收集衬垫之间具有较大的空间来布置电子迹线。
附图简要说明
图1是一侧视图,它示出了用多个焊球互连于一线路板的一基体的实施例。
图1A是一俯视图,它示出了一圆形通孔开口。
图1B是一俯视图,它示出了一椭圆形通孔开口。
图2是一侧视图,它示出了在一锥形通孔中的塞子的实施例。
图3是另一侧视图,它示出了在一锥形通孔中的塞子的实施例。
图4是另一侧视图,它示出了在一锥形通孔中的塞子的实施例。
图5是一侧视图,它示出了用一焊球互连到一线路板的一基体的实施例。
图6是一侧视图,它示出了用焊球互连到一线路板的一双层基体的实施例。
图7是一侧视图,它示出了包括一连接于基体的IC芯片的芯片规模封装的
实施例。
图8是一沿图7的8-8线截取的基体的视图。
详细说明
在图1的第一实施例中,一柔性线路10包括一由柔性绝缘材料形成的基体12。基体12是厚度T1为12微米至25微米的聚合物或其它合适的材料。聚合物可以是用于电子装置的聚酰亚胺、聚酯或其它已知的聚合物。基体12还包括一第一表面14和一第二表面16。在第一表面14上形成铜、镀金铜、金或其它合适材料的导电层18,该导电层18包括多个导电的收集衬垫20和多个布置在收集衬垫20之间的导电迹线22。
在基体12中形成多个斜面通孔24。每一通孔24在第一表面14有一具有第一宽度W1的第一开口26,在第二表面16有一具有第二宽度W2的第二开口28。第二宽度W2大于第一宽度W1。斜面通孔24包括一从第一表面14倾斜一20°至80°、最好是20°至45°的α角的侧壁30。第一开口26在图1A中是圆形的,在图1B中是椭圆形的,或是其它合适形状,第一宽度W1为0.05毫米至0.5毫米。
在图1和2中,在斜面通孔24中形成一导电塞子32,该导电塞子32从与第一开口26相邻的第一塞子接头表面34伸向第二开口28。塞子32终止在与第二开口28相邻的第二塞子接头表面36。第一塞子接头表面34连接于导电收集衬垫20。第二塞子接头表面36是拱顶形的。第二塞子接头表面36可终止在第一表面14与第二表面16之间,也可使拱顶的一部分从第二表面16朝外延伸,如图3所示,或整个拱顶形表面从第二表面16朝外延伸,如图4所示。因此,塞子从第一塞子接头表面34延伸到第二塞子接头表面36的厚度或高度T2的范围是可变的,但至少是5微米,如图2所示。
如图5所示,一导电焊球38在第一焊球表面40连接于第二塞子接头表面36,并从第二基体表面16伸出。焊球38终止在与一印刷线路板44接触的第二焊球表面42。塞子32和焊球38可由各种合适的材料所形成。例如,塞子32可由与用容易熔解的锡铅焊料形成的焊球38结合的高温锡铅焊料所形成。还有,塞子32可由与用一种锡铅焊料形成的焊球38结合的铜所形成。也可用其它的组合物,只要满足导电要求和它们能提供剪切强度比焊料材料强的塞子材料的条件。作为另一例子,塞子32可由与用一种锡铅焊料形成的焊球38结合的镍形成。此外,为改进粘结,可在收集衬垫20与第一塞子接头表面34之间设置一接头涂层46。涂层46可由从金、钯(paladium)、和镍金中选择的合适材料所形成。此外,塞子32与焊球38之间的粘结可用在它们之间另一接头涂层48改进。涂层48可由也从金、钯、和镍金中选择的合适材料形成。
在图1中,斜面通孔24以并排形式分开。因此,收集衬垫20也以并排形式分开。这些通孔24之间的中心距D为0.25毫米至约1.27毫米。这样的间隔使至少三个迹线22在并排的收集衬垫20之间通过。
在图6中,线路10包括一基体,该基体包括一第一绝缘层12a和一第二绝缘层13。第一绝缘层12a包括一第一表面14a和一第二表面16a。一导电层18a设置在第一绝缘层12a与第二绝缘层13之间的第一表面14a上。一斜面通孔24形成在第一绝缘层12a中,如上所述。还有,第二绝缘层13可由上述的聚合物材料形成。12a和13中的一层可设置为另一层的覆盖涂层。
众所周知,带式球网格阵列(tape ball grid array)(TBGA)封装一般包括一基体,基体上有一安装在被一斜面通孔阵列包围的空穴中的集成线路(IC)。图7和8中的一个实施例公开了一种改进,这种改进使得基体的表面面积基本上与IC相同。由于如上所述的斜面通孔的开口的尺寸缩小,所以这是可能的。因此,缩小开口的尺寸的优点是,能够增加布置在这些通孔之间的迹线。还有,相反的或较大的斜面通孔的开口增加表面接触,以提高焊球的剪切强度。图7中的芯片尺度封装100包括一具有第一表面114和第二表面116的基体112。第一表面114的表面面积A1基本上与安装在基体112上的IC150的第二表面面积A2相同。一在第一表面114面积的一部分上的导电层118通过引线152连接于IC150。一在基体112表面114上的粘结层155和一在IC150上的粘结层157通过它们之间的插入层154而互连。例如,插入层154可以是一种诸如泡沫或弹性材料的顺从材料,或是一种诸如陶瓷或铜片的非顺从材料。基体112包括多个如上所述的斜面通孔124。每一斜面通孔包括一在第一表面114的第一开口126和一在第二表面116的第二开口128。如上所述,第二宽度比第一宽度大。在每一斜面通孔中设置一塞子132,以从相邻的第一开口126延伸到相邻的第二开口128,并终止在一塞子接头表面136。一导电焊球138连接于塞子接头表面136并延伸至从第二表面116伸出,以连接于一印刷线路板144。因此,多个焊球138提供了均匀分布在基体112的第二表面116的阵列,不会由于此前普遍知道的将一IC封装安装在相反的表面114上所需的间隔而阻断。
如所看到的,这些实施例的主要优点是通孔塞子适配器使得焊球通过小的通孔(直径小于0.200毫米)可靠连接于柔性线路。使用通孔塞子适配器方案,焊球互连的可靠性肯定不会受到削弱,从而容许基于IC封装应用的高的输入/输出(I/O)、精细间距弯曲(fine pitch flex)的布线要求。对于柔性线路,使用一般设计的规定,一较小的通孔容许一较小的收集衬垫,因此,在收集衬垫之间具有较大的空间来布置电迹线。作为一例子,在一直径为0.085毫米的斜面通孔中使用一通孔塞子适配器,可在收集衬垫之间布置4条迹线,而且具有与仅允许布置一条迹线的0.300毫米通孔相类似的焊球互连可靠性。
前面描述了一柔性线路,其中用传统的焊球和一通孔塞子适配器,在精细柔性线路与粗糙的印刷线路板焊球衬垫之间有一z轴通孔互连。该通孔塞子适配器的一种这样的应用为BGA至印刷线路板互连的IC封装中的柔性线路应用。
通孔塞子适配器是一种可被附加地镀入一斜面通孔中的金属塞子。除用附加的电镀工艺来形成塞子之外,诸如焊料回流之类工艺也可用于形成通孔塞子。这种通孔塞子适配器是一种截锥体(一圆锥体在两平行平面之间的实心体)形的金属结构,在第二接头表面呈微拱顶形。当截锥体的z方向厚度在斜面通孔中增大时,传统焊球连接件的表面面积也显著增大,产生一机械适配器,它允许小通孔具有与大通孔应用相类似的焊球互连可靠性。
柔性线路中的小通孔允许改进柔性线路的布线,以提高基于BGA封装应用的较高的I/O和较小的间距弯曲。
其结果是,一个实施例提供了一种线路,它包括一基体,该基体包括一具有一第一表面和一第二表面的绝缘层。一导电层在第一表面上。一斜面通孔形成在绝缘层中。通孔在第一表面有一为第一宽度的第一开口和在第二表面中有宽度比第一宽度大的第二宽度的第二开口。一导电塞子连接于导电层,形成在通孔中并从相邻的第一开口伸向第二开口。塞子终止在与第二开口相邻的一塞子接头表面。一导电焊球连接于塞子接头表面,并从第二表面伸出。
另一实施例提供一种线路,它包括一基体,该基体包括一具有一第一表面和一第二表面的绝缘层。一导电层在第一表面上。一斜面通孔形成在绝缘层中。通孔在第一表面有一为第一宽度的第一开口和在第二表面中有宽度比第一宽度大的第二宽度的第二开口。一导电塞子连接于导电层,形成在通孔中并从相邻的第一开口伸向第二开口。塞子终止在与第二开口相邻的一塞子接头表面。一导电焊球有一连接于塞子接头表面的第一焊球表面。焊球延伸至从第二表面伸出,并终止在一第二焊球表面。一印刷线路板与第二焊球表面结合。
在另一实施例中,一线路包括一基体,该基体包括一具有一第一表面和一第二表面的绝缘层。一对并列的斜面通孔形成在绝缘层中。每一通孔在第一表面有一为第一宽度的第一开口和在第二表面中有宽度比第一宽度大的第二宽度的第二开口。每一通孔包括一具有一与第一开口相邻的第一塞子接头表面的导电塞子。每一塞子从相邻的第一塞子接头表面伸向第二开口。每一塞子终止在与第二开口相邻的一第二塞子接头表面。一导电焊球形成在每一通孔中,并具有一与其对应的第二塞子接头表面结合的第一焊球表面,并延伸至从第二表面伸出。每一焊球终止在一第二焊球表面。一印刷线路板与第二焊球表面结合。一导电收集衬垫层与每一塞子的第一接头表面结合,以形成并列的、分开的收集衬垫层。多个导电迹线在并列的收集衬垫层之间延伸。
另一实施例提供一种将焊球连接到一柔性线路基体中的一通孔中的方法。该方法是通过在一具有一第一表面和一第二表面的柔性线路基体中形成一斜面通孔来实现的。一第一通孔开口形成在第一表面中,并有一第一宽度。一第二通孔的开口形成在第二表面中,并有一比第一宽度大的第二宽度。一导电层形成在第一开口中。一导电塞子形成在连接于导电层的斜面通孔,使得塞子从相邻的第一表面朝第二表面延伸。塞子终止在与第二表面相邻的第一塞子接头表面。一导电焊球与塞子接头表面结合。焊球延伸至从第二表面伸出。
尽管示出和描述了所示的实施例,但在上述的公开中和一些例子中可进行广泛的修改、改变和替换,可采用实施例的一些特征,而不对应使用其它的特征。因此,要知道的是,可大范围地和与在此所公开的实施例的范围一致的方式解释所附的权利要求书。
Claims (13)
1.一线路,它包括:
一基体,该基体包括一具有一第一表面和一第二表面的绝缘层;
一在第一表面上的导电层,
其中,绝缘层和导电层形成一柔性线路;
一形成在绝缘层中的斜面通孔,该通孔在第一表面中有一具有第一宽度的第一开口,在第二表面中有一具有比第一宽度宽的第二宽度的第二开口;
一连接于导电层的导电塞子,该导电塞子形成在通孔中,并从相邻的第一开口朝第二开口延伸,终止在靠近第二开口的一塞子接头表面;以及
一连接于塞子接头表面并延伸至从第二表面伸出的导电焊球。
2.如权利要求1所述的线路,其特征在于,绝缘层由从聚酰亚胺和聚酯中选择的聚合物材料形成,这种材料的厚度在12微米至125微米之间。
3.如权利要求1所述的线路,其特征在于,斜面通孔侧壁从第一表面倾斜一从20°至80°的角度。
4.如权利要求1所述的线路,其特征在于,塞子接头表面形成一拱顶。
5.如权利要求4所述的线路,其特征在于,拱顶在第一表面与第二表面之间。
6.如权利要求4所述的线路,其特征在于,拱顶的一部分从第二表面朝外延伸。
7.如权利要求1所述的线路,其特征在于,塞子有一从第一表面延伸到拱顶的厚度,该厚度至少是5微米。
8.如权利要求1所述的线路,其特征在于,球由一种锡铅焊料所形成,塞子由一种导电材料形成,其剪切强度比锡铅焊料强。
9.如权利要求1所述的线路,其特征在于,导电层由铜或金形成。
10.如权利要求9所述的线路,其特征在于,还包括:
一在导电层与塞子之间的接头涂层,该涂层从金、钯和镍金材料组中选择。
11.如权利要求9所述的线路,其特征在于,还包括:
一在塞子接头表面与球之间的接头涂层,该涂层从金、钯和镍金材料组中选择。
12.一线路,它包括:
一基体,该基体包括一具有一第一表面和一第二表面的绝缘层;
一对形成在绝缘层中的并排的斜面通孔,每一通孔在第一表面中有一具有第一宽度的第一开口,在第二表面中有一具有比第一宽度宽的第二宽度的第二开口;
每一通孔包括一导电塞子,导电塞子有一与第一开口相邻的第一塞子接头表面,塞子从相邻的第一塞子接头朝第二开口延伸,塞子终止在靠近第二开口的一第二塞子接头表面;
一形成在通孔中的导电焊球,每一焊球有一与其对应的第二塞子接头表面接触的第一焊球表面,并延伸至从第二表面伸出,各焊球终止在第二焊球表面;
一与第二焊球表面结合的印刷线路板;
一与各塞子的第一接头表面结合的导电收集衬垫层,以形成若干并排的间隔开的收集衬垫层;以及
多个在并排的收集衬垫层之间延伸的导电迹线。
13.如权利要求12所述的线路,其特征在于,多个导电迹线包括至少三个迹线。
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- 1999-01-15 WO PCT/US1999/000179 patent/WO2000013232A1/en active IP Right Grant
- 1999-01-15 CA CA002338550A patent/CA2338550A1/en not_active Abandoned
- 1999-01-15 AU AU24513/99A patent/AU2451399A/en not_active Abandoned
- 1999-01-15 IL IL14105199A patent/IL141051A0/xx unknown
- 1999-01-15 CN CNB998100609A patent/CN1192429C/zh not_active Expired - Fee Related
- 1999-01-15 EP EP99904023A patent/EP1118119A1/en not_active Withdrawn
- 1999-01-15 KR KR10-2001-7002416A patent/KR100367126B1/ko not_active IP Right Cessation
- 1999-09-22 TW TW088114625A patent/TW463348B/zh not_active IP Right Cessation
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CN102271470A (zh) * | 2010-06-03 | 2011-12-07 | 株式会社村田制作所 | 电子器件的制造方法及电子器件 |
CN103117262A (zh) * | 2011-11-16 | 2013-05-22 | 东琳精密股份有限公司 | 具有连接接口的电子装置、其电路基板以及其制造方法 |
CN104241231A (zh) * | 2013-06-11 | 2014-12-24 | 宏启胜精密电子(秦皇岛)有限公司 | 芯片封装基板及其制作方法 |
CN104241231B (zh) * | 2013-06-11 | 2017-12-08 | 南安市鑫灿品牌运营有限公司 | 芯片封装基板的制作方法 |
US20220231198A1 (en) * | 2021-01-20 | 2022-07-21 | Gio Optoelectronics Corp | Substrate structure and electronic device |
CN113038703A (zh) * | 2021-03-17 | 2021-06-25 | 京东方科技集团股份有限公司 | 一种柔性电路板及其制造方法及电子设备 |
Also Published As
Publication number | Publication date |
---|---|
US20020113312A1 (en) | 2002-08-22 |
CN1192429C (zh) | 2005-03-09 |
TW463348B (en) | 2001-11-11 |
US20010045611A1 (en) | 2001-11-29 |
JP3898891B2 (ja) | 2007-03-28 |
US6400018B2 (en) | 2002-06-04 |
KR100367126B1 (ko) | 2003-01-06 |
WO2000013232A1 (en) | 2000-03-09 |
CA2338550A1 (en) | 2000-03-09 |
IL141051A0 (en) | 2002-02-10 |
KR20010072971A (ko) | 2001-07-31 |
AU2451399A (en) | 2000-03-21 |
US6864577B2 (en) | 2005-03-08 |
JP2002524857A (ja) | 2002-08-06 |
EP1118119A1 (en) | 2001-07-25 |
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