CN1267992C - 多层布线结构的半导体器件 - Google Patents
多层布线结构的半导体器件 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 14
- 238000000034 method Methods 0.000 title description 14
- 239000001257 hydrogen Substances 0.000 claims description 9
- 229910052739 hydrogen Inorganic materials 0.000 claims description 9
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 8
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 8
- 239000003990 capacitor Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 description 30
- 239000002184 metal Substances 0.000 description 30
- 229910052581 Si3N4 Inorganic materials 0.000 description 19
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 19
- 238000006243 chemical reaction Methods 0.000 description 15
- 238000005245 sintering Methods 0.000 description 15
- 238000005755 formation reaction Methods 0.000 description 14
- 230000015572 biosynthetic process Effects 0.000 description 13
- 239000007789 gas Substances 0.000 description 13
- 238000010438 heat treatment Methods 0.000 description 12
- 239000000463 material Substances 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 10
- 230000035939 shock Effects 0.000 description 8
- 239000011347 resin Substances 0.000 description 7
- 229920005989 resin Polymers 0.000 description 7
- 238000003466 welding Methods 0.000 description 7
- 239000011248 coating agent Substances 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 6
- 239000002904 solvent Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 230000009471 action Effects 0.000 description 4
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 4
- 238000012858 packaging process Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- -1 polysiloxane Polymers 0.000 description 4
- 229920001296 polysiloxane Polymers 0.000 description 4
- 230000001902 propagating effect Effects 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 239000012298 atmosphere Substances 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000006378 damage Effects 0.000 description 3
- 230000018044 dehydration Effects 0.000 description 3
- 238000006297 dehydration reaction Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000012299 nitrogen atmosphere Substances 0.000 description 3
- 239000002243 precursor Substances 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000009931 harmful effect Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229920002521 macromolecule Polymers 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 210000004027 cell Anatomy 0.000 description 1
- 210000000170 cell membrane Anatomy 0.000 description 1
- 238000009833 condensation Methods 0.000 description 1
- 230000005494 condensation Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- RTZKZFJDLAIYFH-UHFFFAOYSA-N ether Substances CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 239000000178 monomer Substances 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000007634 remodeling Methods 0.000 description 1
- 230000004043 responsiveness Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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Abstract
本发明揭示一种多层布线结构的半导体器件,该半导体器件包括:设置在形成电容绝缘膜的第一区域上的第一绝缘膜;设置在所述第一区域以外的第二区域上的第二绝缘膜;与所述第二绝缘膜相比,所述第一绝缘膜加热时氢气释放量较少。该半导体器件能防止从绝缘膜排出的氢气引起强介电体存储器和金属-绝缘体-金属电容绝缘膜性能恶化。
Description
相关申请的交叉引用
本申请基于并宣称以2001年9月27日提交的在先日本专利申请No.2001-298309为优先权,该申请的整个内容在此引入为参考。
发明背景
1.发明领域
本发明涉及多层布线结构的半导体器件,尤其涉及同一布线层内的绝缘膜的结构。
2.相关技术说明
为实现半导体器件,特别是LSI的性能提高,多层布线结构中使用的绝缘膜朝低介电率发展。即,通过作为布线彼此之间设置的绝缘膜使用低介电率的绝缘膜,可降低布线彼此之间的寄生电容,改善传播过布线的信号的延迟时间,实现LSI动作的高速化。
这里,为使绝缘膜的介电率k降低到3以下,需要降低绝缘膜的密度。但是,由于和绝缘膜的机械强度的折衷关系,绝缘膜低介电率化,使得机械强度不足够。
原来的多层布线结构的半导体器件中,同一布线层使用的绝缘膜用一种材料构成,作为该绝缘膜使用时,产生下面的问题。
第一问题是将低介电率绝缘膜用于多层布线结构时,焊接工序和封装工序等不耐机械冲击,绝缘膜会割裂。
例如,图1表示由于焊接工序时的机械冲击割裂绝缘膜的情况。图1中,多个布线层60的每一个都使用低介电率密度小的材料构成的绝缘膜61构成。多个金属布线62分别由埋置在各绝缘膜61的表面形成的例如Cu构成。最上层的布线层60上除金属布线层62外,还形成Cu构成的焊盘63。另外,最上层的布线层60上形成钝化膜64。
这里,作为上述绝缘膜61,使用低介电率密度小的材料时,由于焊接工序时对焊盘63的机械冲击,在与焊盘63的下面角部相接的绝缘膜61部分上产生割裂。
第二问题是形成绝缘膜的途中,从绝缘膜排出的气体、水对元件产生不良影响。通过甲基聚硅氧烷的涂布、烧结形成绝缘膜时,甲基聚硅氧烷的涂布膜由于脱水缩合反应而进行架桥,因此必然在成膜的过程中释放大量的氢和水。但是,LSI中,形成强介电体存储器单元和MIM(Metal-Insulator-Metal:金属—绝缘体—金属)电容等时,这些元件的电容绝缘膜中的很多在氢气氛中加热时会引起性能恶化。
图2A~2C表示构成多层布线结构的一个布线层中形成MM电容的半导体器件的制造工序。
首先,如图2A所示,例如SOG(Spin On Glass)等构成的绝缘膜61的表面上形成埋置例如Cu构成的金属布线62的布线层60。接着在整个面上形成例如硅氮化物(SiN)等构成的阻止膜65,另外,在其上形成MIM电容66。MIM电容66具有由上部电极和下部电极夹住例如硅氮化物、钽氧化物、钛氮化物等构成的电容绝缘膜的结构。
接着如图2B所示,涂布例如甲基聚硅氧烷,之后进行烧结形成构成上层的布线层的绝缘膜61。烧结该绝缘膜61时,从甲基聚硅氧烷的涂布膜释放大量的氢(H)。该释放的氢通过加热,把氢引入MIM电容66的电容绝缘膜中,引起性能恶化。
之后,如图2C所示,形成例如Cu构成的金属布线62来贯通绝缘膜61的表面和内部。
第三问题是由于从绝缘膜释放的气体的原因,引起其他膜的腐蚀、侵蚀,造成膜被破坏。根据绝缘膜的的种类,有吸水性、透水性高的膜。在具有结合能量比较低的结合的绝缘膜中,也有多层布线形成工序时的350~400℃左右的温度下释放气体的不稳定膜。通过这种逃逸气体,释放气体的绝缘膜自身的特性当然也变化,由于释放气体的原因,其他膜被腐蚀、侵蚀,引起膜被破坏。
图3表示作为构成布线层的绝缘膜61使用容易释放气体的膜时,在加热工序时引起膜破坏的情况。
图3中,构成布线层的绝缘膜61上形成硅氮化物(SiN)等构成的阻止绝缘膜65后,在其上形成新的绝缘膜61。烧结该新的绝缘膜61时的加热工序时,作为绝缘膜61使用容易释放气体的膜时,从该绝缘膜61释放气体,由于该释放气体,使得与下部的膜的密合性恶化的部分,例如焊盘63的上部中,在阻止绝缘膜65上产生膜破坏。
这样,在原来,用一种材料构成同一布线层使用的绝缘膜。因此,作为绝缘膜使用低介电率的绝缘膜,要实现动作的高速化时,机械冲击在绝缘膜中产生割裂,从绝缘膜排出的气体和水对元件产生不良影响。由于从绝缘膜释放的气体的原因,引起膜腐蚀和侵蚀,引起膜破坏等,这些在可靠性方面都是问题。
发明概述
根据本发明的一个方面,提供一种多层布线结构的半导体器件,包括:被施加机械压力的电极;设置在需要机械强度的区域上并形成上述电极的第一绝缘膜;与上述第一绝缘膜形成在同一层上并设置在与上述第一绝缘膜相比不需要机械强度的区域上的第二绝缘膜;在上述第二绝缘膜表面上设置的布线层。
根据本发明的另一个方面,提供一种多层布线结构的半导体器件的制造方法,包括:在衬底上涂布产生架桥反应或发泡反应的绝缘材料的膜;热处理上述绝缘材料的膜,产生架桥反应或发泡反应,在上述衬底上形成第一绝缘膜;在上述衬底上选择地剩余上述第一绝缘膜并在其他区域去除上述第一绝缘膜;在去除上述第一绝缘膜的区域形成第二绝缘膜。
附图的简要说明
图1是已有的半导体器件的截面图;
图2A~2C是顺序表示已有的半导体器件的制造工序的截面图;
图3是已有的半导体器件的截面图;
图4A是本发明的第一实施例的LSI芯片的平面图;
图4B是沿图4A中4B-4B线的截面图;
图5A~5G是顺序表示第一实施例的LSI芯片的制造工序的截面图;
图6A~6B是顺序表示第一实施例的LSI芯片的其它制造工序的截面图;
图7A是本发明的第二实施例的LSI芯片的平面图;
图7B是沿着图7A的7B-7B线的截面图;
图8A~8F是顺序表示第二实施例的LSI芯片的制造工序的截面图;
图9A是本发明的第三实施例的LSI芯片的平面图;
图9B是沿着图9A的9B-9B线的截面图;
图10是本发明的第四实施例的LSI芯片的截面图;
图11A是本发明的变形例的布线层的平面图;
图11B是沿着图11A的11B-11B线的截面图;
发明的具体说明
下面参考附图根据实施例详细说明本发明。
图4A,4B是在LSI中实施本发明的第一实施例的LSI芯片的平面图和截面图。图4B中仅表示出芯片上部附近结构。这些图不必反映实际尺寸。
芯片上部层叠例如3层的布线层11,12,13。这3层的布线层11,12,13的每一个中,2种绝缘膜在芯片中央部和周边部分区域设置。
上述2种绝缘膜中设置在芯片中央部的一个绝缘膜14例如由有机SOG膜构成。该绝缘膜14具有多个空孔,其介电率k小于3,例如设为2.2~2.7的范围的值。并且,该绝缘膜14表面上埋置形成例如Cu构成的多个金属布线15。
芯片周边部设置的另一绝缘膜16例如由通过等离子体CVD法形成的SiN膜构成。该绝缘膜16与有机SOG膜构成的那个绝缘膜14相比,介电率k高,但机械强度优越。并且,该绝缘膜16表面上埋置形成例如Cu构成的多个焊盘17。
上述布线层11,12,13上部分别形成由SiN、SiCN、SiCO等之一材料构成的阻止膜18。上述阻止膜18防止Cu向其他布线层扩散。
另外,上述布线层11,12,13上形成的焊盘17经布线层12,13上形成的通路布线19把对应的彼此之间电连接起来。
最上层的布线层13上形成例如SiN膜/TEO-SiO2膜/SiN膜构成的3层结构的钝化膜20。并且,该钝化膜20的与上述焊盘17对应的位置上开出焊接用的开口部21。
图4A和4B所示的LSI芯片中,多个布线层11,12,13在表面具有形成了金属布线15和焊盘17的绝缘膜,各绝缘膜由设置在芯片中央部的一个绝缘膜14和设置在芯片周边部的另一绝缘膜16构成。
这里各布线层11,12,13中,其表面上形成金属布线15的绝缘膜14具有多个空孔,其介电率k设为2.2~2.7的范围的低值。因此,各布线层彼此间的金属布线15之间的电容耦合度小,附随各金属布线15的寄生电容的值抑制到很低。其结果是传播过各金属布线15的信号的延迟时间被改善,LSI芯片的动作实现高速化。
另一方面,在各布线层11,12,13中,位于焊盘17周围或下面的绝缘膜16由通过等离子体CVD法形成的SiN膜构成。该绝缘膜16与有机SOG膜构成的绝缘膜14相比,机械强度优越。因此在对最上层的布线层13的焊盘17连线的焊接工序和封装工序等时,即便对焊盘17施加机械冲击(机械压力)的情况下,绝缘膜16也难以割裂。
另外,由通过等离子体CVD法形成的SiN膜构成的绝缘膜16由于水分吸附、透水少,逃逸气体引起的膜比较容易产生破坏的焊盘附近的阻止膜18的膜破坏可受到抑制。
这样上述实施例的LSI芯片不损坏可靠性,可实现动作高速化。
上述实施例中,说明了构成各布线层的绝缘膜使用2种绝缘膜构成的情况,但其可使用2种以上的绝缘膜构成。
上述实施例中,说明了作为介电率k小于3的绝缘膜14使用有机SOG膜的情况,但由于通过等离子体CVD法形成的SiN膜的介电率k比3更低,因此其可使用该SiN膜作为绝缘膜14。
图4A,4B所示的LSI芯片可经例如下面说明的制造工序来制造。
首先,如图5A所示,预先形成元件和其他布线层的晶片(衬底)30上通过旋涂法涂布把以带有OH基的SiO2为基本支架的前躯体混合在溶媒中得到的材料,成膜有机SOG(Spin On Glass)膜31。
接着如图5B所示,在氧气气氛和氮气气氛中,通过在例如1350~400℃以上的温度下实施热处理,烧结有机SOG膜31形成绝缘膜14。此时,通过引起前躯体之间的脱水聚合,形成经氧原子的SiO2的架桥,在绝缘膜14中产生多个空孔,绝缘膜14为多孔质膜。
一般地,脱水聚合在350~400℃以上的温度下引起,溶媒的挥发从200℃左右开始。多孔质的绝缘膜14的介电率k取2.2~2.7范围的值。
接着如图5C所示,通过PEP工序,上述绝缘膜14被选择刻蚀,仅各芯片中央部剩余绝缘膜14,其他部分被去除。
接着如图5D所示,通过例如等离子体CVD法在整个面上堆积SiN构成的绝缘膜16。
随后如图5E所示,通过CMP法研磨或堆积抗蚀剂后,借助刻蚀反向等方法去除绝缘膜16,直到上述绝缘膜16的上面和绝缘膜14的上面在同一面被平坦化。由此,各芯片的中央部由绝缘膜14构成,各芯片的周边部形成绝缘膜16构成的绝缘膜。
之后,如图5F所示,绝缘膜14的表面上形成金属布线15,绝缘膜16的表面上形成焊盘17。
上述金属布线15和焊盘17的具体形成方法如下所述。即,分别在绝缘膜14和绝缘膜16的表面上形成金属布线用和焊盘形成用的槽后,根据需要通过溅射法顺序形成TaN、Ta、WN等构成的阻挡金属和密封用的Cu。随后,通过电解电镀法形成Cu,接着通过CMP法研磨来平坦化。
接着如图5G所示,整个面上形成SiN、SiCN、SiCO等构成的阻止膜18。
通过上述一连串的工序形成1个布线层,通过反复进行必要次数的该一连串工序可形成多层布线层。
上述实施例中,说明了通过对有机SOG膜实施热处理并烧结产生架桥反应来形成具有多个空孔的多孔质绝缘膜14的情况,但也可在SOG膜中混入分子量大的树脂,用烧结时的热能将分子量大的树脂分解为CH4、CO2、H2、C这样的小分子量的分子,通过脱离的发泡反应产生多个空孔,形成多孔质的绝缘膜14。
另外,替代上述SOG膜,可使用聚合物材料来形成绝缘膜14。例如,涂布在溶媒中混入了本来具有空间结构的大分子量的单体(CxHy)的溶体,之后进行烧结,使溶媒挥发,可形成具有分子水平的空孔的绝缘膜14。
或者,涂布混合了具有高的热稳定生的有机树脂和具有低的热稳定生的有机树脂二者的聚合物材料,通过烧结时的热能,使低热稳定性的有机树脂相挥发,形成有空孔的绝缘膜14。
此外,涂布混入了SiO2的无机相的聚合物材料,进行烧结后,暴露于HF气氛中仅溶出SiO2相来形成空孔,这样可形成绝缘膜14。
但是,图5A~5G说明了在制造方法中成膜有机SOG膜31后,进行烧结形成绝缘膜14,接着选择刻蚀绝缘膜14,仅在各芯片的中央部剩余绝缘膜14的情况。
与此相反,变形例的制造方法中,在图5A的工序中,有机SOG膜31成膜后,如图6A所示,通过选择地向各芯片中央部提供能量,升温到350~400℃以上的温度,烧结该部分的有机SOG膜31来形成绝缘膜14。
接着,如图6B所示,未提供能量的部分的有机SOG膜31被有机溶媒溶解,仅各芯片中央部剩余绝缘膜14。之后的工序与图5D~5G的情况相同,省略说明。
上述能量可通过例如激光照射、电子射线照射、分子射线照射提供。
接着参考图7A和7B说明本发明的第二实施例的LSI芯片。图7A和7B中,与图4A和4B对应的位置附加相同的符号,省略其说明,仅说明与图4A和4B不同的地方。
图7A和7B所示的LSI芯片也具有例如3层的布线层11,12,13。并且这3层的布线层11,12,13的每一个由有机SOG膜构成的1种绝缘膜构成,芯片中央部由多孔质的绝缘膜14a构成,芯片周边部由非多孔质的绝缘膜14b构成。
多孔质的绝缘膜14a的介电率k例如低至2.1左右,但机械强度差。另一方面,非多孔质的绝缘膜14b的介电率k高至例如2.7左右,但机械强度比绝缘膜14a优越。
这里,表面上形成金属布线15的绝缘膜14a是多孔质的绝缘膜,介电率k为低至2.1左右的值。因此各布线层彼此之间的金属布线15之间的电容耦合度小,可将附随各金属布线15的寄生电容抑制到很低。其结果是传播过各金属布线15的信号的延迟时间得以改善,实现LSI芯片的动作高速化。
另一方面,各布线层11,12,13中,焊盘17周围或下面配置的绝缘膜14b是非多孔质的绝缘膜。绝缘膜14b与绝缘膜14a相比,机械强度优越。因此,对最上层的布线层13的焊盘17连线的焊接工序和封装工序等时,即便是向焊盘17施加机械冲击的情况下,绝缘膜14b也难以割裂。
即,该实施例LSI芯片中,与图4A和4B同样,也不损坏可靠性,提高动作速度。
图7A和7B所示LSI芯片中,说明了作为构成各布线层的绝缘膜使用了2种绝缘膜的情况,但其可使用2种以上的绝缘膜构成。
图7A,7B所示的LSI芯片可经例如下面说明的制造工序来制造。
首先,如图8A所示,预先形成元件和其他布线层的晶片(衬底)30上通过旋涂法涂布把以带有OH基的SiO2为基本支架的前躯体混合在溶媒中得到的材料,成膜有机SOG膜31。
接着如图8B所示,在氧气气氛和氮气气氛中,烧结有机SOG膜31,在整个面上引起架桥反应形成绝缘膜14b。此时,该绝缘膜14b的介电率k为2.7左右的值。
接着如图8C所示,在各芯片的中央部的绝缘膜14b中选择地提供能量,通过对该部分在比前面烧结时的温度高的温度下加热促进该部分的架桥反应,形成有多个空孔的多孔质绝缘膜14a。芯片周边部上剩余非多孔质的绝缘膜14b。
上述能量可通过例如激光照射、电子射线照射、分子射线照射提供。
接着如图8D所示,形成各芯片的中央部由绝缘膜14a构成,各芯片的周边部由绝缘膜14b构成的绝缘膜。
之后,与图5F、5G的情况同样,如图8E、8F所示,绝缘膜14a的表面上形成金属布线15,绝缘膜14b的表面上形成焊盘17。
该实施例中,替代选择地对各芯片中央部的绝缘膜14b提供能量加热来促进架桥反应,在该部分形成具有多个空孔的多孔质的绝缘膜14a,可在SOG膜中混入大分子量的树脂,选择地提供能量时,把该分子量大的树脂分解为CH4、CO2、H2、C这样的小分子量的分子,通过脱离的发泡反应产生多个空孔,形成多孔质的绝缘膜14a。
上述图8A~8F的方法中,说明了通过激光照射、电子射线照射、分子射线照射选择地提供能量并加热,产生架桥反应和发泡反应,形成多孔质的绝缘膜14a的情况。
与上述方法相对,可在构成布线层的绝缘膜的表面形成布线后,从外部施加交流磁场来在布线中产生涡流,升高布线温度,仅对布线附近的绝缘膜提供热量,选择地引起架桥反应或发泡反应,把该部分的绝缘膜变为多孔质的绝缘膜。
图9A和9B表示如上述那样通过从外部施加交流磁场来形成多孔质的绝缘膜的第三实施例的LSI芯片的平面图和截面图。图9A和19B中,与图4A和4B对应的位置附加相同的符号,省略其说明,仅说明与图4A和4B不同的地方。
图9A和9B中,在烧结后的非多孔质的绝缘膜14b的表面上形成金属布线15。然后,从外部施加交流磁场,在上述各金属布线15中产生涡流,升高其温度,仅对金属布线15附近的绝缘膜提供热量,选择地引起架桥反应或发泡反应,形成多孔质的绝缘膜14a。
图10是本发明的第三实施例的LSI芯片的截面图。图10中,与图4B对应的位置附加相同的符号,省略其说明,仅说明与图4B不同的地方。
LSI芯片中形成例如3个布线层11,12,13。并且这3个布线层11,12,13中分别分区域设置2种绝缘膜。作为该2种绝缘膜,在表面形成金属布线15的区域中,设置例如介电率k为2.1左右的有机SOG膜构成的多孔质绝缘膜40a。表面上设置焊盘17的区域和形成MIM电容41的区域中,设置Al2O3(氧化铝)构成的绝缘膜40b。
MIM电容41具有由上部电极和下部电极夹住例如SiN(硅氮化物)、TaO(钽氧化物)、TiN(钛氮化物)等构成的电容绝缘膜的结构。
在表面形成金属布线15的区域中设置的绝缘膜40a是多孔质绝缘膜,介电率k为低至2.1左右的值。因此,各布线层彼此之间的金属布线15之间的电容耦合度小,附随各金属布线15的寄生电容的值抑制到很低。其结果是传播过各金属布线15的信号的延迟时间被改善,LSI芯片的动作实现高速化。
另一方面,形成焊盘17和MIM电容41的区域中设置的Al2O3构成的绝缘膜40b机械强度优越的同时,在加热时氢气释放量比较少。
因此,在对焊盘17连线的焊接工序和封装工序等时,即便对焊盘17施加机械冲击的情况下,绝缘膜40b也难以割裂。
形成MIM电容的区域中设置Al2O3构成的绝缘膜40b。因此,防止加热工序时MIM电容的电容绝缘膜暴露于氢气中,防止MIM电容的性能恶化。
上述实施例中,说明了形成MIM电容的区域中设置加热时氢气释放量比较少的绝缘膜的情况。但是,形成具有电容绝缘膜的其他元件,例如高介电体存储器的LSI芯片中,也可在形成该高介电体存储器的区域中设置Al2O3构成的绝缘膜。
说明了作为氢气释放量比较少的绝缘膜,使用Al2O3构成的绝缘膜的情况,但此外,可将例如等离子体CVD法形成的SiO2膜等用作上述绝缘膜40b。
图10中,说明的也是构成各布线层的绝缘膜由2种绝缘膜构成的情况,但其可使用2种以上的绝缘膜构成。
以上各实施例中,同一布线层中使用的不同绝缘膜不限于如上所述,根据LSI芯片内的各区域特性可区分使用适当绝缘膜。例如,作为绝缘膜,可使用多孔质/非多孔质的有机SOG、MSQ(Methyl-silsesquioxane)、HSQ(hydrogen-silsesquioxane)、SiN、SiON、SiCN、SiO2、PSG、聚合物材料基的多孔质MSX(Methyl-poly-siloxane)、多孔质PAE(poly-arylene-ether)等。
各布线层中设置不同的2种绝缘膜时,如图11A和11B所示,按筛眼状配置设置一个绝缘膜51,另一绝缘膜52按岛状配置设置在该筛眼之间。
这里,根据第一实施例说明时,例如一个绝缘膜51与具有多个空孔的介电率k为2.2~2.7的范围的值的绝缘膜14相当,另一绝缘膜52与机械强度优越的绝缘膜16相当,或者相反。
上述各实施例中,说明了作为施加机械压力的电极,在设置焊盘的LSI芯片上实施本发明的情况,但可在芯片上形成多个球电极的BGA用LSI芯片上实施。即,实施BGA用LSI芯片时的电极连接时,球电极上施加机械冲击(机械压力)。因此,形成球电极的布线层的区域上设置机械强度强的绝缘膜,例如通过等离子体CVD法形成的SiN膜等,在像形成金属布线的区域那样的不需要机械强度的布线层区域上可设置介电率低的例如有机SOG膜等的绝缘膜。
对本领域技术人员而言,显然可知道附加的优点和变形。因此,本发明在其更广义方面不限于这里所示和所描述的特定细节和代表性实施例。从而,在不背离如后附权利要求及其等价物限定的一般性的发明概念的精神或范围的情况下可进行各种改型。
Claims (2)
1.一种多层布线结构的半导体器件,其特征在于,该半导体器件包括:
设置在形成电容绝缘膜的第一区域上的第一绝缘膜;
设置在所述第一区域以外的第二区域上的第二绝缘膜;与所述第二绝缘膜相比,所述第一绝缘膜加热时氢气释放量较少。
2.根据权利要求1的半导体器件,其中所述第一绝缘膜是氧化铝膜或等离子体CVD氧化膜。
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JP2004349474A (ja) * | 2003-05-22 | 2004-12-09 | Toshiba Corp | 半導体装置とその製造方法 |
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JP4707330B2 (ja) * | 2004-03-30 | 2011-06-22 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
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JP4749133B2 (ja) * | 2004-11-30 | 2011-08-17 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
US7524755B2 (en) * | 2006-02-22 | 2009-04-28 | Chartered Semiconductor Manufacturing, Ltd. | Entire encapsulation of Cu interconnects using self-aligned CuSiN film |
JP5326202B2 (ja) | 2006-11-24 | 2013-10-30 | 富士通株式会社 | 半導体装置及びその製造方法 |
US20140069170A1 (en) * | 2007-04-19 | 2014-03-13 | Se Yeol Seo | Sensor for humidity and management system therefor |
KR100886814B1 (ko) * | 2007-04-19 | 2009-03-04 | 서세열 | 기저귀용 습도 센서 및 그 관리 시스템 |
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US20090079072A1 (en) * | 2007-09-21 | 2009-03-26 | Casio Computer Co., Ltd. | Semiconductor device having low dielectric insulating film and manufacturing method of the same |
KR100909757B1 (ko) * | 2007-10-31 | 2009-07-29 | 주식회사 하이닉스반도체 | 반도체 소자의 층간절연막 형성 방법 |
JP4666028B2 (ja) * | 2008-03-31 | 2011-04-06 | カシオ計算機株式会社 | 半導体装置 |
JP5731904B2 (ja) * | 2011-05-25 | 2015-06-10 | ルネサスエレクトロニクス株式会社 | 半導体装置及び半導体装置の製造方法 |
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2001
- 2001-09-27 JP JP2001298309A patent/JP2003100757A/ja active Pending
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2002
- 2002-09-25 TW TW091122008A patent/TW565927B/zh not_active IP Right Cessation
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Also Published As
Publication number | Publication date |
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US6563218B2 (en) | 2003-05-13 |
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KR100574728B1 (ko) | 2006-04-28 |
EP1298725A3 (en) | 2003-10-22 |
US20030201539A1 (en) | 2003-10-30 |
US6750138B2 (en) | 2004-06-15 |
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