CN100346466C - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
- Publication number
- CN100346466C CN100346466C CNB2005100528174A CN200510052817A CN100346466C CN 100346466 C CN100346466 C CN 100346466C CN B2005100528174 A CNB2005100528174 A CN B2005100528174A CN 200510052817 A CN200510052817 A CN 200510052817A CN 100346466 C CN100346466 C CN 100346466C
- Authority
- CN
- China
- Prior art keywords
- layer
- interconnection
- semiconductor device
- metal level
- dielectric constant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
Claims (8)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004053620A JP2005244031A (ja) | 2004-02-27 | 2004-02-27 | 半導体装置およびその製造方法 |
JP2004053620 | 2004-02-27 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1667812A CN1667812A (zh) | 2005-09-14 |
CN100346466C true CN100346466C (zh) | 2007-10-31 |
Family
ID=34879710
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2005100528174A Expired - Fee Related CN100346466C (zh) | 2004-02-27 | 2005-02-28 | 半导体器件及其制造方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US7388291B2 (zh) |
JP (1) | JP2005244031A (zh) |
CN (1) | CN100346466C (zh) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7361584B2 (en) * | 2004-11-04 | 2008-04-22 | International Business Machines Corporation | Detection of residual liner materials after polishing in damascene process |
US7811935B2 (en) * | 2006-03-07 | 2010-10-12 | Micron Technology, Inc. | Isolation regions and their formation |
KR100881620B1 (ko) | 2007-01-29 | 2009-02-04 | 삼성전자주식회사 | 반도체 장치 및 그 형성 방법 |
WO2009144643A1 (en) * | 2008-05-30 | 2009-12-03 | Nxp B.V. | Thermo-mechanical stress in semiconductor wafers |
CN102543671B (zh) * | 2010-12-08 | 2015-02-11 | 中国科学院微电子研究所 | 半导体晶片的制造方法 |
JP5673627B2 (ja) | 2012-08-03 | 2015-02-18 | トヨタ自動車株式会社 | 半導体装置及びその製造方法 |
US9099442B2 (en) | 2013-08-05 | 2015-08-04 | Micron Technology, Inc. | Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods |
CN106158735B (zh) * | 2015-04-21 | 2019-02-01 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件制作方法、半导体器件及电子装置 |
US10304772B2 (en) | 2017-05-19 | 2019-05-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure with resistive element |
US10366919B2 (en) * | 2017-09-20 | 2019-07-30 | Globalfoundries Inc. | Fully aligned via in ground rule region |
US10515852B2 (en) * | 2017-11-09 | 2019-12-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of semiconductor device with resistive element |
CN111293074B (zh) * | 2018-12-10 | 2022-12-02 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
CN115084000A (zh) * | 2021-03-10 | 2022-09-20 | 长鑫存储技术有限公司 | 半导体结构及半导体结构的制作方法 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5793112A (en) * | 1996-04-11 | 1998-08-11 | Mitsubishi Denki Kabushiki Kaisha | Multilevel embedded wiring system |
US6157081A (en) * | 1999-03-10 | 2000-12-05 | Advanced Micro Devices, Inc. | High-reliability damascene interconnect formation for semiconductor fabrication |
US6297557B1 (en) * | 1997-07-25 | 2001-10-02 | Philips Electronics North America Corp. | Reliable aluminum interconnect via structures |
US6323555B1 (en) * | 1998-01-28 | 2001-11-27 | Interuniversitiar Microelektronica Centrum (Imec Vzw) | Metallization structure on a fluorine-containing dielectric and a method for fabrication thereof |
CN1369112A (zh) * | 1999-06-09 | 2002-09-11 | 联合讯号公司 | 集成电路中自调准Cu扩散阻挡层的制造方法 |
JP2003051500A (ja) * | 2001-08-07 | 2003-02-21 | Toshiba Corp | 半導体装置及びその製造方法 |
US6610592B1 (en) * | 2000-04-24 | 2003-08-26 | Taiwan Semiconductor Manufacturing Company | Method for integrating low-K materials in semiconductor fabrication |
CN1466190A (zh) * | 2002-06-29 | 2004-01-07 | ����ʿ�뵼������˾ | 形成铜金属线的方法 |
Family Cites Families (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6180523B1 (en) * | 1998-10-13 | 2001-01-30 | Industrial Technology Research Institute | Copper metallization of USLI by electroless process |
US6214728B1 (en) * | 1998-11-20 | 2001-04-10 | Chartered Semiconductor Manufacturing, Ltd. | Method to encapsulate copper plug for interconnect metallization |
US6100195A (en) * | 1998-12-28 | 2000-08-08 | Chartered Semiconductor Manu. Ltd. | Passivation of copper interconnect surfaces with a passivating metal layer |
JP2001176965A (ja) | 1999-12-20 | 2001-06-29 | Nec Corp | 半導体装置及びその製造方法 |
US6368967B1 (en) * | 2000-05-04 | 2002-04-09 | Advanced Micro Devices, Inc. | Method to control mechanical stress of copper interconnect line using post-plating copper anneal |
US6376353B1 (en) * | 2000-07-03 | 2002-04-23 | Chartered Semiconductor Manufacturing Ltd. | Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects |
PT1311499E (pt) * | 2000-08-08 | 2006-07-31 | Ortho Mcneil Pharm Inc | Compostos biciclicos como ligandos do receptor h3 |
US6677680B2 (en) * | 2001-02-28 | 2004-01-13 | International Business Machines Corporation | Hybrid low-k interconnect structure comprised of 2 spin-on dielectric materials |
US6710450B2 (en) * | 2001-02-28 | 2004-03-23 | International Business Machines Corporation | Interconnect structure with precise conductor resistance and method to form same |
US6640592B2 (en) * | 2001-05-08 | 2003-11-04 | Southco, Inc. | Key operated latch with combined rotational and translational latching action |
US6537913B2 (en) * | 2001-06-29 | 2003-03-25 | Intel Corporation | Method of making a semiconductor device with aluminum capped copper interconnect pads |
US6806526B2 (en) * | 2001-08-13 | 2004-10-19 | Advanced Micro Devices, Inc. | Memory device |
KR100413828B1 (ko) * | 2001-12-13 | 2004-01-03 | 삼성전자주식회사 | 반도체 장치 및 그 형성방법 |
KR20020037326A (ko) | 2002-04-25 | 2002-05-18 | 박사룡 | 골프퍼팅용 고글 |
US6900488B1 (en) * | 2002-10-31 | 2005-05-31 | Advanced Micro Devices, Inc. | Multi-cell organic memory element and methods of operating and fabricating |
US6753247B1 (en) * | 2002-10-31 | 2004-06-22 | Advanced Micro Devices, Inc. | Method(s) facilitating formation of memory cell(s) and patterned conductive |
US6870183B2 (en) * | 2002-11-04 | 2005-03-22 | Advanced Micro Devices, Inc. | Stacked organic memory devices and methods of operating and fabricating |
US6746971B1 (en) * | 2002-12-05 | 2004-06-08 | Advanced Micro Devices, Inc. | Method of forming copper sulfide for memory cell |
US6773954B1 (en) * | 2002-12-05 | 2004-08-10 | Advanced Micro Devices, Inc. | Methods of forming passive layers in organic memory cells |
US6686263B1 (en) * | 2002-12-09 | 2004-02-03 | Advanced Micro Devices, Inc. | Selective formation of top memory electrode by electroless formation of conductive materials |
US8241701B2 (en) * | 2005-08-31 | 2012-08-14 | Lam Research Corporation | Processes and systems for engineering a barrier surface for copper deposition |
US6806579B2 (en) * | 2003-02-11 | 2004-10-19 | Infineon Technologies Ag | Robust via structure and method |
US6787458B1 (en) * | 2003-07-07 | 2004-09-07 | Advanced Micro Devices, Inc. | Polymer memory device formed in via opening |
US6977218B2 (en) * | 2003-07-17 | 2005-12-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for fabricating copper interconnects |
US7205233B2 (en) * | 2003-11-07 | 2007-04-17 | Applied Materials, Inc. | Method for forming CoWRe alloys by electroless deposition |
US20060027924A1 (en) * | 2004-08-03 | 2006-02-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metallization layers for crack prevention and reduced capacitance |
US20060046502A1 (en) * | 2004-08-27 | 2006-03-02 | Ngo Minh V | Deposition of hard-mask with minimized hillocks and bubbles |
US7232765B1 (en) * | 2004-11-12 | 2007-06-19 | Spansion Llc | Utilization of a Ta-containing cap over copper to facilitate concurrent formation of copper vias and memory element structures |
US7220642B2 (en) * | 2004-11-12 | 2007-05-22 | Spansion Llc | Protection of active layers of memory cells during processing of other elements |
JP4963349B2 (ja) * | 2005-01-14 | 2012-06-27 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US8771804B2 (en) * | 2005-08-31 | 2014-07-08 | Lam Research Corporation | Processes and systems for engineering a copper surface for selective metal deposition |
US8747960B2 (en) * | 2005-08-31 | 2014-06-10 | Lam Research Corporation | Processes and systems for engineering a silicon-type surface for selective metal deposition to form a metal silicide |
-
2004
- 2004-02-27 JP JP2004053620A patent/JP2005244031A/ja active Pending
-
2005
- 2005-02-24 US US11/063,565 patent/US7388291B2/en not_active Expired - Fee Related
- 2005-02-28 CN CNB2005100528174A patent/CN100346466C/zh not_active Expired - Fee Related
-
2008
- 2008-04-29 US US12/111,352 patent/US20080203572A1/en not_active Abandoned
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5793112A (en) * | 1996-04-11 | 1998-08-11 | Mitsubishi Denki Kabushiki Kaisha | Multilevel embedded wiring system |
US6297557B1 (en) * | 1997-07-25 | 2001-10-02 | Philips Electronics North America Corp. | Reliable aluminum interconnect via structures |
US6323555B1 (en) * | 1998-01-28 | 2001-11-27 | Interuniversitiar Microelektronica Centrum (Imec Vzw) | Metallization structure on a fluorine-containing dielectric and a method for fabrication thereof |
US6157081A (en) * | 1999-03-10 | 2000-12-05 | Advanced Micro Devices, Inc. | High-reliability damascene interconnect formation for semiconductor fabrication |
CN1369112A (zh) * | 1999-06-09 | 2002-09-11 | 联合讯号公司 | 集成电路中自调准Cu扩散阻挡层的制造方法 |
US6610592B1 (en) * | 2000-04-24 | 2003-08-26 | Taiwan Semiconductor Manufacturing Company | Method for integrating low-K materials in semiconductor fabrication |
JP2003051500A (ja) * | 2001-08-07 | 2003-02-21 | Toshiba Corp | 半導体装置及びその製造方法 |
CN1466190A (zh) * | 2002-06-29 | 2004-01-07 | ����ʿ�뵼������˾ | 形成铜金属线的方法 |
Also Published As
Publication number | Publication date |
---|---|
CN1667812A (zh) | 2005-09-14 |
JP2005244031A (ja) | 2005-09-08 |
US20050189654A1 (en) | 2005-09-01 |
US7388291B2 (en) | 2008-06-17 |
US20080203572A1 (en) | 2008-08-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN100346466C (zh) | 半导体器件及其制造方法 | |
CN1309070C (zh) | 半导体器件及其制造方法 | |
CN1139122C (zh) | 半导体器件及其制造方法 | |
TWI643291B (zh) | 形成互連之方法 | |
CN1292469C (zh) | 半导体器件及其制造方法 | |
CN2793923Y (zh) | 半导体元件 | |
CN1231960C (zh) | 能够抑制电流在焊盘里集中的半导体器件及其制造方法 | |
CN1551353A (zh) | 包括金属互连和金属电阻器的半导体器件及其制造方法 | |
CN1790702A (zh) | 改进的hdp氮化物基ild盖层 | |
CN1292477C (zh) | 半导体器件及其制造方法 | |
CN1276506C (zh) | 半导体器件及其制造方法 | |
CN1967800A (zh) | 半导体集成电路器件的制造方法 | |
CN100346468C (zh) | 半导体器件及其制造方法 | |
CN1893020A (zh) | 半导体器件及其制造方法 | |
CN1835235A (zh) | 半导体器件和mim电容器 | |
CN1815728A (zh) | 半导体器件以及其制造方法 | |
CN1591858A (zh) | 超低介电常数多孔材料的双重镶嵌集成 | |
CN1716591A (zh) | 半导体器件及其制造方法 | |
CN1267992C (zh) | 多层布线结构的半导体器件 | |
CN1685086A (zh) | 电抛光和电镀方法 | |
CN1731575A (zh) | 半导体器件及其制造方法 | |
CN1453834A (zh) | 半导体器件和制造方法以及电镀液 | |
CN1507055A (zh) | 集成电路电容器 | |
CN1198587A (zh) | 用以覆盖半导体器件上的孔的改进基层结构及其形成方法 | |
CN1134835C (zh) | 半导体器件及其制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: RENESAS ELECTRONICS CO., LTD. Free format text: FORMER OWNER: NEC CORP. Effective date: 20101119 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20101119 Address after: Kanagawa, Japan Patentee after: Renesas Electronics Corporation Address before: Kanagawa, Japan Patentee before: NEC Corp. |
|
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20071031 Termination date: 20140228 |