CN1241236C - 铁电电容器及集成半导体内存芯片的制造方法 - Google Patents
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Abstract
本案关于一种使用于集成半导体内存芯片中制造铁电电容器的方法，该铁电电容器根据堆栈原理架构，其中个别电容器模块(10，11)有一氧障碍层(4a，4b)在一下电容器电极(5a，5b)以及一导电插栓(1a，1b)之间形成。在未由对应氧障碍层(4a，4b)所覆盖之地点，未结构化之一黏着层(3)由在铁电(6a，6b)退火过程期间产生之氧气所氧化而形成在此一地点之绝缘片段，并使得铁电电容器(10，11)之下电容器电极(5a，5b)彼此电绝缘。此将使得免去绝缘层(3)之结构化步骤变成可能。更且，该层(3)充作氧气之吸气剂，而防止氧气扩散至该插栓。
Description
技术领域
本发明是关于一种在集成半导体内存芯片中制造铁电电容器的方法。此类型的制造方法被描述于DE19926501A1中。
背景技术
为了制造应用于具有一高整合密度的半导体内存中的铁电电容器，一铁电材料例如SrBi2(Ta，Nb)2O9(简称为SBT或SBTN)，Pb(Zr，Ti)O3(简称为PZT)或是Bi4Ti3O12(简称为BTO)被用来作为介电层在介于一电容器的两电极之间。电容器的电极材料是一贵重金属或贵重金属氧化物其在氧气中可耐高温。适合作为此用途的材料为Pt，Pd，Ir，Rh，Ru，RuOx，IrOx，RhOx，SrRuO3，SaSrCoOx(简称为LSCO)，HT超导体YBa2Cu3O7等等。大体而言，在电容器的结构当中，不是技术上更高要求的堆栈原则被遵守，就是根据偏移胞元原则之程序其占用一较大范围的芯片面积被遵守(参考W.Hartner et al.的”整合的铁电材料”，1999，26，197)。
如前文所述关于所引用的DE19926501A1的权利要求1，揭示一氧障碍层被需要，为了避免一传导插头的氧化，其由聚硅或钨所组成且连接底部电容器电极至一半导体电极或一金属化轨迹，在根据堆栈原则所构造的铁电电容器的实例中。一黏着层，例如Ir/IrOx组成的黏着层，在氧障碍层以及插头之间形成，该黏着层被需要为了维持低接触阻抗在插头与氧障碍层之间且为了避免可能的Ir硅化。先前的实验已经揭露，在逐步刻划电容器的组件的期间，(即各自受影响的氧障碍层，电容器的底部电极，铁电层以及顶部电极的刻划)，该黏着层从侧面被氧化在氧气环绕下的热处理期间且如此藉由插头中断底部电容电极的连接。氧障碍层仅可在氧气的扩散下保护黏着层以及插头的垂直方向，而非在水平的方向。
同样地，底部电容电极已经被发现与其下面的氧障碍层有部分重叠，此为非常重要的。此部份重叠越大，氧从侧面扩散的范围越低，如此以至于较大量的电容器起作用。这是因为黏着层以及插头的水平氧化进行较慢的缘故。因为黏着层必须由传导材料组成，所以有必要去刻划它否则黏着层可能产生一短路电路在所有芯片上的铁电电容器之间。
所有现今的可供工业用的具有铁电层的制品均根据偏移胞元原则来建造以及具有仅有几千位至一兆位的整合密度。偏移胞元原理不需要一氧障碍层。在堆栈原理中，电容器组件通常被逐步地刻划以氯蚀刻步骤。换句话说，氧障碍层，底部电容器电极，铁电层以及顶部电容器电极各自被刻划以氯蚀刻步骤。
以堆栈原理构造的铁电电容器中，一传导的氧障碍层是必需的，如前所述。Ir/IrOx是典型的用作氧障碍层的材料。举例来说，Ti，TiN，TaSiN，Ta或TaN可被用来作为传导性的黏着层关于钨或聚硅插头。因该黏着层必需为传导性的，因此必须刻划否则可能在所有电容组件产生电路上的短路电路。
美国专利5,811,181号描述一制造铁电电容器的方法，其中一含钽黏着层被沉积。
EP-A-0911871描述一Ti组成的黏着层在一依照堆栈原理形成的铁电电容器障碍金属层-由TiN组成-以及一传导插头之间形成。然而，该黏着层在铁电电容构造期间被刻划(参见该文件的图2B至2D)。
US-B-6,168,991描述在一DRAM胞元中，一由堆栈方法构造的电容器，该电容器的最下面的层，其贴近一传导插头，是一包含钽，氮化钽或一钽与氮化钽结合的电极层且其同时作为一障碍层，此外，给予一良好的接触至一重叠的介电层。此最底部的电极层包含Ta/TaN是在内存胞元的电容器的制造期间被刻划。
EP-A-0920054描述一铁电电容器被依照堆栈原理制造且具有一由TiN(举例而言)组成的黏着层介于一下层的传导插头以及一底部电极层之间。该黏着层伴随铁电电容器的重叠层在刻划入各个内存胞元期间一起被刻划并且在处理电容器期间遭受一从侧边而不欲产生的氧化，特别是在氧气氛围下铁的退火期间，黏着层被氧化的区域产生一高阻抗层(第9列，第7-17行)。因为这个缘故，此文件意欲在形成底部电容器电极的铂金属层蚀刻之前执行氧热处理，或者如果蚀刻已经发生在—确定的范围但是TiN黏着层的侧墙部分还未被覆盖之前。如此，此文中仅传达出TiN黏着层被一氧热处理氧化。然而，毫无结果关于描述仍未刻划的TiN黏着层的氧化在一为了简化在制造铁电内存胞元期间的刻划所需的方式下被引起。
发明内容
本发明的目的是设计在前言所述的集成半导体内存芯片中铁电电容的制造方法，如此可省掉黏着层的刻划且同时其比预期早产生的氧化也可被延迟。
本发明是基于对黏着层在铁退火或铁电电容组件的铁电层沉积后实行之氧中热处理程序期间被氧化的深刻体认。在本案中，实验已经显示黏着层氧化越迅速，热处理步骤持续时间越长且热处理温度越高。此实验的研究显示在氧障碍层下横向的氧化已经发生较慢。
如上说明的目的是被依照本发明的技术方案而达成。
根据本发明，黏着层不需要被刻划，因为在电容器组件之间的区域一开始产生一短路电路，首先会在铁电层被热处理期间氧化，如此扮演一电绝缘作用对象。
结果，一方面黏着层的刻划被排除了，以及另一方面，这层可当作是一氧气的吸收层。此未刻划的黏着层额外地阻绝氧气在氧障碍层下更深入的扩散。
如果，更佳地是使用TaSiN或TaN作为黏着层的材料，钽可被使用作终点讯号，例如，在一刻划铁电电容组件期间藉由氧障碍层/底部电容电极的反应性离子蚀刻。
两者择一地，蚀刻可被选择性地影响，因此黏着层的材料用作一蚀刻停止剂。此避免经由过度蚀刻到中间氧化物而造成一额外的地形升高。
根据本发明，提供一种在集成半导体内存芯片中制造铁电电容器的方法，所述铁电电容器根据堆栈原理制造，一氧障碍层在所述铁电电容器的一金属底部电容器电极以及一传导插头间形成，所述传导插头连接所述底部电容器电极至位于所述铁电电容器下方的一半导体电极或是连接至一金属化轨迹，以及一黏着层由传导性材料制成而被形成于所述插头以及所述氧障碍层间，其特征在于所述黏着层是以来刻划的形式被形成在一具有所述铁电电容器的区域中，并且该黏着层在其未被该氧障碍层所覆盖的部分被一热处理步骤氧化且因此转变成一绝缘层。
根据本发明，根据本发明的方法的用法是用以制造一集成半导体内存芯片。
附图说明
根据本发明的制造方法，目前较佳地示范实施例是参考如下图标以更详尽的解释。
图标的图形中，按类别：
图1显示一剖面图，经由一集成半导体内存切面，图标藉堆栈原理构造的铁电电容器组件的结构具有一未刻划的连续的黏着层；
图2同样地显示一剖面图，经由一集成半导体内存切面而图标一执行于铁电层沉积之后的热处理步骤，其中黏着层未覆盖的区域被氧化，以及
图3显示一详细的铁电电容器组件部分，其被显示在图2的一圆圈III中。
具体实施方式
图1中的剖面图在本案中显示两铁电电容器组件10以及11之一氧障碍层4a，4b以及，在后者之上，底部电极部分5a，5b。在氧障碍层4a，4b以及传导插头1a，1b之间，所述传导插头1a，1b用来连接所述底部电容器电极5a，5b到位于所述铁电电容器10，11下方的一半导体电极(图中未示出)或是连接至一金属化轨迹(图中未示出)，以及由钨或聚硅化物所组成一未刻划的黏着层3，其包含例如TaSiN，TaN，Ta，TiN，Ti被形成以一连续的形式，那也就是说，在一具有铁电电容器的集成半导体内存芯片之上所有的范围。黏着层3因此位于氧障碍层4a，4b，其被预期用以预防依据硅化物或钨化物插头1a，1b在铁电电容的堆栈构造的氧化，以及插头1a，1b之间，且在一中间氧化层2的所有地区之上，该氧化层2填满在传导插头1a，1b中间的地区。
必需说明的是，与其作为黏着促进剂的功能不同，黏着层3是必需的，为了维持插头1a，1b以及相关氧障碍层4a，4b之间的低接触阻抗且为了预防Ir可能的硅化。
随后，根据本发明，黏着层3维持不刻划，换句话说其不被选择性地移除未被氧障碍层4a，4b覆盖的地方。
反而，如图2所示，黏着层3恰好被氧所氧化，(参照图2中非常大的箭号)，在无论如何实行于铁电层6a，6b的热处理期间被释出。在此必需说明的是，底部铁电电极5a，5b是以一贵重金属或金属氧化物组成，其可在氧中忍受高温度。于此适当的物质例如有：Pt，Pd，Ir，Rh，Ru，RuOx，IrOx，RhOx，SrRuO3，LaSrCoOx(简称LSCO)，HAT超导体例如YBa2Cu3O7以及其它适合的材料。氧化的结果，黏着层3未被氧障碍层4a，4b覆盖的部分均转变成一氧化层13具有一电绝缘特性，因此底部铁电电极彼此间被电绝缘。
详细的视点III于图3中清楚显示黏着层3的氧化过程连续在氧障碍层4a，4b下，所以氧障碍层4a，4b的边缘与氧化区域稍微有部分重叠。
根据本发明的制造方法导致根据堆栈原理构造的具有铁电电容器的铁电半导体内存中，一方面黏着层3的刻划被省去以及，另一方面，此层可甚至被用作为氧的吸收层。未刻划的黏着层3额外地阻绝在氧障碍层4a，4b之下的氧扩散经由黏着层。
氧障碍层4a，4b以及/或底部电容器电极5a，5b在反应性离子蚀刻步骤刻划期间，例如钽可被用来作为终点讯号若是黏着层3包含TaSiN或TaN。
氧障碍层4a，4b以及/或底部电容器电极5a，5b的选择性蚀刻期间，黏着层3的未刻划的材料可被当作是一蚀刻停止剂。此避免地形的一另外的升高因为经由难以避免的过度蚀刻至中间氧化层2中。
组件符号说明
1a，1b 传导插头
2 中间氧化物
3 黏着层
4a，4b 氧障碍层
5a，5b 底部电容器电极
6a，6b 铁电层
10，11 铁电电容器
13 绝缘氧化黏着层
O2 氧气
Claims (5)
1.一种在集成半导体内存芯片中制造铁电电容器的方法，所述铁电电容器根据堆栈原理制造，一氧障碍层在所述铁电电容器的一金属底部电容器电极以及一传导插头间形成，所述传导插头连接所述底部电容器电极至位于所述铁电电容器下方的一半导体电极或是连接至一金属化轨迹，以及一黏着层由传导性材料制成而被形成于所述插头以及所述氧障碍层间，其特征在于所述黏着层是以未刻划的形式被形成在一具有所述铁电电容器的区域中，并且该黏着层在其未被该氧障碍层所覆盖的部分被一热处理步骤氧化且因此转变成一绝缘层。
2.根据权利要求1的制造方法，其中所述热处理步骤是在所述铁电电容器中铁电层沉积后进行的热处理步骤。
3.根据权利要求1或2的制造方法，其中所述黏着层包含Ta。
4.根据权利要求1的制造方法，其中所述传导插头是由聚硅或钨化物组成。
5.根据权利要求1的制造方法，其中所述黏着层的绝缘层氧化部分延伸至所述氧障碍层的边缘区域下。
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| DE10105997A DE10105997C1 (de) | 2001-02-09 | 2001-02-09 | Verfahren zur Herstellung ferroelektrischer Kondensatoren und integrierter Halbleiterspeicherbausteine |
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| CN100377357C (zh) * | 2003-10-22 | 2008-03-26 | 松下电器产业株式会社 | 半导体装置及其制造方法 |
| WO2008072827A1 (en) * | 2006-12-15 | 2008-06-19 | University Of Seoul Foundation Of Industry-Academic Cooperation | Ferroelectric material and method of forming ferroelectric layer using the same |
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| JP3476932B2 (ja) * | 1994-12-06 | 2003-12-10 | シャープ株式会社 | 強誘電体薄膜及び強誘電体薄膜被覆基板並びに強誘電体薄膜の製造方法 |
| TW345723B (en) * | 1996-07-09 | 1998-11-21 | Hitachi Ltd | Semiconductor memory and process for producing the same |
| JP3542704B2 (ja) * | 1997-10-24 | 2004-07-14 | シャープ株式会社 | 半導体メモリ素子 |
| US5930659A (en) * | 1997-12-05 | 1999-07-27 | Advanced Microdevices, Inc. | Forming minimal size spaces in integrated circuit conductive lines |
| US6313539B1 (en) * | 1997-12-24 | 2001-11-06 | Sharp Kabushiki Kaisha | Semiconductor memory device and production method of the same |
| DE19926501A1 (de) * | 1999-06-10 | 2000-12-21 | Siemens Ag | Verfahren zur Herstellung eines Halbleiterspeicherbauelements |
| US6168991B1 (en) * | 1999-06-25 | 2001-01-02 | Lucent Technologies Inc. | DRAM capacitor including Cu plug and Ta barrier and method of forming |
| US6455424B1 (en) * | 2000-08-07 | 2002-09-24 | Micron Technology, Inc. | Selective cap layers over recessed polysilicon plugs |
| JP2002076298A (ja) * | 2000-08-23 | 2002-03-15 | Matsushita Electric Ind Co Ltd | 半導体記憶装置およびその製造方法 |
| KR100391987B1 (ko) * | 2000-09-18 | 2003-07-22 | 삼성전자주식회사 | 강유전체 캐퍼시터를 갖는 반도체 장치 및 그 제조방법 |
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| Publication number | Publication date |
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| JP2004518306A (ja) | 2004-06-17 |
| WO2002065518A2 (de) | 2002-08-22 |
| KR20030078074A (ko) | 2003-10-04 |
| EP1358671A2 (de) | 2003-11-05 |
| DE10105997C1 (de) | 2002-07-25 |
| US6875652B2 (en) | 2005-04-05 |
| JP3886907B2 (ja) | 2007-02-28 |
| CN1489780A (zh) | 2004-04-14 |
| US20040185578A1 (en) | 2004-09-23 |
| KR100563783B1 (ko) | 2006-03-27 |
| WO2002065518A3 (de) | 2002-11-21 |
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