WO2002065518A3 - Verfahren zur herstellung ferroelektrischer kondensatoren und integrierter halbleiterspeicherbausteine - Google Patents

Verfahren zur herstellung ferroelektrischer kondensatoren und integrierter halbleiterspeicherbausteine Download PDF

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Publication number
WO2002065518A3
WO2002065518A3 PCT/DE2001/004790 DE0104790W WO02065518A3 WO 2002065518 A3 WO2002065518 A3 WO 2002065518A3 DE 0104790 W DE0104790 W DE 0104790W WO 02065518 A3 WO02065518 A3 WO 02065518A3
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WO
WIPO (PCT)
Prior art keywords
oxygen
ferroelectric capacitors
semiconductor memory
memory chips
integrated semiconductor
Prior art date
Application number
PCT/DE2001/004790
Other languages
English (en)
French (fr)
Other versions
WO2002065518A2 (de
Inventor
Igor Kasko
Matthias Kroenke
Thomas Mikolajick
Original Assignee
Infineon Technologies Ag
Igor Kasko
Matthias Kroenke
Thomas Mikolajick
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Igor Kasko, Matthias Kroenke, Thomas Mikolajick filed Critical Infineon Technologies Ag
Priority to KR1020037010399A priority Critical patent/KR100563783B1/ko
Priority to JP2002565350A priority patent/JP3886907B2/ja
Priority to EP01990318A priority patent/EP1358671A2/de
Publication of WO2002065518A2 publication Critical patent/WO2002065518A2/de
Publication of WO2002065518A3 publication Critical patent/WO2002065518A3/de
Priority to US10/638,594 priority patent/US6875652B2/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7687—Thin films associated with contacts of capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

Bei einem Verfahren zur Herstellung von im Stackprinzip aufgebauten ferroelektrischen Kondensatoren zur Anwendung in integrierten, Halbleiterspeicherbausteinen weisen die einzelnen Kondensatormodule (10, 11) eine Sauerstoffbarriere (4a, 4b) zwischen einer unteren Kondensatorelektrode (5a, 5b) und einem elektrisch leitenden Plug (1a, 1b) auf. Eine unstrukturierte Hafschicht (3) wird dort wo sie nicht von der jeweiligen Sauerstoffbarriere (4a, 4b) bedeckt ist, von dem Sauerstoff, der beim Temperungsvorgang des Ferroelektrikums (6a, 6b) entsteht, aufoxidiert und bildet dort isolierende Abschnitte, so dass die unteren Kondensatorelektroden (5a, 5b9 der ferroelektrischen Kondensatoren (10, 11) elektrisch voneinander isoliert sind. Dadurch entfällt der Strukturierungsschritt für die Haftschicht (3) und ausserdem kann diese Schicht (3) zum Gettern von Sauerstoff und zur Hemmung von Sauerstoffdiffusion zum Plug dienen.
PCT/DE2001/004790 2001-02-09 2001-12-18 Verfahren zur herstellung ferroelektrischer kondensatoren und integrierter halbleiterspeicherbausteine WO2002065518A2 (de)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020037010399A KR100563783B1 (ko) 2001-02-09 2001-12-18 강유전 커패시터의 제조 방법 및 집적 반도체 메모리 칩
JP2002565350A JP3886907B2 (ja) 2001-02-09 2001-12-18 強誘電性キャパシタおよび集積半導体メモリー用チップの製造方法
EP01990318A EP1358671A2 (de) 2001-02-09 2001-12-18 Verfahren zur herstellung ferroelektrischer kondensatoren und integrierter halbleiterspeicherbausteine
US10/638,594 US6875652B2 (en) 2001-02-09 2003-08-11 Method for producing ferroelectric capacitors and integrated semiconductor memory chips

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10105997.3 2001-02-09
DE10105997A DE10105997C1 (de) 2001-02-09 2001-02-09 Verfahren zur Herstellung ferroelektrischer Kondensatoren und integrierter Halbleiterspeicherbausteine

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US10/638,594 Continuation US6875652B2 (en) 2001-02-09 2003-08-11 Method for producing ferroelectric capacitors and integrated semiconductor memory chips

Publications (2)

Publication Number Publication Date
WO2002065518A2 WO2002065518A2 (de) 2002-08-22
WO2002065518A3 true WO2002065518A3 (de) 2002-11-21

Family

ID=7673463

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2001/004790 WO2002065518A2 (de) 2001-02-09 2001-12-18 Verfahren zur herstellung ferroelektrischer kondensatoren und integrierter halbleiterspeicherbausteine

Country Status (7)

Country Link
US (1) US6875652B2 (de)
EP (1) EP1358671A2 (de)
JP (1) JP3886907B2 (de)
KR (1) KR100563783B1 (de)
CN (1) CN1241236C (de)
DE (1) DE10105997C1 (de)
WO (1) WO2002065518A2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10334124A1 (de) * 2003-07-25 2005-02-17 Infineon Technologies Ag Haftung von Strukturen aus schlecht haftenden Materialien
US20050087788A1 (en) * 2003-10-22 2005-04-28 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same
WO2008072827A1 (en) * 2006-12-15 2008-06-19 University Of Seoul Foundation Of Industry-Academic Cooperation Ferroelectric material and method of forming ferroelectric layer using the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0911871A2 (de) * 1997-10-24 1999-04-28 Sharp Kabushiki Kaisha Halbleiter-Speicherbauteil mit ferroelektrischem Dünnfilm
EP0920054A1 (de) * 1996-07-09 1999-06-02 Hitachi, Ltd. Halbleiterspeicher und deren herstellungsverfahren
US5930659A (en) * 1997-12-05 1999-07-27 Advanced Microdevices, Inc. Forming minimal size spaces in integrated circuit conductive lines
DE19926501A1 (de) * 1999-06-10 2000-12-21 Siemens Ag Verfahren zur Herstellung eines Halbleiterspeicherbauelements
US6168991B1 (en) * 1999-06-25 2001-01-02 Lucent Technologies Inc. DRAM capacitor including Cu plug and Ta barrier and method of forming

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3476932B2 (ja) * 1994-12-06 2003-12-10 シャープ株式会社 強誘電体薄膜及び強誘電体薄膜被覆基板並びに強誘電体薄膜の製造方法
US6313539B1 (en) * 1997-12-24 2001-11-06 Sharp Kabushiki Kaisha Semiconductor memory device and production method of the same
US6455424B1 (en) * 2000-08-07 2002-09-24 Micron Technology, Inc. Selective cap layers over recessed polysilicon plugs
JP2002076298A (ja) * 2000-08-23 2002-03-15 Matsushita Electric Ind Co Ltd 半導体記憶装置およびその製造方法
KR100391987B1 (ko) * 2000-09-18 2003-07-22 삼성전자주식회사 강유전체 캐퍼시터를 갖는 반도체 장치 및 그 제조방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0920054A1 (de) * 1996-07-09 1999-06-02 Hitachi, Ltd. Halbleiterspeicher und deren herstellungsverfahren
EP0911871A2 (de) * 1997-10-24 1999-04-28 Sharp Kabushiki Kaisha Halbleiter-Speicherbauteil mit ferroelektrischem Dünnfilm
US5930659A (en) * 1997-12-05 1999-07-27 Advanced Microdevices, Inc. Forming minimal size spaces in integrated circuit conductive lines
DE19926501A1 (de) * 1999-06-10 2000-12-21 Siemens Ag Verfahren zur Herstellung eines Halbleiterspeicherbauelements
US6168991B1 (en) * 1999-06-25 2001-01-02 Lucent Technologies Inc. DRAM capacitor including Cu plug and Ta barrier and method of forming

Also Published As

Publication number Publication date
WO2002065518A2 (de) 2002-08-22
EP1358671A2 (de) 2003-11-05
US6875652B2 (en) 2005-04-05
DE10105997C1 (de) 2002-07-25
KR100563783B1 (ko) 2006-03-27
KR20030078074A (ko) 2003-10-04
CN1241236C (zh) 2006-02-08
US20040185578A1 (en) 2004-09-23
JP3886907B2 (ja) 2007-02-28
JP2004518306A (ja) 2004-06-17
CN1489780A (zh) 2004-04-14

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