CN1235282C - 用于提高刷新特性的半导体元件的制造方法 - Google Patents

用于提高刷新特性的半导体元件的制造方法 Download PDF

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CN1235282C
CN1235282C CNB021542406A CN02154240A CN1235282C CN 1235282 C CN1235282 C CN 1235282C CN B021542406 A CNB021542406 A CN B021542406A CN 02154240 A CN02154240 A CN 02154240A CN 1235282 C CN1235282 C CN 1235282C
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徐文植
朴性桂
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SK Hynix Inc
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Abstract

本发明提供一种半导体元件的制造方法，其为了提高刷新特性，在掩膜了存储器结点的接合部的状态下，仅在位线接合部完成硼环离子注入。该方法包括如下步骤：完成用于在半导体基板内调节门限电压(Vt)的第1离子注入的步骤；在已完成所述第1离子注入的半导体基板上形成栅电极的步骤；完成用于调节使所述栅电极作为掩膜按规定角度倾斜的门限电压的第2离子注入的步骤；完成用于在所述栅电极两侧的基板区域上形成LDD区域的第3离子注入的步骤，在此，所述第1离子注入在对门限电压调节必要的全部掺杂质浓度的0～90%范围内完成，在按0～30°的角度完成所述第2离子注入的同时分别在与栅电极垂直的两方向或四方向上完成。

Description

用于提高刷新特性的半导体元件的制造方法
技术领域
本发明涉及半导体元件的制造方法，特别是涉及能改善因设计标准减少而刷新特性降低的半导体元件的制造方法。
背景技术
如公知的那样，动态RAM(动态随机存取存储器)元件是一种存储的数据可以在必要时读取的存储元件，用起开关作用的金属氧化物半导体晶体管和电荷，即由保存数据的电容器构成的动态RAM单元等的集合进行制造。
在这样的动态RAM元件中，数据的存储就相当于在电容器中累积电荷，理想的累积在电容器中的电荷不被消耗。但是，保存在电容器中的初始电荷量有时被在金属氧化物半导体晶体管的pn结等中产生的漏泄电流消耗，其结果，有时就发生数据自然消失。
因而，动态RAM元件在各动态RAM单元中保存的数据完全消失之前，读保存的数据，必须用与其读出信息加在一起的重新初始的电荷量进行再充电的过程是必要的。将这样保存到的单元电荷进行再充电的过程称作刷新动作，只有周期性地重复该刷新动作，才能维持各动态RAM单元中存储的数据。
在此，所述刷新动作的周期与电容器形成工序有密切的关联，在通常的动态RAM制造工序中，存储器结点接触形成后，通过离子注入，调节所述刷新动作的周期。换言之，现有的动态RAM元件为了提高刷新特性，即，目的是使接合区域上的电场松弛，向暴露的源极/漏极区域中离子注入杂质。
发明内容
但是，为了利用设计标准的减少来调节辅助0.15μm单元晶体管的门限电压，需要大约～2.0E13/cm2程度的高沟道掺杂，但该情况下，伴随着LDD(轻掺杂漏区)区域浓度的增加，导致结区域的电场急剧地增加，因此，产生因辅助陷阱的隧道效应而异常结漏电增加，从而刷新时间明显减少的现象。
另一方面，为了改善所述刷新时间减少的状况，现有技术中，在沟道离子注入时，掩膜存储器结点，即与电容器接触的接合部分，附加用于沟道门限电压调节的离子注入的步骤，但该情况下，由于门限电压离子注入时和栅形成时的误定位等，显现出刷新时间和门限电压变动激烈的特性。
结果，按设计标准减少的趋势，作为现有的动态RAM制造工序，对达到了结区域上的电场松弛存在界限，因此为确保刷新特性有难度。
因而，本发明研究出了解决如上问题的办法，其目的是提供一种能改善刷新特性的半导体元件的制造方法。
用于达到如上目的的本发明的半导体元件的制造方法，包括如下步骤：完成用于在半导体基板内调节门限电压(Vt)的第1离子注入的步骤；在已完成所述第1离子注入的半导体基板上形成栅电极的步骤；在生成结构上形成感光膜图形，该感光膜图形掩蔽与电容器的存储器结点接触的基板部分；使所述感光膜图形作为掩膜，完成用于调节门限电压的、按规定角度倾斜的第2离子注入的步骤；完成用于在所述栅电极两侧的基板区域上形成LDD区域的第3离子注入的步骤。
在此，所述第1离子注入在对门限电压调节必要的全部掺杂质浓度的0～90％范围内完成，在按0～30°的角度完成所述第2离子注入的同时，分别在与栅电极垂直的两方向或四方向上完成。
根据本发明，由于仅对位线接触部完成硼环离子注入，因此，能降低存储器结点接触部上的沟道硼浓度，松弛电场，因而，能改善动态RAM元件上的刷新特性。
下面，参照对本发明的最佳实施例的以下说明，能明确如上所述的本发明的目的和另外的特征及优点。
附图说明
图1a至d是用于说明本发明的实施例涉及的半导体元件的制造方法的工序的剖面图；
图2是用于说明根据现有发明制造的半导体元件的结区域上的电场和沟道硼浓度的模拟结果图；
图3是用于说明根据本发明制造的半导体元件的结区域上的电场和沟道硼浓度的模拟结果图。
具体实施方式
以下，参照附图对本发明的最佳实施例详细地进行说明。
图1a至图1d是用于说明本发明的实施例涉及的半导体元件的制造方法的工序的剖面图，其说明如下。
参照图1a，利用公知的STI(浅槽隔离)工序，在半导体基板1的适当地方上形成限定它的活性区域的沟槽型的元件分离膜2。接着，为了调节单元晶体管的门限电压(Vt)，在所述半导体基板1的活性区域内离子注入规定的不纯物，例如硼。这时，用于所述门限电压调节的离子注入最好在对门限电压调节必要的全部掺杂质浓度的0～90％范围内进行。图中符号3示出用于单元门限电压调节的第1离子注入区域。
参照图1b，在所述半导体基板1上依次蒸镀了氧化膜、导电膜和氮化膜的状态中，利用公知的蚀刻工序作图形成所述叠层膜，在下部形成栅氧化膜4，然后，在上部形成具有用于缓冲的氮化膜6的栅电极5。
参照图1c，在所述生成物上形成感光膜图形7，该感光膜图形7掩膜存储器结点部，即与电容器的存储器结点接触的基板部分。接着，应用0～30°的倾斜，对由所述感光膜图形7不能掩膜的基板部分，更正确地说，对在后续与位线接触的接合预定区域，进行用于门限电压调节的离子注入。图中符号8示出用于单元门限电压调节的第2离子注入区域。
在此，所述倾斜离子注入如上所述使用硼(B)作为杂质，分别在与栅电极5垂直的两方向或四方向上完成，特别是，按使用于单元门限电压调节的离子注入区域的全部掺杂质浓度变为1E12～1E14/cm2的程度来完成。
参照图1d，在已除去感光膜图形的状态下，完成LDD离子注入。这时，所述LDD离子注入用覆盖层完成，以使能在存储器结点和与位线接触的基板部分的全部区域上进行。图中符号9示出LDD区域。
之后，顺次完成通过高浓度离子注入杂质形成结区域、形成位线和电容器等一系列的后续工序，完成制造本发明的半导体元件。
经过如上所述工序制造的本发明的半导体元件，由于经过倾斜离子注入，仅在与位线接合的基板区域上完成硼环离子注入，因此，能相对地减少与存储器结点接触的结区域上的沟道硼浓度，这样，能降低所述存储器结点接合部上的电场，减少因陷波电路加速隧穿而异常结漏电。其结果，刷新时间增加，即能改善刷新特性。
图2和图3是用于详细地说明根据现有技术和本发明制造的半导体元件的存储器结点结区域上的电场和沟道硼浓度的模拟结果图。
首先，看结区域上的电场，在由现有技术制造的元件中，如图2所示，预想门限电压(Vt)是～0.985V，最大电场是～0.48MV/cm，然后，预想的刷新时间(tREF)是～236ms的程度。相反，在由本发明制造的元件中，如图3所示，预想门限电压(Vt)是～0.868V，最大电场是～0.42MV/cm，然后，预想的刷新时间(tREF)是～236ms的程度。
其次，看沟道硼浓度，本发明涉及的元件的存储器结点上的沟道硼浓度与现有技术的比，具有相对低的掺杂浓度。
因而，由于本发明的半导体元件与现有的比在结区域上具有较低电场，因此就减少漏泄电流，具有提高了的刷新特性。
此外，本发明在栅形成之后，由于仅在位线接合部进行用于门限电压调节的离子注入，因此，能防止因现有技术中的用于门限电压调节的离子注入时或栅形成时的误定位而诱发刷新特性降低的情况。
并且，由于本发明将位线接合部的深度最大限度在浅度维持，形成非对称接点，因此，从图2和3就可以看出，能改善体击穿容限。
加之，由于本发明利用因位线接合部上的高沟道浓度而能量障碍的增加，而能减少沟道开路电流，因此与现有技术比门限电压的调节比较容易。
另一方面，所述的本发明的实施例中，在完成对位线接触部的离子注入之后，完成LDD离子注入，但也可以首先完成所述LDD离子注入。此外，完成对位线接触部的离子注入中，也可以不倾斜离子注入，按90°垂直地完成单一离子注入。并且，所述没记述的工序还有，在完成对位线接触部的离子注入之后，附加完成磷或砷的离子注入，从而能减少位线的电阻(Rc)。
如上所述，由于本发明在掩膜了存储器结点接触部的状态下，仅对位线接触部完成硼环离子注入，调节门限电压，因此，能降低所述存储器结点接触部的沟道硼浓度，松弛电场，这样，就能改善动态RAM元件的刷新特性，进而提高动态RAM元件的特性。
此外，本发明由于位线接合成浅非对称接点，因此，能改善体击穿容限，进一步提高元件特性。
本发明可以在不脱离其主旨的范围内作各种各样的变形实施。

Claims (8)

1.一种半导体元件的制造方法，其特征在于包括：
完成用于在半导体基板内调节门限电压(Vt)的第1离子注入的步骤；
在已完成所述第1离子注入的半导体基板上形成栅电极的步骤；
在生成结构上形成感光膜图形，该感光膜图形掩蔽与电容器的存储器结点接触的基板部分；
使所述感光膜图形作为掩膜，完成用于调节门限电压的、按规定角度倾斜的第2离子注入的步骤；以及
完成用于在所述栅电极两侧的基板区域上形成LDD区域的第3离子注入的步骤。
2.如权利要求1所述的半导体元件的制造方法，其特征在于，所述第1离子注入在对门限电压调节必要的全部掺杂质浓度的0～90％范围内完成。
3.如权利要求1所述的半导体元件的制造方法，其特征在于，所述第2离子注入按0～30°的角度完成。
4.如权利要求1或3所述的半导体元件的制造方法，其特征在于，所述第2离子注入分别在与栅电极垂直的两方向或四方向上完成。
5.如权利要求1所述的半导体元件的制造方法，其特征在于，在所述第2离子注入步骤之后，完成所述第3离子注入步骤之前，还包括离子注入磷或砷的步骤。
6.如权利要求1或3所述的半导体元件的制造方法，其特征在于，所述第2离子注入步骤中，全部掺杂质浓度是1E12～1E14/cm2。
7.如权利要求1所述的半导体元件的制造方法，其特征在于，在完成所述第3离子注入步骤之后，完成所述第2离子注入步骤。
8.如权利要求1所述的半导体元件的制造方法，其特征在于，所述第2离子注入步骤按90°垂直地单一离子注入。
CNB021542406A 2001-12-27 2002-12-27 用于提高刷新特性的半导体元件的制造方法 Expired - Fee Related CN1235282C (zh)

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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6579751B2 (en) * 1999-09-01 2003-06-17 Micron Technology, Inc. Semiconductor processing methods of forming integrated circuitry
KR100549010B1 (ko) 2004-06-17 2006-02-02 삼성전자주식회사 채널부 홀의 일 측벽에 채널 영역을 갖는 트랜지스터의형성방법들
KR100729923B1 (ko) * 2005-03-31 2007-06-18 주식회사 하이닉스반도체 스텝 ｓｔｉ 프로파일을 이용한 낸드 플래쉬 메모리 소자의트랜지스터 형성방법
US7705387B2 (en) * 2006-09-28 2010-04-27 Sandisk Corporation Non-volatile memory with local boosting control implant
US7977186B2 (en) * 2006-09-28 2011-07-12 Sandisk Corporation Providing local boosting control implant for non-volatile memory
KR102707534B1 (ko) * 2016-12-02 2024-09-20 삼성전자주식회사 반도체 메모리 소자
CN111384144B (zh) * 2018-12-27 2024-01-26 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5432107A (en) 1992-11-04 1995-07-11 Matsushita Electric Industrial Co., Ltd. Semiconductor fabricating method forming channel stopper with diagonally implanted ions
US5439835A (en) * 1993-11-12 1995-08-08 Micron Semiconductor, Inc. Process for DRAM incorporating a high-energy, oblique P-type implant for both field isolation and punchthrough
US5376566A (en) * 1993-11-12 1994-12-27 Micron Semiconductor, Inc. N-channel field effect transistor having an oblique arsenic implant for lowered series resistance
US5409848A (en) * 1994-03-31 1995-04-25 Vlsi Technology, Inc. Angled lateral pocket implants on p-type semiconductor devices
US5593907A (en) 1995-03-08 1997-01-14 Advanced Micro Devices Large tilt angle boron implant methodology for reducing subthreshold current in NMOS integrated circuit devices
JP2787908B2 (ja) * 1995-12-25 1998-08-20 日本電気株式会社 半導体装置の製造方法
US5811338A (en) * 1996-08-09 1998-09-22 Micron Technology, Inc. Method of making an asymmetric transistor
US5773862A (en) * 1996-08-27 1998-06-30 Zycad Corporation Floating gate FGPA cell with separated select device
US5874329A (en) * 1996-12-05 1999-02-23 Lsi Logic Corporation Method for artificially-inducing reverse short-channel effects in deep sub-micron CMOS devices
US6025224A (en) * 1997-03-31 2000-02-15 Siemens Aktiengesellschaft Device with asymmetrical channel dopant profile
US6297111B1 (en) * 1997-08-20 2001-10-02 Advanced Micro Devices Self-aligned channel transistor and method for making same
JPH11146467A (ja) * 1997-11-12 1999-05-28 Sony Corp リモートコントローラ、リモートコントローラの制御方法、受信装置、受信方法、制御装置、制御方法、リモートコントロールシステム、リモートコントロールシステムの制御方法、および、伝送媒体
JP3070732B2 (ja) * 1997-11-13 2000-07-31 日本電気株式会社 Ｍｏｓ半導体装置の製造方法
US6083795A (en) * 1998-02-09 2000-07-04 Taiwan Semiconductor Manufacturing Company Large angle channel threshold implant for improving reverse narrow width effect
US6030871A (en) * 1998-05-05 2000-02-29 Saifun Semiconductors Ltd. Process for producing two bit ROM cell utilizing angled implant
KR100532978B1 (ko) * 1999-01-13 2005-12-01 주식회사 하이닉스반도체 반도체소자의 제조방법
US6080630A (en) * 1999-02-03 2000-06-27 Advanced Micro Devices, Inc. Method for forming a MOS device with self-compensating VT -implants
US6346442B1 (en) * 1999-02-04 2002-02-12 Tower Semiconductor Ltd. Methods for fabricating a semiconductor chip having CMOS devices and a fieldless array
JP2001119001A (ja) 1999-10-18 2001-04-27 Hitachi Ltd 半導体集積回路装置の製造方法
KR20010068316A (ko) * 2000-01-04 2001-07-23 윤종용 모스 트랜지스터의 제조방법
US6512273B1 (en) * 2000-01-28 2003-01-28 Advanced Micro Devices, Inc. Method and structure for improving hot carrier immunity for devices with very shallow junctions
US6337262B1 (en) 2000-03-06 2002-01-08 Chartered Semiconductor Manufacturing Ltd. Self aligned T-top gate process integration
US6545904B2 (en) * 2001-03-16 2003-04-08 Micron Technology, Inc. 6f2 dram array, a dram array formed on a semiconductive substrate, a method of forming memory cells in a 6f2 dram array and a method of isolating a single row of memory cells in a 6f2 dram array

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