WO2021203888A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2021203888A1
WO2021203888A1 PCT/CN2021/079595 CN2021079595W WO2021203888A1 WO 2021203888 A1 WO2021203888 A1 WO 2021203888A1 CN 2021079595 W CN2021079595 W CN 2021079595W WO 2021203888 A1 WO2021203888 A1 WO 2021203888A1
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region
semiconductor device
trench
substrate
injection
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PCT/CN2021/079595
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English (en)
French (fr)
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刘志拯
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长鑫存储技术有限公司
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Priority to US17/310,762 priority Critical patent/US11984505B2/en
Publication of WO2021203888A1 publication Critical patent/WO2021203888A1/zh

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Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof.
  • DRAM Dynamic random access memory
  • PG gate
  • the parasitic electrons induced through the gate terminal can easily leak to the bit line contact terminal, causing data corruption in adjacent non-accessed columns.
  • the reduced word line spacing will make the "column hammer effect” more serious, especially at the bottom of the gate.
  • a main purpose of the present disclosure is to overcome at least one of the above-mentioned drawbacks of the prior art, and to provide a semiconductor device and a manufacturing method thereof.
  • a semiconductor device including:
  • the substrate includes a trench, a source region, a drain region, and a channel region.
  • the trench includes a trench sidewall and a trench bottom wall;
  • a gate oxide layer, the gate oxide layer is arranged in the trench, and the gate oxide layer includes a groove;
  • the gate electrode, the gate electrode is arranged in the groove
  • the implantation region is located on at least one side of the bottom wall of the trench, and at least part of the implantation region is closer to the drain region than the source region, so that the threshold voltage of the part of the channel region close to the implantation region is smaller than that of the part far away from the implantation region. Threshold voltage.
  • a method of manufacturing a semiconductor device including:
  • a trench is formed on the substrate, and a gate oxide layer is formed in the trench.
  • the trench includes the trench sidewall and the trench bottom wall;
  • An implantation region is formed on at least one side of the bottom wall of the trench, and at least part of the implantation region is closer to the drain region than the source region, so that the threshold voltage of the part of the channel region close to the implantation region is smaller than the threshold voltage of the part far from the implantation region .
  • the semiconductor device of the present disclosure is provided with an injection region inside or outside the groove, thereby reducing the threshold voltage of the channel region close to the injection region. Since there is a region with a relatively small threshold voltage in the channel region, this part In the channel region, it is easier to form a conduction channel, and the charge migration in the channel region here is also avoided.
  • Fig. 1 is a schematic structural diagram of a semiconductor device according to an exemplary embodiment
  • Fig. 2 is a schematic structural diagram showing a semiconductor device according to another exemplary embodiment
  • Fig. 3 is a schematic structural diagram showing a manufacturing process of an implanted region of a semiconductor device according to an exemplary embodiment
  • Fig. 4 is a schematic structural diagram showing a manufacturing process of an implanted region of a semiconductor device according to another exemplary embodiment.
  • Trench; 111 groove sidewall; 112, trench bottom wall; 113, bottom end; 12, source region; 13, drain region; 14, substrate; 20, gate oxide layer; 21, groove; 30 , Gate electrode; 40, injection area; 50, cover layer; 60, photoresist layer.
  • the semiconductor device includes a substrate 14.
  • the substrate 14 includes a trench 11, a source region 12, a drain region 13, and a channel region.
  • the trench 11 includes a trench sidewall 111 and a trench bottom wall 112; a gate oxide layer 20, the gate oxide layer 20 is arranged in the trench 11, the gate oxide layer 20 includes a groove 21; a gate electrode 30, the gate electrode 30 is arranged in the recess In the trench 21; the implantation region 40, the implantation region 40 is located on at least one side of the bottom wall 112 of the trench, and at least part of the implantation region 40 is closer to the drain region 13 than the source region 12, so that the channel region is close to the implantation region 40
  • the threshold voltage of the part is smaller than the threshold voltage of the part far away from the injection region 40.
  • the semiconductor device is provided with the injection region 40 inside or outside the groove 21, thereby reducing the threshold voltage at the position of the channel region close to the injection region 40.
  • the threshold voltage in the channel region is relatively small. In this area, the channel region in this part is easier to form a conduction channel, and the charge migration in the channel region here is also avoided, thereby solving the problem of damage to the semiconductor device due to the charge migration in the prior art.
  • the charge at the bottom of the channel region is more prone to migration problems. Therefore, an injection region 40 is provided near the bottom wall 112 of the trench to reduce the threshold voltage at the bottom of the channel region.
  • the parasitic electrons induced by the gate electrode 30 are likely to leak to the bit line contact end, that is, the connection position with the drain region 13, so it is necessary to ensure that at least part of the injection region 40 is opposite to each other.
  • the source region 12 is closer to the drain region 13, so that the threshold voltage at the bottom of the channel region close to the drain region 13 is reduced.
  • the trench 11 is a U-shaped groove, which includes a trench sidewall 111 and a trench bottom wall 112, and two ends of the trench sidewall 111 are respectively connected to the source region 12
  • the drain region 13 that is, half of the trench bottom wall 112 is close to the source region 12
  • the other half of the trench bottom wall 112 is close to the drain region 13
  • the half of the trench bottom wall 112 close to the drain region 13 is located inside and/or outside the trench bottom wall 112
  • the bottom wall 112 of the trench is an arc-shaped surface, and the sidewalls of the trench 111 are two planes, and the charge at the bottom of the channel region arranged around the trench 11 is more likely to migrate, that is, the position opposite to the sidewall 111 of the trench.
  • the threshold voltage at the bottom of the channel region can be changed by providing the implantation region 40 on the inside or outside of the bottom wall 112 of the trench.
  • the threshold voltage of the portion of the channel region close to the implanted region 40 is lower than the threshold voltage of the portion far from the implanted region 40 by 0.05V-0.1V.
  • the bottom wall 112 of the trench has a bottom end 113
  • the injection region 40 extends along the extending direction of the bottom wall 112 of the trench, and the injection region 40 is located on the side of the bottom end 113 close to the drain region 13.
  • the bottom end 113 is the lowest point of the bottom wall 112 of the trench, and the wall surfaces on both sides of it are respectively close to the source region 12 and the drain region 13, where the injection region 40 is located on the side of the wall surface close to the drain region 13, which is used to reduce
  • the bottom of the channel region is close to the threshold voltage of the drain region 13 side.
  • the extending direction of the groove 11 and the extending direction of the groove 21 are approximately the same, that is, a U-shaped groove is formed, and the injection area 40 extends along the extending direction of a certain U-shaped groove.
  • the extending direction here is mainly It means that the trend of extension is the same.
  • the length of the channel region between the source region 12 and the drain region 13 is A
  • the length of the implant region 40 is B, where 10B ⁇ A ⁇ 12B.
  • the length of the channel region is the path from the source region 12 and the drain region 13 to each other, that is, the distance from one end connected to the source region 12 to the other end connected to the drain region 13, and the length direction of the injection region 40 Consistent with the length direction of the channel region, the overall size is small, and only the threshold voltage of part of the channel region needs to be changed.
  • the gate electrodes 30 are all arranged in the groove 21, and the semiconductor device further includes: a covering layer 50, which is arranged on the gate electrode 30 and located in the groove 21.
  • the cover layer 50 is filled in the groove 21 to shield the gate electrode 30, and the tops of the source region 12, the drain region 13, the gate oxide layer 20, and the cover layer 50 are on the same plane.
  • the capping layer 50 is a titanium nitride (TiN) layer.
  • the substrate 14 is a P-type substrate, and the source region 12 and the drain region 13 are both N-type ion doped regions.
  • the substrate 14 is a P-type substrate
  • the source region 12 and the drain region 13 are two N-type regions formed by N-type ion doping
  • the channel region connects the source region 12 and the drain region 13.
  • the P-type substrate is a substrate implanted with P-type ions (boron B or gallium Ga and other group III element ions)
  • the source region 12 and the drain region 13 are two implanted N-type ions (phosphorus P or arsenic As and other group V element ions) )
  • LDD Lightly Doped Drain
  • each trench 11 is provided with a gate oxide layer 20 and a gate electrode 30, and corresponds to an injection region 40.
  • the size of the semiconductor device can be reduced by sharing the same drain region 13 with two adjacent gate electrodes 30, that is, the closer the distance between two adjacent gate electrodes 30 is, this design will make the column hammer effect problem more serious, so by The arrangement of the injection zone 40 can avoid the column hammer effect problem.
  • the corresponding two injection regions 40 are arranged oppositely, that is, close to the side of the drain region 13 located between the two source regions 12.
  • the implantation region 40 is disposed in at least one of the gate oxide layer 20 and the gate electrode 30; wherein, the implantation region 40 is a low work function region.
  • the arrangement of the low work function region can reduce the threshold voltage at the bottom of the channel region close to the drain region 13.
  • the gate oxide layer 20 and the gate electrode 30 are both centrally symmetrical structures, which are cut along the center line, one half is close to the source region 12, the other half is close to the drain region 13, and the low work function region is located close to the drain Within the other half of zone 13.
  • the low work function region when the low work function region is provided in the gate electrode 30, it may be in contact with the gate oxide layer 20.
  • the low work function region when the low work function region is provided in the gate oxide layer 20, it can be in contact with at least one of the gate electrode 30 and the bottom wall 112 of the trench.
  • the low work function region includes a low work function material, and the work function of the low work function material is less than 4.55 eV.
  • the low work function material can be directly injected into the gate oxide layer 20 and/or the gate electrode 30.
  • the work function of the low work function material is greater than 3.8 eV.
  • the work function range of the low work function material is 3.8 eV-4.55 eV, and the low work function material can be titanium/titanium nitride (Ti/TiN).
  • the implantation region 40 is disposed in the substrate 14; wherein, the implantation region 40 is the anti-doped region of the substrate 14.
  • the ions implanted in the implantation region 40 are opposite to the ions of the substrate 14, that is, when the substrate 14 is a P-type substrate (P-type ions), the implantation region 40 is implanted with N-type ions. Doping reduces the threshold voltage of the channel region.
  • the counter-doped region is in contact with the gate oxide layer 20, and the counter-doped region includes at least one of phosphorus ions and arsenic ions.
  • the anti-doped region includes P31.
  • injection regions 40 are provided on both sides of the trench bottom wall 112; wherein the injection regions 40 provided in at least one of the gate oxide layer 20 and the gate electrode 30 are low work function regions; the substrate The implantation region 40 provided in 14 is the anti-doped region of the substrate 14.
  • the low work function area includes low work function materials, the work function range of the low work function materials is 3.8eV-4.55eV, the low work function material can be titanium/titanium nitride (Ti/TiN), and the anti-doped area At least one of phosphorus ion and arsenic ion is included.
  • An embodiment of the present disclosure also provides a method for manufacturing a semiconductor device, including: providing a substrate 14; forming a trench 11 on the substrate 14, and forming a gate oxide layer 20 in the trench 11, the trench 11 including The trench sidewall 111 and the trench bottom wall 112; the gate electrode 30 is formed in the groove 21 of the gate oxide layer 20; the source region 12 and the drain region 13 are formed on the substrate 14; at least one of the trench bottom wall 112 An implantation region 40 is formed on the side, and at least a part of the implantation region 40 is closer to the drain region 13 relative to the source region 12 so that the threshold voltage of the portion of the channel region close to the implantation region 40 is smaller than the threshold voltage of the portion far from the implantation region 40.
  • the source region 12 and the drain region 13 are formed, and then the gate oxide layer 20, the gate electrode 30 and the substrate 14 are formed.
  • An implanted region 40 is formed in at least one of the two to change the threshold voltage of the channel region.
  • the manufacturing method of the semiconductor device further includes: forming a cover layer 50 on the gate oxide layer 20.
  • the cover layer 50 is filled in the groove 21 to shield the gate electrode 30, and the tops of the source region 12, the drain region 13, the gate oxide layer 20, and the cover layer 50 are on the same plane.
  • the capping layer 50 is a titanium nitride (TiN) layer.
  • the provided substrate 14 is a P-type substrate, and the source region 12 and the drain region 13 are formed by performing N-type ion doping in the P-type substrate.
  • the P-type substrate is a substrate implanted with P-type ions (boron B or gallium Ga and other group III element ions), and the source region 12 and the drain region 13 are two implanted N-type ions (phosphorus P or arsenic As and other group V element ions) ) Lightly Doped Drain (LDD for short).
  • the method of forming the implantation region 40 includes: implanting a low work function material into at least one of the gate oxide layer 20 and the gate electrode 30.
  • the work function range of the low work function material is 3.8 eV-4.55 eV
  • the low work function material may be titanium/titanium nitride (Ti/TiN).
  • the method of forming the implantation region 40 includes implanting ions opposite to the ions of the substrate 14 into the substrate 14. That is, when the substrate 14 is a P-type substrate (P-type ions), the implanted region 40 is implanted with N-type ions, which are anti-state ion implantation, and the anti-state ion includes at least one of phosphorus ions and arsenic ions. Among them, arsenic ion is P31.
  • the method of manufacturing the semiconductor device before forming the injection region 40, further includes: forming a photoresist layer 60 on the substrate 14.
  • the photoresist layer 60 shields a part of the drain region 13 to expose the middle of the drain region 13 Inject according to a preset path to form an injection region 40, the preset path intersects the middle of the drain region 13, and is inclined at the top of the drain region 13.
  • the preset path needs to avoid the photoresist layer 60, so it needs to intersect the part of the drain region 13 that is not blocked by the photoresist layer 60.
  • a photoresist layer 60 is formed.
  • the photoresist layer 60 covers the source region 12, the gate oxide layer 20,
  • the entire cover layer 50 and the part of the drain region 13, and the leaked part of the drain region 13 is used as a channel for injecting the low work function material, and the injection channel can be injected at different positions along the preset paths S1 and S2. In order to ensure the number of injections, injections are performed along multiple parallel paths.
  • a photoresist layer 60 is formed.
  • the photoresist layer 60 covers the source region 12, the gate oxide layer 20,
  • the entire cover layer 50 and the part of the drain region 13, and the leaked part of the drain region 13 is used as a channel for injecting anti-state ions, and the injection channel can be implanted at different positions along the preset paths S3 and S4. In order to ensure the number of injections, injections are performed along multiple parallel paths.

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Abstract

本公开涉及半导体技术领域，提出了一种半导体器件及其制造方法，半导体器件包括衬底、栅氧化层、栅电极以及注入区，衬底包括沟槽、源区、漏区以及沟道区，沟槽包括沟槽侧壁和沟槽底壁；栅氧化层设置在沟槽内，栅氧化层包括凹槽；栅电极设置在凹槽内；注入区位于沟槽底壁的至少一侧，且注入区的至少部分相对于源区更靠近漏区，以使沟道区靠近注入区的部分的阈值电压小于远离注入区的部分的阈值电压。本公开的半导体器件通过在凹槽的内侧或外侧设置有注入区，从而会减小沟道区靠近注入区位置处的阈值电压，由于沟道区存在阈值电压相对较小的区域，则此部分的沟道区就更容易形成导通通道，也避免了此处沟道区内的电荷迁移。

Description

半导体器件及其制造方法
交叉引用
本公开要求于2020年04月07日提交的申请号为202010264968.0、名称为“半导体器件及其制造方法”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体技术领域，尤其涉及一种半导体器件及其制造方法。
背景技术
随着电子科技的发展，电子设备变得更小更有处理能力，这也对存储装置与存储器的要求越来越高。高集成度的元件设计可以达成元件尺寸微缩以及存储容量增加的功效。
动态随机存取存储器(dynamic random access memory，DRAM)由于“列锤效应”(row hammering)问题会导致失效。列锤效应问题会造成通过栅(pass-gate，PG)的电荷迁移。在对单条列不断存取的运作环境下，其通过栅端所感应出的寄生电子很容易漏电至位线接触端，造成邻近非存取列的数据崩溃。而高度集成化的元件，字线间距缩小，会使得“列锤效应”问题更为严重，尤其是栅端的底部。
发明内容
本公开的一个主要目的在于克服上述现有技术的至少一种缺陷，提供一种半导体器件及其制造方法。
根据本公开的第一个方面，提供了一种半导体器件，包括：
衬底，衬底包括沟槽、源区、漏区以及沟道区，沟槽包括沟槽侧壁和沟槽底壁；
栅氧化层，栅氧化层设置在沟槽内，栅氧化层包括凹槽；
栅电极，栅电极设置在凹槽内；
注入区，注入区位于沟槽底壁的至少一侧，且注入区的至少部分相对于源区更靠近漏区，以使沟道区靠近注入区的部分的阈值电压小于远离注入区的部分的阈值电压。
根据本公开的第二个方面，提供了一种半导体器件的制造方法，包括：
提供衬底；
在衬底上形成沟槽，并在沟槽内形成栅氧化层，沟槽包括沟槽侧壁和沟槽底壁；
在栅氧化层的凹槽内形成栅电极；
在衬底上形成源区和漏区；
在沟槽底壁的至少一侧形成注入区，并且注入区的至少部分相对于源区更靠近漏区，以使沟道区靠近注入区的部分的阈值电压小于远离注入区的部分的阈值电压。
本公开的半导体器件通过在凹槽的内侧或外侧设置有注入区，从而会减小沟道区靠近注入区位置处的阈值电压，由于沟道区存在阈值电压相对较小的区域，则此部分的沟道区就更容易形成导通通道，也避免了此处沟道区内的电荷迁移。
附图说明
通过结合附图考虑以下对本公开的优选实施方式的详细说明，本公开的各种目标，特征和优点将变得更加显而易见。附图仅为本公开的示范性图解，并非一定是按比例绘制。在附图中，同样的附图标记始终表示相同或类似的部件。其中：
图1是根据一示例性实施方式示出的一种半导体器件的结构示意图；
图2是根据另一示例性实施方式示出的一种半导体器件的结构示意图；
图3是根据一示例性实施方式示出的一种半导体器件的注入区的制造过程的结构示意图；
图4是根据另一示例性实施方式示出的一种半导体器件的注入区的制造过程的结构示意图。
附图标记说明如下：
11、沟槽；111、槽侧壁；112、沟槽底壁；113、底端；12、源区；13、漏区；14、衬底；20、栅氧化层；21、凹槽；30、栅电极；40、注入区；50、覆盖层；60、光阻层。
具体实施方式
体现本公开特征与优点的典型实施例将在以下的说明中详细叙述。应理解的是本公开能够在不同的实施例上具有各种的变化，其皆不脱离本公开的范围，且其中的说明及附图在本质上是作说明之用，而非用以限制本公开。
在对本公开的不同示例性实施方式的下面描述中，参照附图进行，附图形成本公开的一部分，并且其中以示例方式显示了可实现本公开的多个方面的不同示例性结构，系统和步骤。应理解的是，可以使用部件，结构，示例性装置，系统和步骤的其他特定方案，并 且可在不偏离本公开范围的情况下进行结构和功能性修改。而且，虽然本说明书中可使用术语“之上”，“之间”，“之内”等来描述本公开的不同示例性特征和元件，但是这些术语用于本文中仅出于方便，例如根据附图中的示例的方向。本说明书中的任何内容都不应理解为需要结构的特定三维方向才落入本公开的范围内。
本公开的一个实施例提供了一种半导体器件，请参考图1和图2，半导体器件包括：衬底14，衬底14包括沟槽11、源区12、漏区13以及沟道区，沟槽11包括沟槽侧壁111和沟槽底壁112；栅氧化层20，栅氧化层20设置在沟槽11内，栅氧化层20包括凹槽21；栅电极30，栅电极30设置在凹槽21内；注入区40，注入区40位于沟槽底壁112的至少一侧，且注入区40的至少部分相对于源区12更靠近漏区13，以使沟道区靠近注入区40的部分的阈值电压小于远离注入区40的部分的阈值电压。
本公开一个实施例的半导体器件通过在凹槽21的内侧或外侧设置有注入区40，从而会减小沟道区靠近注入区40位置处的阈值电压，由于沟道区存在阈值电压相对较小的区域，则此部分的沟道区就更容易形成导通通道，也避免了此处沟道区内的电荷迁移，从而解决了现有技术中由于电荷迁移而导致半导体器件损坏的问题。
在一个实施例中，沟道区底部的电荷更容易出现迁移问题，故在靠近沟槽底壁112的位置处设置有注入区40，以此减小沟道区底部的阈值电压，而在对单条列不断存取的运作环境下，其通过栅电极30所感应出的寄生电子很容易漏电至位线接触端，即与漏区13的连接位置处，故需要保证注入区40的至少部分相对于源区12更靠近漏区13，从而使得沟道区底部靠近漏区13的阈值电压减小。
在一个实施例中，如图1所示，沟槽11为一个U形槽，其包括沟槽侧壁111和沟槽底壁112，沟槽侧壁111的两个端部分别连接源区12和漏区13，即沟槽底壁112的一半靠近源区12，沟槽底壁112的另一半靠近漏区13，而靠近漏区13的一半沟槽底壁112内侧，和/或外侧设置有注入区40。沟槽底壁112是弧形面，而沟槽侧壁111为两个平面，而环绕沟槽11设置的沟道区其底部的电荷更容易出现迁移，即与沟槽侧壁111相对的位置处，而通过在沟槽底壁112的内侧或外侧设置有离注入区40都可以改变沟道区底部的阈值电压。
在一个实施例中，沟道区靠近注入区40的部分的阈值电压比远离注入区40的部分的阈值电压小0.05V-0.1V。
在一个实施例中，如图1所示，沟槽底壁112具有底端113，注入区40沿沟槽底壁112的延伸方向延伸，注入区40位于底端113靠近漏区13的一侧。底端113即为沟槽底 壁112的最低点，而位于其两侧的壁面分别靠近源区12和漏区13，此处注入区40位于靠近漏区13的壁面侧，即用于减小沟道区底部靠近漏区13一侧的阈值电压。其中，沟槽11的延伸方向以及凹槽21的延伸方向大致相同，即均形成了U形槽，而注入区40则是沿着某个U形槽的延伸方向延伸，此处的延伸方向主要是表示延伸的趋势相同。
在一个实施例中，源区12和漏区13之间的沟道区的长度为A，注入区40的长度为B，其中，10B≤A≤12B。沟道区的长度就是由源区12和漏区13相互导通的路径，即由与源区12相连接的一端到与漏区13相连接的另一端的距离，而注入区40的长度方向与沟道区的长度方向相一致，其整体尺寸较小，只需改变部分的沟道区的阈值电压。
如图1所示，栅电极30均设置在凹槽21内，半导体器件还包括：覆盖层50，覆盖层50设置在栅电极30上，且位于凹槽21内。覆盖层50填充在凹槽21内以遮挡栅电极30，而源区12、漏区13、栅氧化层20以及覆盖层50的顶部在同一个平面上。覆盖层50为氮化钛(TiN)层。
在一个实施例中，衬底14为P型衬底，源区12和漏区13均为N型离子掺杂区。
在一个实施例中，衬底14为P型衬底，源区12和漏区13为两个通过N型离子掺杂形成的N型区，沟道区连接源区12和漏区13。P型衬底为注入P型离子(硼B或镓Ga等Ⅲ族元素离子)的衬底，源区12和漏区13为两个注入N型离子(磷P或砷As等Ⅴ族元素离子)的轻掺杂区(Lightly Doped Drain，简称LDD)。
在一个实施例中，栅电极30为多个，相邻两个栅电极30之间共用一个漏区13。衬底14包括多个沟槽11，而每个沟槽11内均设置有栅氧化层20、栅电极30，并对应有注入区40。通过将相邻两个栅电极30共用一个漏区13可以减小半导体器件的尺寸，即相邻两个栅电极30的距离也就越近，此设计会使得列锤效应问题更加严重，故通过注入区40的设置可以避免列锤效应问题。对于相邻两个栅电极30，其对应的两个注入区40相对设置，即靠近位于两个源区12之间的漏区13侧。
如图1所示，注入区40设置在栅氧化层20和栅电极30中的至少之一内；其中，注入区40为低功函数区。低功函数区的设置能够减小沟道区底部靠近漏区13一侧的阈值电压。
在一个实施例中，栅氧化层20和栅电极30均为中心对称结构，将其沿中心线切开，一半靠近源区12，另一半靠近漏区13，而低功函数区是位于靠近漏区13的另一半内。
在一个实施例中，当低功函数区设置在栅电极30内时，其可与栅氧化层20相接触。相应地，当低功函数区设置在栅氧化层20内时，其可与栅电极30以及沟槽底壁112的至 少一个相接触。
在一个实施例中，低功函数区包括低功函数材料，低功函数材料的功函数小于4.55eV。低功函数材料可以直接注入到栅氧化层20和/或栅电极30内。
在一个实施例中，低功函数材料的功函数大于3.8eV。低功函数材料的功函数范围为3.8eV-4.55eV，低功函数材料可以为钛/氮化钛(Ti/TiN)。
如图2所示，注入区40设置在衬底14内；其中，注入区40为衬底14的反态掺杂区。注入区40注入的离子与衬底14的离子为相反的离子，即，当衬底14为P型衬底(P型离子)时，注入区40内注入的为N型离子，通过注入反态掺杂降低沟道区的阈值电压。
在一个实施例中，反态掺杂区与栅氧化层20相接触，反态掺杂区包括磷离子和砷离子中的至少之一。其中，反态掺杂区包括P31。
在一个实施例中，沟槽底壁112的两侧均设置有注入区40；其中，栅氧化层20和栅电极30中的至少之一内设置的注入区40为低功函数区；衬底14内设置的注入区40为衬底14的反态掺杂区。其中，低功函数区包括低功函数材料，低功函数材料的功函数范围为3.8eV-4.55eV，低功函数材料可以为钛/氮化钛(Ti/TiN)，而反态掺杂区包括磷离子和砷离子中的至少之一。
本公开的一个实施例还提供了一种半导体器件的制造方法，包括：提供衬底14；在衬底14上形成沟槽11，并在沟槽11内形成栅氧化层20，沟槽11包括沟槽侧壁111和沟槽底壁112；在栅氧化层20的凹槽21内形成栅电极30；在衬底14上形成源区12和漏区13；在沟槽底壁112的至少一侧形成注入区40，并且注入区40的至少部分相对于源区12更靠近漏区13，以使沟道区靠近注入区40的部分的阈值电压小于远离注入区40的部分的阈值电压。
在一个实施例中，当将完栅氧化层20和栅电极30形成到衬底14上后，完成源区12和漏区13的成型，然后在栅氧化层20、栅电极30以及衬底14的至少之一内形成注入区40，以改变沟道区的阈值电压。
在一个实施例中，在栅氧化层20的凹槽21内形成栅电极30后，半导体器件的制造方法还包括：在栅氧化层20上形成覆盖层50。覆盖层50填充在凹槽21内以遮挡栅电极30，而源区12、漏区13、栅氧化层20以及覆盖层50的顶部在同一个平面上。覆盖层50为氮化钛(TiN)层。
在一个实施例中，提供的衬底14为P型衬底，通过在P型衬底内进行N型离子掺杂形成源区12和漏区13。P型衬底为注入P型离子(硼B或镓Ga等Ⅲ族元素离子)的衬 底，源区12和漏区13为两个注入N型离子(磷P或砷As等Ⅴ族元素离子)的轻掺杂区(Lightly Doped Drain，简称LDD)。
在一个实施例中，形成注入区40的方法包括：在栅氧化层20和栅电极30中的至少之一内注入低功函数材料。其中，低功函数材料的功函数范围为3.8eV-4.55eV，低功函数材料可以为钛/氮化钛(Ti/TiN)。
在一个实施例中，形成注入区40的方法包括：在衬底14内注入与衬底14的离子相反的离子。即当衬底14为P型衬底(P型离子)时，注入区40内注入的为N型离子，其为反态离子注入，反态离子包括磷离子和砷离子中的至少之一，其中，砷离子为P31。
在一个实施例中，在形成注入区40前，半导体器件的制备方法还包括：在衬底14上形成光阻层60，光阻层60遮挡部分的漏区13，以露出漏区13的中部；按照预设路径进行注入以形成注入区40，预设路径与漏区13的中部相交，且倾斜于漏区13的顶端。预设路径需要避开光阻层60，故需要与漏区13未受光阻层60遮挡的部分相交。
如图3所示，在形成栅氧化层20、栅电极30、覆盖层50、源区12以及漏区13后，形成光阻层60，光阻层60覆盖源区12、栅氧化层20、覆盖层50的全部以及漏区13的部分，而漏区13外漏的部分用作为注入低功函数材料的通道，而其注入通道可沿预设路径S1以及S2进行不同位置处的注入。为了保证注入数量，会沿多个相平行的路径进行注入。
如图4所示，在形成栅氧化层20、栅电极30、覆盖层50、源区12以及漏区13后，形成光阻层60，光阻层60覆盖源区12、栅氧化层20、覆盖层50的全部以及漏区13的部分，而漏区13外漏的部分用作为注入反态离子的通道，而其注入通道可沿预设路径S3以及S4进行不同位置处的注入。为了保证注入数量，会沿多个相平行的路径进行注入。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和示例实施方式仅被视为示例性的，本公开的真正范围和精神由下面的权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。

Claims (16)

  1. 一种半导体器件，包括：
    衬底(14)，所述衬底(14)包括沟槽(11)、源区(12)、漏区(13)以及沟道区，所述沟槽(11)包括沟槽侧壁(111)和沟槽底壁(112)；
    栅氧化层(20)，所述栅氧化层(20)设置在所述沟槽(11)内，所述栅氧化层(20)包括凹槽(21)；
    栅电极(30)，所述栅电极(30)设置在所述凹槽(21)内；
    注入区(40)，所述注入区(40)位于所述沟槽底壁(112)的至少一侧，且所述注入区(40)的至少部分相对于所述源区(12)更靠近所述漏区(13)，以使所述沟道区靠近所述注入区(40)的部分的阈值电压小于远离所述注入区(40)的部分的阈值电压。
  2. 根据权利要求1所述的半导体器件，所述沟槽底壁(112)具有底端(113)，所述注入区(40)沿所述沟槽底壁(112)的延伸方向延伸，所述注入区(40)位于所述底端(113)靠近所述漏区(13)的一侧。
  3. 根据权利要求1所述的半导体器件，所述源区(12)和所述漏区(13)之间的所述沟道区的长度为A，所述注入区(40)的长度为B，其中，10B≤A≤12B。
  4. 根据权利要求1所述的半导体器件，所述栅电极(30)均设置在所述凹槽(21)内，所述半导体器件还包括：
    覆盖层(50)，所述覆盖层(50)设置在所述栅电极(30)上，且位于所述凹槽(21)内。
  5. 根据权利要求1所述的半导体器件，所述衬底(14)为P型衬底，所述源区(12)和所述漏区(13)均为N型离子掺杂区。
  6. 根据权利要求1所述的半导体器件，所述栅电极(30)为多个，相邻两个所述栅电极(30)之间共用一个所述漏区(13)。
  7. 根据权利要求1至6中任一项所述的半导体器件，所述注入区(40)设置在所述栅氧化层(20)和所述栅电极(30)中的至少之一内；
    其中，所述注入区(40)为低功函数区。
  8. 根据权利要求7所述的半导体器件，所述低功函数区包括低功函数材料，所述低功函数材料的功函数小于4.55eV。
  9. 根据权利要求8所述的半导体器件，所述低功函数材料的功函数大于3.8eV。
  10. 根据权利要求1至6中任一项所述的半导体器件，所述注入区(40)设置在所述衬底(14)内；
    其中，所述注入区(40)为所述衬底(14)的反态掺杂区。
  11. 根据权利要求10所述的半导体器件，所述反态掺杂区与所述栅氧化层(20)相接触，所述反态掺杂区包括磷离子和砷离子中的至少之一。
  12. 根据权利要求1至6中任一项所述的半导体器件，所述沟槽底壁(112)的两侧均设置有所述注入区(40)；
    其中，所述栅氧化层(20)和所述栅电极(30)中的至少之一内设置的所述注入区(40)为低功函数区；所述衬底(14)内设置的所述注入区(40)为所述衬底(14)的反态掺杂区。
  13. 一种半导体器件的制造方法，包括：
    提供衬底(14)；
    在所述衬底(14)上形成沟槽(11)，并在所述沟槽(11)内形成栅氧化层(20)，所述沟槽(11)包括沟槽侧壁(111)和沟槽底壁(112)；
    在所述栅氧化层(20)的凹槽(21)内形成栅电极(30)；
    在所述衬底(14)上形成源区(12)和漏区(13)；
    在所述沟槽底壁(112)的至少一侧形成注入区(40)，并且所述注入区(40)的至少部分相对于所述源区(12)更靠近所述漏区(13)，以使沟道区靠近所述注入区(40)的部分的阈值电压小于远离所述注入区(40)的部分的阈值电压。
  14. 根据权利要求13所述的半导体器件的制造方法，形成所述注入区(40)的方法包括：
    在所述栅氧化层(20)和所述栅电极(30)中的至少之一内注入低功函数材料。
  15. 根据权利要求13所述的半导体器件的制造方法，形成所述注入区(40)的方法包括：
    在所述衬底(14)内注入与所述衬底(14)的离子相反的离子。
  16. 根据权利要求14或15所述的半导体器件的制造方法，在所述形成所述注入区(40)前，所述半导体器件的制备方法还包括：
    在所述衬底(14)上形成光阻层(60)，所述光阻层(60)遮挡部分的所述漏区(13)，以露出所述漏区(13)的中部；
    按照预设路径进行注入以形成所述注入区(40)，所述预设路径与所述漏区(13)的 中部相交，且倾斜于所述漏区(13)的顶端。
PCT/CN2021/079595 2020-04-07 2021-03-08 半导体器件及其制造方法 WO2021203888A1 (zh)

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