CN1224239A - 具有低介电常数绝缘膜的半导体器件及其制造方法 - Google Patents

具有低介电常数绝缘膜的半导体器件及其制造方法 Download PDF

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CN1224239A
CN1224239A CN99100191A CN99100191A CN1224239A CN 1224239 A CN1224239 A CN 1224239A CN 99100191 A CN99100191 A CN 99100191A CN 99100191 A CN99100191 A CN 99100191A CN 1224239 A CN1224239 A CN 1224239A
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dielectric film
film
moisture percentage
semiconductor device
dielectric
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CN1139977C (zh
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宇佐美达矢
小田典明
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Desella Advanced Technology Co
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NEC Corp
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Abstract

一种半导体器件包括形成在半导体衬底(101)上的第一绝缘膜(102)。布线图案(103)部分地形成在第一层间绝缘膜(102)上。形成第二绝缘膜(105)用来覆盖第一绝缘膜(102)和布线图案(103)。第三绝缘膜(106)形成在第二绝缘膜(105)上。在这种情况下,至少第一绝缘膜(102)的上表面部分具有低于第二绝缘膜(105)的水分含量百分比。

Description

具有低介电常数绝缘膜的半导体器件及其制造方法
本发明涉及一种半导体器件和一种制造这种半导体器件的方法。本发明特别涉及一种使用低介电常数材料的SOG(旋涂玻璃)膜作为层间绝缘膜的一部分的半导体器件及制造这种器件的方法。
通常，SOG绝缘膜是通过旋转镀膜的方法形成的。用这种SOG膜作为层间绝缘膜的一部分的技术常常被用来消除因布线图案引起的衬底表面的不均匀性。
然而，在使用硅材料的传统SOG膜中，存在以下问题。即，首先(1)因为在烘烤过程中巨大的收缩很容易产生裂缝。第二(2)因为当一旦使用旋转镀膜方法，SOG膜的厚度最多为200nm，所以需要使用多次旋转镀膜方法以形成一层较厚的SOG膜。第三(3)具有低介电常数的另一材料需要减小布线图案之间的电容，因为SOG膜的介电常数近似等于由CVD方法形成的SiO2的介电常数。由于这些理由，因此提出使用HSQ(三氧化氢硅(HSiO3/2)n)(Hydrogen Silsesquoxane)的SOG膜来解决上述问题。
图1A到1D是在一种制造方法中用SOG膜作为层间绝缘膜的一部分的半导体器件的横截面图。这种方法在“亚微米到0.5μm范围内流体氧化物的平面特性”(ULSI应用中的高级合金和互连系统，1995,pp.121-125)中被提到过的。
如图1A所示，用TEOS(四乙氧硅烷)做材料源通过等离子CVD方法在硅衬底501上形成一层二氧化硅膜502作为下层间绝缘膜。在金属布线图案503形成在层间绝缘膜502之后，用TEOS(四乙氧硅烷)做材料源通过等离子CVD方法形成一层内衬氧化膜504来覆盖金属503。
随后，如图1B所示，通过旋转镀膜HSQ来长一层HSG-SOG膜505。然后，烘烤HSG-SOG膜。
接下来，如图1C所示，用TEOS做材料源通过等离子CVD方法在HSG-SOG膜上形成一层二氧化硅膜506。
接着，如图1D所示，通过CMP(化学机械抛光)方法抛光二氧化硅膜506以便形成上层间绝缘膜507。
应该注意到，相似的制造方法在日本公开专利申请(JP-A-平7-2240460和JP-A-平8-111458)中描述过。
然而，在上面提到的层间绝缘膜的结构中存在一个问题。也就是，由于使用TEOS系统材料源在烘烤HSQ膜的过程中水分从下二氧化硅膜中挥发，致使HSQ膜的介电常数变大。在一对比实验中，在形成对比样品时，它的所有层间绝缘膜都是使用高密度等离子体通过CVD方法形成的二氧化硅。在如图1A-1D所示的普通样品和对比样品中，金属布线图案被形成成具有0.3μm的间隔。当测量两个样品的金属布线图案之间的电容时，普通样品金属布线图案之间的电容为对比样品金属布线图案之间的电容的110％。也就是，具有低介电常数膜的HSQ的介电常数大于二氧化硅的介电常数。这应该是因为在烘烤HSQ时从下膜逸出的水分进入HSQ，因此Si-H偶合减弱而Si-OH偶合增强。随Si-H偶合减弱和Si-OH偶合增强，HSQ的介电常数也增大。众所周知，当HSQ在有氧的情况下烘烤，HSQ的介电常数变大。因此，应该考虑到同样的现象会发生。
当HSQ膜被上绝缘膜覆盖时，HSQ膜相对于下绝缘膜来说并没有受到上绝缘膜很大的影响。然而，在和上绝缘膜相连的部分HSQ膜中，Si-OH偶合增大而Si-H偶合降低。
本发明的目的是为了解决上面提到的问题。因此，本发明的一个目的是提供一种半导体器件。在这种半导体器件中，通过抑制在烘烤过程中来自和低介电常数膜相连的另一绝缘膜的水分，防止象HSQ膜一类的低介电常数膜中的Si-H偶合降低。
本发明的另一个目的是提供能够防止所包含的象HSG一类的低介电常数膜的介电常数增大的半导体器件。
本发明的又一目的是提供制造上述半导体器件的方法。
为了达到本发明的目的，半导体器件包括：形成在半导体衬底上的第一绝缘膜。布线图案部分地形成在第一层间绝缘膜上。形成第二绝缘膜来覆盖第一绝缘膜和布线图案。第三绝缘膜形成在第二绝缘膜上。在这种情况下，至少第一绝缘膜的部分上表面含有百分比低于第二绝缘膜的水分。
这种半导体器件还可以包含一层用来覆盖第一绝缘膜和布线图案的内衬绝缘膜。在这种情况下，第二绝缘膜形成在内衬绝缘膜上。
第二绝缘膜的相对介电常数小于3.5，且第二绝缘膜包含Si-H偶合。
第一绝缘膜的上表面部分含有百分比低于0.02wt％的水分。在这种情况下，用包含PSG膜和BPSG膜的二氧化硅膜、氮氧化硅(SiON)、氮化硅膜和包含二氧化硅膜的氟等材料之一来生成第二绝缘膜。
最好至少是第三绝缘膜的下表面部分含有百分比低于0.02wt％的水分。用包含PSG膜和BPSG膜的二氧化硅膜、氮氧化硅(SiON)膜、氮化硅膜和含氟二氧化硅膜其中之一来形成第三绝缘膜。
为了达到本发明的另一个目的，一种制造半导体器件的方法包括以下步骤：
在半导体衬底上形成第一绝缘膜以便使至少第一绝缘膜的上表面部分含有第一水分含量百分比。
在第一绝缘膜上形成布线图案。
形成第二绝缘膜以覆盖第一绝缘膜和布线图案，第二绝缘膜具有低于第一水分含量百分比的第二水分含量百分比；并且
在第二绝缘膜上形成第三绝缘膜。
在这种情况下，用HSQ(三氧化氢硅(HSiO3/2)n)或聚硅氨烷通过旋涂方法形成第二绝缘膜。为了形成第二绝缘膜，对通过旋涂方法在预定温度预定时间下形成的第二绝缘膜进行第一热处理。因此，在第一热处理后，第二水分含量百分比是经第一热处理后的水分含量百分比。
同样，第一绝缘膜可以用SiH4气或含有Si-H偶合的有机硅烷源作为反应气体通过CVD方法形成。用SiO2、含有P或B的SiO2、Si3N4、SiON和SiOF其中之一来形成第一绝缘膜。这种方法包括在形成第二绝缘膜的步骤之前对第一绝缘膜进行第二热处理的步骤。因此，第一水分含量百分比是在第二热处理之后的水分含量百分比。
为了达到本发明的又一目的，制造半导体器件的方法包括以下步骤：
在半导体衬底上形成第一绝缘膜；
在第一绝缘膜上形成布线图案；
形成内衬绝缘膜以覆盖第一绝缘膜和布线图案以便使至少布线图案绝缘膜的上表面部分具有含有第一水分含量百分比；
在内衬绝缘膜上形成第二绝缘膜，第二绝缘膜具有低于第一水分含量百分比的第二水分含量百分比；并且
在第二绝缘膜上形成第三绝缘膜。
用SiH4气或具有Si-H偶合的有机硅烷源作为反应气体通过CVD方法形成内衬绝缘膜是最好不过的。同样，用SiO2、含有P或B的SiO2、Si3N4、SiON和SiOF其中之一形成内衬绝缘膜。
这种方法还可以包括在形成第二绝缘膜之前对内衬绝缘膜进行第三热处理过程的步骤。因此，第一水分含量百分比是经第三热处理后的水分含量百分比。
图1A-1D是在普通制造方法中半导体器件的横截面图；
图2是根据本发明第一实施例的半导体器件结构的横截面图；
图3A-3D是在一种制造方法中根据本发明第一实施例的半导体器件的横截面图；
图4是根据本发明第二实施例的半导体器件的横截面图；
图5A-5D是在一种制造方法中根据本发明第二实施例的半导体器件的横截面图。
下面，将参照附图详细描述本发明半导体器件。
图2是根据本发明第一实施例的半导体器件结构的横截面图。第一层间绝缘膜102形成在上面形成晶体管一类元件的硅衬底102上。金属布线图案103形成在第一层间绝缘膜102上。具有低介电常数的SOG膜105通过HSQ的旋涂形成在第一层间绝缘膜102上以覆盖第一层间绝缘膜102和金属布线图案103。用CVD方法形成层间绝缘膜106以覆盖SOG膜105。CVD绝缘膜106通过化学机械抛光(CMP)方法以使表面光滑。第二绝缘膜107包括低介电常数SOG膜105和形成在SOG膜105上的CVD绝缘层106。
在这种情况下，在本发明中，含有第一层间绝缘膜102的水分含量百分比，特别是第一层间绝缘膜102的上层部分的水分含量百分比被抑制为低于低介电常数SOG膜的水分含量百分比。同样，根据需要，CVD绝缘层106的水分含量百分比被抑制为低于低介电常数SOG膜105的水分百分比。
第二金属布线图案(没有示出)可以形成在第二层间绝缘膜107上。类似地，也可以形成一组或多组层间绝缘膜和金属布线图案。
连接低介电常数SOG膜105和CVD绝缘层106的第一层间绝缘膜的上部可以是用SiH4气为材料气体通过等离子体CVD方法形成的膜。也就是，该膜可以是包含PSG和BPSG的二氧化硅(SiO2)膜、氮氧化硅(SiON)膜、氮化硅(Si3N4)膜或含氟氧化硅(SiOF)膜。
同样，可以用N2O气和包含Si-H偶合的有机硅烷源比如TMS(三甲氧基硅烷)和TES(三乙氧基硅烷)，通过等离子体CVD方法形成这种膜。在这种情况下，这种膜可以是包含PSG和BPSG的二氧化硅膜。在SiH4的情况下，需要使用采用ICP(电感偶合等离子体)系统的高密度等离子体CVD方法。然而，在有机硅烷材料源的情况下，可以采用双频平行盘等离子体CVD系统。
在低介电常数SOG膜象HSG膜被烘烤后，含有低介电常数SOG105的水分含量百分比降低到大约0.02wt％。因此，需要第一层间绝缘膜102和连接SOG的CVD绝缘膜106的水分含量百分比等于或小于0.02wt％。CVD绝缘膜也符合这种条件。
在形成低介电常数膜SOG膜105之前，在形成层间绝缘膜102之后或形成金属布线图案103之后，进行热处理。热处理是在温度等于或高于400摄氏度(低介电常数SOG膜的烘烤温度)下进行的。因此，第一层间绝缘膜102的水分含量百分比被预先降低了。所以，可以得到好的结果。
可以用旋涂HSQ形成低介电常数SOG膜105。然而替代的，也可以用另一种材料形成HSG-SOG膜105。在这种情况下，SOG膜必需包含Si-H偶合且具有等于或小于3.5的相对介电常数。例如，可以用具有Si-H偶合的聚硅氨烷形成SOG膜。
下面，将详细描述根据本发明的第一实施例的半导体器件的制造方法。图3A-3D是按工艺排续的本发明第一实施例的半导体器件的横截面图。
参照图3A，作为第一层间绝缘膜的二氧化硅302形成在其上形成晶体管一类元件的硅衬底301上，其厚度大约为7000埃。在这种情况下，用SiH4、O2和氩等气体通过平行盘等离子体CVD方法形成二氧化硅。随后，淀积TiN/Al-Cu/TiN/Ti叠层导电膜并且形成金属布线图案303。
接下来，如图3B所示，用MIBK(甲基异丁酮)溶液溶解HSQ并且该溶液被旋转涂敷在第一层间绝缘膜302和金属布线图案303上。然后，这样形成的衬底放在热盘上在大约150、200和350℃下分别烘烤一分钟。接着，衬底放入垂直扩散炉并且在400℃下在氮气中烘烤1小时。因此，形成膜厚大约为4000埃的HSQ-SOG膜305。在这种情况下，下二氧化硅膜302是在用SiH4通过象平行盘设备和等离子体CVD方法形成的，它的水分含量百分比低于HSQ膜305的水分含量百分比。在烘烤之后，用TDS(热吸收谱计)测量二氧化硅膜302的水分含量百分比，并且和HSQ膜305的水分含量百分比比较。结果，发现在烘烤之后二氧化硅302的水分含量百分比大约是HSQ膜305的水分含量百分比的85％。因此，在烘烤HSQ膜时水分决没有从低二氧化硅302进入HSQ膜305。这样，烘烤可以在于燥环境进行。因此，可以形成介电常数不增大的HSQ-SOG膜305。
接下来，如图3C所示，通过平行盘等离子体CVD设备采用SiH4气在HSQ-SOG膜305上形成具有低水分含量百分比的二氧化硅膜306。这时，二氧化硅膜306象二氧化硅302一样具有的厚度为14000埃左右。
下面，如图3D所示，用CMP方法抛光二氧化硅膜306以便使在金属布线图案上保留的二氧化硅膜306大约为7000埃。这样，形成了第二层间绝缘膜(305,306)。
如上所述，形成了层间绝缘膜和金属布线图案，并且测量布线图案之间的电容。在这种情况下，布线图案之间的间距为0.3μm。为了比较，形成一比较样品以便通过高密度等离子体CVD方法在二氧化硅上形成整个第二层间绝缘膜。比较结果表明本发明的半导体器件的布线图案之间的电容比比较样品的电容小25％。
图4是根据本发明第二实施例的半导体器件结构的横截面图。参照图4，其中具有与图2中参考数字后两位数字相同的参考数字代表与图2中相同的部件。
第一实施例和第二实施例的不同点是形成一薄内衬绝缘层204来覆盖第一层间绝缘膜202和金属布线图案203。内衬绝缘层204的水分含量百分比被抑制得等于低介电常数SOG膜205的水分含量百分比。可以用上面提到形成CVD绝缘层106的相同方法形成内衬绝缘层204。当在等于或高于低介电常数SOG膜205的烘烤温度(大约400℃)下进行热处理时可以得到比较好的结果，以致在形成内衬绝缘层204之后和形成低介电常数膜SOG膜205之前绝缘层的水分含量百分比被预先地降低。
形成内衬绝缘层204作为低介电常数SOG膜205的下层膜，该下层膜具有低水分含量百分比。因此，在第二实施例中，第一层间绝缘膜202不必是具有低水分含量百分比的膜。然而，内衬绝缘层204形成的比较薄。因此，为了抑制低介电常数SOG膜205的介电常数，最好至少第一层间绝缘膜202上层部分是水分含量百分比较低的膜。通过插入绝缘层204，布线图案之间的电容变大。然而，布线图案之间的漏电流却增大了。同样，可以改善低介电常数SOG膜和金属布线图之间的不匹配。
图5A-5D是按工艺排列的根据本发明第二实施例的半导体器件的横截面图。
参照图5A，象第一实施例一样，作为第一层间绝缘膜的二氧化硅形成在其上形成晶体管一类元件的硅衬底401上，它的厚度大约为7000埃。在这种情况下，用SiH4通过ICP高密度等离子体CVD设备形成二氧化硅。接着，淀积TiN/Al-Cu/TiN/Ti薄导电膜并且制图以形成金属布线图案403。然后，用SiH4、NH3、N2O等气体通过平行盘等离子体CVD设备在第一层间绝缘膜402和金属布线图案403上形成厚度为1000埃的SiON膜。
接下来如图5B所示，用MIBK溶液溶解HSQ并且该溶液被旋转涂敷在内衬绝缘膜404上。然后，这样形成的衬底放在热盘上在大约150、200和350℃下分别烘烤一分钟。接着，衬底放入垂直扩散炉并且在400℃下在氮气中烘烤1小时。这样形成了HSQ-SOG膜405。
接下来如图5C所示，象第一实施例一样，用SiH4通过平行盘等离子体CVD设备在HSQ-SOG膜405上形成具有低水分含量百分比的厚度为14000埃的二氧化硅膜406。
在第二实施例中，用SiH4气形成的SiON膜是形成在HSQ-SOG膜下，用SiH4气形成的二氧化硅是形成HSQ-SOG膜上。SiON膜和二氧化硅膜都含有低水分含量百分比。因为这种原因，在烘烤过程中，水分并不进入HSQ膜中。因此介电常数不会变大。当测量第二实施例中的布线图案之间的电容时，电容比上面提到的对比样品的电容降低了18％。
下面，将根据本发明第三实施例描述半导体器件。在第三实施例中制造这种半导体器件的方法实质上和第二实施例中的方法相同。第三实施例和第二实施例的不同点是内衬绝缘层是用含有Si-H偶合的有机硅烷代替SiON膜来形成的二氧化硅。即在本实施例中，用TMS和N2O气体通过双频平行盘等离子体CVD设备形成内衬氧化膜。因此，在第三实施例中，也可以象第二实施例一样，实现低介电常数膜结构。
如上所述，根据本发明，当形成象HSQ-SOG膜一类的低介电常数膜时，具有低水分含量百分比的绝缘层被用作HSQ-SOG膜的下层。因此，在烘烤过程中，防止水分进入HSQ膜是可能的。因此，根据本发明，可以抑制低介电常数膜的Si-H偶合变成Si-OH偶合，致使低介电常数膜的介电常数增大。
同样，如果在低介电常数膜上形成具有低水分含量百分比的绝缘层，低介电常数膜的介电常数可以更加稳定。
再者，当用具有低水分含量百分比的内衬绝缘层覆盖金属布线图案时，除了上面提到的效果外，低介电常数膜与金属布线图案的配合可以得到改善。因此，低介电常数膜的剥落可以得到抑制。
用部分-H族被碱族替代的SiH4或有机硅烷通过高密度等离子体CVD方法形成HSQ-SOG的下层。这样形成的二氧化硅具有比较低的水分含量百分比。因此，即使在旋转涂敷HSQ后烘烤衬底，水分也不会从下层逸出，水分也不会进入HSQ-SOG膜中。

Claims (18)

1．一种半导体器件，其中包括：
形成在半导体衬底上的第一绝缘膜；
部分地形成在所述第一层间绝缘膜上的布线图案；
用来覆盖所述第一绝缘膜和所述布线图案的第二绝缘膜；和
形成在所述第二绝缘膜上的第三绝缘膜；
其中至少所述第一绝缘膜的上表面部分的水分含量百分比低于所述第二绝缘膜的水分含量百分比。
2．根据权利要求1所述的半导体器件，其特征在于还包括用来覆盖所述第一绝缘膜和所述布线图案的内衬绝缘膜，所述第二绝缘膜形成在所述内衬绝缘膜上。
3．根据权利要求1或2所述的半导体器件，其特征在于：所述第二绝缘膜具有小于3.5的相对介电常数。
4．根据权利要求1或2所述的半导体器件，其特征在于：所述绝缘膜含有Si-H偶合。
5．根据权利要求1或2所述的半导体器件，其特征在于：所述低于绝缘膜的上表面的一部分具有低于0.02wt％的水分含量百分比。
6．根据权利要求5所述的半导体器件，其特征在于：所述第二绝缘膜是用包含PSG膜和BPSG膜的二氧化硅膜、氮氧化硅(SiON)膜、氮化硅膜和包含氟二氧化硅膜中的一种形成的。
7．根据权利要求1或2所述的半导体器件，其特征在于：至少所述第三绝缘膜的下表面部分含有低于0.02wt％的水分含量百分比。
8．根据权利要求7所述的半导体器件，其特征在于：所述第三缘膜是用包含PSG膜和BPSG膜的二氧化硅膜、氮氧化硅(SiON)膜、氮化硅和含氟二氧化硅膜中的一种形成的。
9．一种制造半导体器件的方法，其特征在于包括以下步骤：
在半导体衬底上形成第一绝缘膜致使所述第一绝缘膜的至少上表面部分具有第一水分含量百分比；
在所述第一绝缘膜上形成布线图案；
形成第二绝缘膜以覆盖所述第一绝缘膜和所述布线图案，所述第二绝缘膜具有低于所述第一水分含量百分比的第二水分含量百分比；并且
在所述第二绝缘膜上形成第三绝缘膜。
10．根据权利要求9所述的方法，其特征在于：所述形成第二绝缘膜的步骤包括用三氧化氢硅(HSiO3/2)或聚硅氨烷通过旋转镀膜方法形成所述第二绝缘膜。
11．根据权利要求10所述的方法，其特征在于：所述形成第二绝缘膜的步骤包括在预定温度对通过旋转镀膜方法形成的所述第二绝缘膜进行预定时间的第一热处理，其中所述第二水分含量百分比是在所述热处理之后的水分含量百分比。
12．根据权利要求9至11中的任何一项所述的方法，其特征在于：所述形成第一绝缘膜的步骤包括用含有Si-H偶合的SiH4气或有机硅烷源作为反应源通过CVD方法形成所述第一绝缘膜。
13．根据权利要求12所述的方法，其特征在于：所述第一绝缘膜是用SiO2、含有P或B的SiO2、Si3N4、SiON、SiOF其中之一形成的。
14．根据权利要求12所述的方法，其特征在于还包括在形成所述第二绝缘膜之前对所述第一绝缘膜进行第二热处理的步骤，其中所述第一水分含量百分比是在所述第二热处理之后的水分含量百分比。
15．一种制造半导体器件的方法，其特征在于包括以下步骤：
在半导体衬底上形成第一绝缘膜；
在所述第一绝缘膜上形成布线图案；
形成内衬绝缘膜来覆盖所述第一绝缘膜和所述布线图案以便至少使所述内衬绝缘膜的上表面部分具有第一水分含量百分比；
在所述内衬绝缘膜上形成第二绝缘膜，所述第二绝缘膜具有低于所述第一水分含量百分比的第二水分含量百分比；并且
在所述第二绝缘膜上形成第三绝缘膜。
16．根据权利要求15所述的方法，其特征在于：所述形成内衬绝缘膜的步骤包括用含有Si-H偶合的SiH4气体或有机硅烷源作为反应源通过CVD方法形成所述内衬绝缘膜。
17．根据权利要求16所述的方法，其特征在于：所述内衬绝缘膜是用SiO2、含有P或B的SiO2、Si3N4、SiON、SiOF其中之一形成的。
18．根据权利要求16所述的方法，其特征在于还包括在形成所述第二绝缘膜步骤之前对所述内衬绝缘膜进行第三热处理的步骤，其中所述第一水分含量百分比是在所述第三热处理之后的水分含量百分比。
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