CN118044343A - 电路板和包括该电路板半导体封装 - Google Patents

电路板和包括该电路板半导体封装 Download PDF

Info

Publication number
CN118044343A
CN118044343A CN202280066228.3A CN202280066228A CN118044343A CN 118044343 A CN118044343 A CN 118044343A CN 202280066228 A CN202280066228 A CN 202280066228A CN 118044343 A CN118044343 A CN 118044343A
Authority
CN
China
Prior art keywords
circuit pattern
insulating layer
circuit board
layer
center line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202280066228.3A
Other languages
English (en)
Chinese (zh)
Inventor
权㫥才
南相赫
吕奇寿
刘昌佑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LG Innotek Co Ltd
Original Assignee
LG Innotek Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LG Innotek Co Ltd filed Critical LG Innotek Co Ltd
Priority claimed from PCT/KR2022/011239 external-priority patent/WO2023008966A1/ko
Publication of CN118044343A publication Critical patent/CN118044343A/zh
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/38Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/381Improvement of the adhesion between the insulating substrate and the metal by special treatment of the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226Via connections in a multilevel interconnection structure
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0235Shape of the redistribution layers
    • H01L2224/02351Shape of the redistribution layers comprising interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0236Shape of the insulating layers therebetween
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/03011Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1705Shape
    • H01L2224/17051Bump connectors having different shapes
    • H01L2224/17055Bump connectors having different shapes of their bonding interfaces

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
CN202280066228.3A 2021-07-29 2022-07-29 电路板和包括该电路板半导体封装 Pending CN118044343A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2021-0100172 2021-07-29
KR1020210100979A KR20230018921A (ko) 2021-07-30 2021-07-30 회로기판 및 이를 포함하는 패키지 기판
KR10-2021-0100979 2021-07-30
PCT/KR2022/011239 WO2023008966A1 (ko) 2021-07-29 2022-07-29 회로 기판 및 이를 포함하는 반도체 패키지

Publications (1)

Publication Number Publication Date
CN118044343A true CN118044343A (zh) 2024-05-14

Family

ID=85253116

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202280066228.3A Pending CN118044343A (zh) 2021-07-29 2022-07-29 电路板和包括该电路板半导体封装

Country Status (2)

Country Link
KR (1) KR20230018921A (ko)
CN (1) CN118044343A (ko)

Also Published As

Publication number Publication date
KR20230018921A (ko) 2023-02-07

Similar Documents

Publication Publication Date Title
JP2023530107A (ja) 回路基板
US20240120265A1 (en) Circuit board and package substrate comprising same
EP4380325A1 (en) Circuit board and semiconductor package comprising same
CN118044343A (zh) 电路板和包括该电路板半导体封装
EP4383956A1 (en) Circuit board and semiconductor package comprising same
KR20210070012A (ko) 인쇄회로기판 및 이의 제조 방법
KR20220149230A (ko) 회로 기판 및 이를 포함하는 패키지 기판
KR20230128676A (ko) 반도체 패키지
KR20230030995A (ko) 회로 기판 및 이를 포함하는 패키지 기판
KR20220148007A (ko) 회로기판 및 이를 포함하는 패키지 기판
US20240021524A1 (en) Semiconductor package
KR20220154555A (ko) 회로기판 및 이를 포함하는 패키지 기판
KR20230149984A (ko) 반도체 패키지
KR20230018236A (ko) 회로 기판, 패키지 기판 및 이의 검사 방법
KR20230023492A (ko) 회로기판 및 이를 포함하는 패키지 기판
KR20230105266A (ko) 회로 기판 및 이를 포함하는 반도체 패키지
KR20220135944A (ko) 회로기판 및 이를 포함하는 패키지 기판
KR20230065804A (ko) 회로기판 및 이를 포함하는 패키지 기판
KR20220135967A (ko) 회로기판 및 이를 포함하는 패키지 기판
CN118056474A (zh) 电路板和包括该电路板的半导体封装
KR20220138205A (ko) 회로기판 및 이를 포함하는 패키지 기판
KR20230155288A (ko) 회로 기판 및 이를 포함하는 반도체 패키지
TW202322669A (zh) 電路板及具有該電路板之半導體封裝
KR20240020913A (ko) 회로 기판 및 이를 포함하는 반도체 패키지
KR20230040817A (ko) 회로기판 및 이를 포함하는 패키지 기판

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication