CN118044343A

CN118044343A - Circuit board and semiconductor package including the same

Info

Publication number: CN118044343A
Application number: CN202280066228.3A
Authority: CN
Inventors: 权㫥才; 南相赫; 吕奇寿; 刘昌佑
Original assignee: LG Innotek Co Ltd
Current assignee: LG Innotek Co Ltd
Priority date: 2021-07-29
Filing date: 2022-07-29
Publication date: 2024-05-14
Also published as: KR20230018921A

Abstract

The circuit board according to an embodiment includes: a first insulating layer including an upper surface and a lower surface, and a first circuit pattern embedded at the upper surface of the first insulating layer, wherein the upper surface of the first insulating layer includes a portion that does not overlap the first circuit pattern in a vertical direction, and the portion of the upper surface of the first insulating layer has a step.

Description

Circuit board and semiconductor package including the same

Technical Field

Embodiments relate to a circuit board and a semiconductor package including the same.

Background

With miniaturization, weight saving, and acceleration of integration of electronic components, the line width of circuits has been miniaturized. In particular, since design rules of semiconductor chips are integrated on the nanometer scale, circuit line widths of package substrates or printed circuit boards on which the semiconductor chips are mounted have been miniaturized to several micrometers or less.

In order to increase the circuit integration of the printed circuit board, i.e., to reduce the circuit line width, various methods have been proposed. In order to prevent loss of circuit linewidth in an etching step for forming a pattern after copper plating, a semi-additive process (SAP) method and an improved semi-additive process (MSAP) have been proposed.

Then, an embedded trace substrate (embedded trace substrate, hereinafter referred to as "ETS") method for embedding a copper foil in an insulating layer in order to realize a fine circuit pattern has been used in industry. In the ETS method, instead of forming a copper foil circuit on the surface of an insulating layer, the copper foil circuit is manufactured in an embedded form in the insulating layer, so there is no circuit loss due to etching, and miniaturization of the circuit pitch is facilitated.

Meanwhile, in order to meet recent wireless data service demands, efforts are being made to develop an improved 5G (5 th generation) communication system or quasi 5G communication system. Here, the 5G communication system uses an ultra-high frequency (millimeter wave) band (6 GHz or less, 28GHz, 38GHz or higher) to achieve a high data rate.

In the 5G communication system, a plurality of substrates (e.g., an antenna substrate, an antenna feeding substrate, a transceiver substrate, and a baseband substrate) are integrated into one compact unit. Therefore, the circuit board applied to the 5G communication system must integrate various boards into one small device, and thus miniaturization of the circuit pattern is more important.

However, in the conventional circuit board, there is a problem in that it is difficult to form the line width and pitch of the trace of the circuit pattern to 10 μm or less due to the limitation of the manufacturing process.

Further, conventionally, the embedded pattern formed in the outermost layer of the ETS structure as described above cannot be subjected to AOI (automatic optical inspection) inspection immediately after the embedded pattern is formed. That is, after the process of forming the circuit pattern and the process of laminating the insulating layer are both completed, the removal of the seed layer for plating the embedded pattern is finally performed in the process of manufacturing the circuit board. This is because AOI cannot be performed since there is no distinction between the seed layer and the embedded pattern before the seed layer is removed.

In addition, when AOI is performed after removing the seed layer for plating the embedded pattern, there is a problem in that normal inspection is impossible for the side surface and the lower surface in the embedded insulating layer among the upper surface, the side surface, and the lower surface of the embedded pattern.

Disclosure of Invention

Technical problem

The embodiment provides a circuit board capable of miniaturizing a circuit pattern and a semiconductor package including the circuit board.

In addition, the embodiment provides a circuit board capable of improving adhesion between an insulating layer and a protective layer and a semiconductor package including the circuit board.

In addition, embodiments provide a circuit board and a semiconductor package including the same that can minimize skin effect on a circuit pattern.

Embodiments provide a circuit board, a semiconductor package, and an inspection method thereof, which can perform AOI even for a pattern (ETS pattern) embedded in an insulating layer.

In addition, the embodiment provides a circuit board, a semiconductor package, and an inspection method thereof, which can improve inspection accuracy and inspection efficiency of an embedded pattern of an ETS structure.

In addition, embodiments provide a circuit board including circuit patterns having different surface roughness (Ra) on an upper surface, a side surface, and a lower surface, a semiconductor package, and an inspection method thereof.

In addition, embodiments provide a circuit board, a semiconductor package, and an inspection method including the same, which can improve electrical reliability of ETS patterns having structures embedded in an insulating layer.

The technical problems to be solved by the proposed embodiments are not limited to the above technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art to which the following description deals with the proposed embodiments.

Technical proposal

The circuit board according to an embodiment includes: a first insulating layer including an upper surface and a lower surface, and a first circuit pattern embedded at the upper surface of the first insulating layer, wherein the upper surface of the first insulating layer includes a portion that does not overlap the first circuit pattern in a vertical direction, and wherein the portion of the upper surface of the first insulating layer has a step.

In addition, the portion of the first insulating layer includes a concave portion whose height decreases as it is horizontally distant from the first circuit pattern.

In addition, at least a portion of the first insulating layer is located at a position higher than an upper surface of the first circuit pattern.

In addition, a center line surface roughness (Ra) of the upper surface of the first insulating layer is different from a center line surface roughness (Ra) of the upper surface of the first circuit pattern.

In addition, a center line surface roughness (Ra) of the upper surface of the first insulating layer ranges from 0.01 μm to 0.5 μm.

In addition, the first insulating layer is an uppermost insulating layer provided at an uppermost side among a plurality of insulating layers, and wherein at least a portion of an upper surface of the first circuit pattern does not overlap with the upper surface of the first insulating layer in a vertical direction.

In addition, the first insulating layer includes a cavity overlapping the first circuit pattern in a vertical direction, wherein the cavity includes an inner surface contacting a side surface of the first circuit pattern and a bottom surface contacting a lower surface of the first circuit pattern, wherein a center line surface roughness (Ra) of an upper surface of the first insulating layer is different from a center line surface roughness (Ra) of the inner surface of the cavity and a center line surface roughness (Ra) of the bottom surface of the cavity.

In addition, a center line surface roughness (Ra) of the inner surface of the cavity is the same as a center line surface roughness (Ra) of the bottom surface of the cavity.

In addition, a center line surface roughness (Ra) of the upper surface of the first insulating layer is smaller than a center line surface roughness (Ra) of the inner surface of the cavity and a center line surface roughness (Ra) of the bottom surface of the cavity.

In addition, a center line surface roughness (Ra) of the upper surface of the first insulating layer is smaller than a center line surface roughness (Ra) of the lower surface of the first insulating layer.

In addition, the circuit board further includes: the circuit board comprises a first insulating layer, a second insulating layer and a second circuit pattern, wherein the second circuit pattern is arranged at the lower surface of the first insulating layer, and the second insulating layer is arranged at the lower surface of the first insulating layer and covers the second circuit pattern.

In addition, a center line surface roughness (Ra) of the upper surface of the first insulating layer is smaller than at least one of a center line surface roughness (Ra) of the side surface of the second circuit pattern and a center line surface roughness (Ra) of the lower surface of the second circuit pattern.

In addition, the circuit board includes a first protective layer disposed on an upper surface of the first insulating layer and having an opening overlapping at least a portion of the upper surface of the first circuit pattern in a vertical direction, and wherein the first protective layer fills the concave portion of the upper surface of the first insulating layer.

In addition, the center line surface roughness (Ra) of the lower surface of the first protective layer satisfies a range of 0.01 μm to 0.5 μm.

In addition, the first circuit pattern includes a trace, and a line width of the trace and a space between adjacent traces satisfy a range of 2 μm to 8 μm.

Meanwhile, the package substrate according to the embodiment includes: a first insulating layer including an upper surface and a lower surface, and including a cavity recessed from the upper surface toward the lower surface; a first circuit pattern disposed in the cavity of the first insulating layer; a connection portion provided on an upper surface of the first circuit pattern; a chip disposed on the connection portion; and a molding layer covering the chip, wherein the first insulating layer is an uppermost insulating layer disposed uppermost among a plurality of insulating layers, the first circuit pattern is disposed in the cavity of the first insulating layer and does not vertically overlap with an upper surface of the first insulating layer, the first insulating layer includes an inner surface of the cavity in contact with a side surface of the first circuit pattern, and a bottom surface of the cavity in contact with a lower surface of the first circuit pattern, a center line surface roughness (Ra) of the upper surface of the first insulating layer is different from a center line surface roughness (Ra) of the upper surface of the first circuit pattern, a center line surface roughness (Ra) of the inner surface of the cavity, and a center line surface roughness (Ra) of a bottom surface of the cavity, and wherein the center line surface roughness (Ra) of the upper surface of the first insulating layer is in a range of 0.01 μm to 0.5 μm.

The circuit board according to an embodiment includes: a first insulating layer, and a first circuit pattern partially embedded in the first insulating layer, wherein a side surface of the first circuit pattern has a first center line surface roughness in a range of 0.05 μm to 0.6 μm, and a lower surface of the first circuit pattern has a second center line surface roughness different from the first center line surface roughness.

In addition, the first insulating layer is an insulating layer disposed at an uppermost side among the plurality of insulating layers, and the first circuit pattern is a circuit pattern disposed at an uppermost side among the circuit patterns disposed on the plurality of insulating layers.

In addition, an upper surface of the first circuit pattern does not overlap with an upper surface of the first insulating layer in a vertical direction.

In addition, the second center line surface roughness of the lower surface of the first circuit pattern is greater than the first center line surface roughness of the side surface of the first circuit pattern.

In addition, the second center line surface roughness of the lower surface of the first circuit pattern has a range between 110% and 170% of the first center line surface roughness of the side surface of the first circuit pattern.

In addition, the upper surface of the first circuit pattern has a third center line surface roughness different from the side surface and the lower surface of the first circuit pattern.

In addition, the third centerline surface roughness is less than the first centerline surface roughness and the second centerline surface roughness.

In addition, the circuit board further includes a second circuit pattern disposed at a lower surface of the first insulating layer, and wherein a side surface and a lower surface of the second circuit pattern have the same fourth center line surface roughness.

In addition, the fourth centerline surface roughness is the same as the first centerline surface roughness.

In addition, the fourth centerline surface roughness satisfies a range between 97% and 103% of the first centerline surface roughness.

In addition, the fourth centerline surface roughness is less than the second centerline surface roughness.

In addition, the side surface of the first circuit pattern is entirely covered with the first insulating layer.

Meanwhile, the package substrate according to the embodiment includes: a first insulating layer; a first circuit pattern partially embedded in the first insulating layer; a connection portion provided on an upper surface of the first circuit pattern; a chip disposed on the connection portion; and a molding layer covering the chip, wherein a side surface of the first circuit pattern has a first center line surface roughness in a range of 0.05 μm to 0.6 μm, a lower surface of the first circuit pattern has a second center line surface roughness greater than the first center line surface roughness, and an upper surface of the first circuit pattern has a third center line surface roughness less than the first center line surface roughness and the second center line surface roughness.

In addition, the chip includes a first chip and a second chip spaced apart in a vertical or horizontal direction, and wherein the first chip includes a Central Processing Unit (CPU) and the second chip includes a Graphics Processor (GPU).

Meanwhile, a method for inspecting a circuit board according to an embodiment includes: preparing a carrier plate comprising a carrier insulating layer and a carrier metal layer arranged at the lower surface of the carrier insulating layer; forming a first dry film on a lower surface of the carrier metal layer, the first dry film including an opening overlapping the first circuit pattern forming region in a vertical direction; forming a first circuit pattern by electroplating the carrier metal layer as a seed layer to fill an opening of the first dry film; soft etching is performed on a lower surface of the first circuit pattern, and AOI (automatic optical inspection) is performed on the soft etched lower surface of the first circuit pattern.

Advantageous effects

The circuit board of the embodiment includes a first insulating layer and a first circuit pattern. The first insulating layer is an uppermost insulating layer, and the first circuit pattern is an uppermost circuit pattern disposed on an upper surface of the uppermost insulating layer. At this time, the first circuit pattern is embedded in the first insulating layer. For example, at least a portion of the upper surface of the first circuit pattern does not overlap with the upper surface of the first insulating layer in the vertical direction. At this time, the upper surface of the first insulating layer in the embodiment has a center line surface roughness (Ra) in the range of 0.01 μm to 0.5 μm. And, the center line surface roughness of the upper surface of the first insulating layer corresponds to the center line surface roughness of the sputtered layer serving as the seed layer of the first circuit pattern. At this time, if the center line surface roughness (Ra) of the seed layer of the first circuit pattern exceeds 0.6 μm and the center line surface roughness (Ra) of the upper surface of the first insulating layer correspondingly exceeds 0.6 μm, a space portion exists between the dry film and the seed layer, and thus it is difficult to refine the line width and the space of the first circuit pattern to 10 μm or less. In contrast, the embodiment allows the center line surface roughness (Ra) of the seed layer and the center line surface roughness (Ra) of the upper surface of the first insulating layer to be in the range of 0.01 μm to 0.5 μm. Accordingly, the embodiment can increase a contact area between the seed layer and the dry film, thereby enabling miniaturization of the first circuit pattern. Accordingly, in an embodiment, the line width and the interval of the first circuit pattern may be formed to 8 μm or less, and thus the circuit integration may be improved, and furthermore, the horizontal width and the vertical thickness of the circuit board may be reduced.

In addition, in the embodiment, a step is formed at the upper surface of the first insulating layer. The step may be formed by removing a portion of the upper surface of the first insulating layer when the seed layer of the first circuit pattern is removed. At this time, if the center line surface roughness (Ra) of the upper surface of the first insulating layer is 0.5 μm or less, the first circuit pattern can be miniaturized. However, it may cause a problem of adhesion to the first protective layer (such as a solder resist). Here, the embodiment forms a step such as a concave portion on the upper surface of the first insulating layer, and allows the first protective layer to fill the concave portion of the upper surface of the first insulating layer during the formation of the first protective layer. Accordingly, the embodiment can increase the contact area between the upper surface of the first insulating layer and the lower surface of the first protective layer, and thus can improve the adhesion between the first insulating layer and the first protective layer.

In addition, the embodiment can improve the electrical reliability of the circuit board due to the step of the upper surface of the first insulating layer. In particular, recent circuit boards require high integration, and therefore, the line width and pitch of the first circuit pattern become finer. In this case, an insulating layer, such as a protective layer, may not be placed on the circuit board. At this time, a space for disposing a connection portion (e.g., solder) for attaching a chip or an interposer (interposer) may not be secured on the first circuit pattern. As a result, a short problem may occur at the connection of adjacent circuit patterns due to the flow of the connection portion. In contrast, the embodiment may block the flow of the connection portion through the second portion of the upper surface of the first insulating layer. Further, the embodiment can increase the length of the upper surface of the first insulating layer by the second portion, and as a result, even if the connection portion flows, it can be prevented from contacting the adjacent circuit pattern.

In addition, the side surfaces and the lower surface of the first circuit pattern in the embodiment may have different center line surface roughness (Ra). For example, the lower surface of the first circuit pattern may have a center line surface roughness (Ra) greater than that of the side surface of the first circuit pattern. This may be due to an additional soft etch process performed during the formation process of the first circuit pattern to perform AOI on the lower surface of the first circuit pattern. Thus, embodiments may allow AOI to be performed on a lower surface of the first circuit pattern before removing the seed layer of the first circuit pattern and after forming the first circuit pattern. Therefore, the AOI accuracy of the first circuit pattern can be improved, and the inspection efficiency can be improved.

Drawings

Fig. 1a is a view for explaining a method of manufacturing a circuit board according to a comparative example.

Fig. 1b is a view for explaining a problem in a method of manufacturing a circuit board of a comparative example.

Fig. 2a is a sectional view showing a semiconductor package according to the first embodiment.

Fig. 2b is a sectional view showing a semiconductor package according to a second embodiment.

Fig. 2c is a sectional view showing a semiconductor package according to a third embodiment.

Fig. 2d is a cross-sectional view showing a semiconductor package according to a fourth embodiment.

Fig. 2e is a sectional view showing a semiconductor package according to a fifth embodiment.

Fig. 2f is a sectional view showing a semiconductor package according to a sixth embodiment.

Fig. 2g is a sectional view showing a semiconductor package according to a seventh embodiment.

Fig. 3 is a view showing a circuit board according to the first embodiment.

Fig. 4a is an enlarged view of a certain area of fig. 3.

Fig. 4b is a view showing a SAM photograph of the corresponding product in fig. 4 a.

Fig. 4c is a view for explaining a center line surface roughness (Ra) of the upper surface of the first insulating layer in fig. 4 a.

Fig. 5 is a plan view of the first circuit pattern of fig. 3.

Fig. 6 is a diagram for explaining a layer structure of the circuit pattern of fig. 3.

Fig. 7 is a view illustrating a package substrate according to an embodiment.

Fig. 8a to 8m are views showing a method of manufacturing the circuit board shown in fig. 3 in process order.

Fig. 9 is a view for explaining surface roughness of a circuit board and a first circuit pattern according to a second embodiment.

Fig. 10 is a view for explaining the surface roughness of the internal circuit pattern or the second circuit pattern of fig. 9.

Fig. 11 is a view for explaining a process of soft-etching a lower surface of a first circuit pattern according to an embodiment.

Fig. 12 to 25 are views showing a method of manufacturing the circuit board shown in fig. 9 in the process order.

Detailed Description

Hereinafter, embodiments disclosed in the present specification will be described in detail with reference to the accompanying drawings, but the same or similar parts are denoted by the same reference numerals regardless of the drawing numbers, and repetitive description thereof will be omitted. The component suffixes "module" and "portion" used in the following description are given or mixed together only in consideration of ease of writing the specification, and do not have meanings or roles distinguished from each other. In addition, in describing the embodiments disclosed in the present specification, when it is determined that detailed descriptions of related known technologies unnecessarily obscure the gist of the embodiments disclosed in the present specification, detailed descriptions thereof will be omitted. Furthermore, the drawings are only for the purpose of facilitating understanding of the embodiments disclosed in the present specification, the technical scope disclosed in the present specification is not limited by the drawings, and should be construed to include all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a similar fashion (i.e., "between …" and "directly between …", "adjacent" and "directly adjacent", etc.).

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Before explaining the embodiment of the present invention, the problem of the comparative example will be explained.

Fig. 1a is a view for explaining a method of manufacturing a circuit board according to a comparative example, and fig. 1B is a view for explaining a problem in a method of manufacturing a circuit board of a comparative example.

Referring to fig. 1a and 1b, the circuit board of the comparative example was manufactured by an Embedded Trace Substrate (ETS) method for miniaturization of circuit patterns.

In addition, the circuit pattern in the ETS method is formed by electroplating using a seed layer, not by etching a copper foil layer. For this reason, there is no change in the shape of the circuit pattern due to etching, and therefore, the circuit pattern can be miniaturized.

In the comparative example, the ETS method is performed by performing a plating process on a carrier plate or a support member to form a fine circuit pattern.

For this purpose, in the comparative example, a carrier plate or a support member was prepared.

CCLs (copper clad laminates) are commonly used for carrier plates or support members.

For example, the carrier plate or support member includes a carrier insulating layer 10 and a carrier copper foil layer 20 disposed on the carrier insulating layer 10.

In addition, the carrier insulating layer 10 and the carrier copper foil layer 20 may be implemented using CCL.

In addition, the comparative example was continued to form a circuit pattern by directly applying the dry film 40 on the carrier copper foil layer 20. Alternatively, after the additional plating layer 30 is formed on the carrier copper foil layer 20, the comparative example is continued by using the plating layer 30 to form a circuit pattern.

At this time, the plating layer 30 is generally formed by a plating process. For example, the plating layer 30 is formed by electrolytic plating or electroless plating treatment. Preferably, the plating layer 30 is typically formed by electroless copper plating.

Therefore, the upper surface (e.g., the surface in contact with the circuit pattern) of the plating layer 30 has a center line surface roughness (Ra) corresponding to the plating conditions in the plating process. For example, the upper surface of the plating layer 30 in the comparative example has a center line surface roughness (Ra) exceeding 0.6 μm. For example, the upper surface of the plating layer 30 in the comparative example has a center line surface roughness (Ra) exceeding 0.8 μm.

This is because, in order to improve the adhesion between the plating layer 30 and the dry film 40, the plating layer 30 is given a center line surface roughness (Ra) higher than a certain level.

However, if the upper surface of the plating layer 30 has a center line surface roughness (Ra) exceeding 0.6 μm as described above, it is difficult to form the width or interval of the circuit pattern to 10 μm or less.

For example, if the dry film 40 is formed on the upper surface of the plating layer 30, the lower surface of the dry film 40 includes a first portion 40-1 that contacts the upper surface of the plating layer 30 and a second portion 40-2 that is not in contact (e.g., separated or spaced apart) from the plating layer 30 due to high center line surface roughness (Ra) of the upper surface of the plating layer 30.

In addition, if a general circuit pattern having a line width or a space exceeding 10 μm is formed on the plating layer 30, a major problem (e.g., a physical reliability problem of separation of the dry film 40 from the plating layer 30) due to the non-contact second portion 40-2 may not occur. However, the circuit pattern becomes finer, so it causes a physical reliability problem due to the second portion 40-2.

For example, the dry film 40 disposed on the plating layer 30 includes a plurality of openings OR. In addition, the width w1 of the opening OR corresponds to the width of the circuit pattern, and the spacing distance w2 between the plurality of openings OR corresponds to the spacing of the circuit pattern.

In addition, if the width w1 of the openings exceeds 10 μm and the spacing distance w2 between the openings exceeds 10 μm, the width of the portion corresponding to the spacing distance w2 between the plurality of openings exceeds 10 μm, and thus, the problem of separation of the dry film 40 from the plating layer 30 does not occur.

However, as shown in (a) of fig. 1B, if the width w1 'of the opening OR is made smaller than 10 μm, OR the spacing distance w2' between the Openings (OR) becomes smaller than 10 μm, the bonding area between the dry film 40 and the plating layer 30 is reduced, and thus, adhesion between the dry film 40 and the plating layer 30 may occur due to the second portion 40-2.

For example, the fact that the spacing distance w2' between the openings is less than 10 μm means that the dry film 40 includes a region having a width of less than 10 μm in contact with the upper surface of the plating layer 30. In addition, if the width of the region of the dry film 40 in contact with the plating layer 30 is less than 10 μm, the coupling force between the dry film 40 and the plating layer 30 may be reduced due to the second portion 40-2 not in contact with the plating layer 30, and thus, the dry film 40 may include the region a separated from the plating layer 30 due to the reduced adhesion.

Therefore, in the comparative example, it is difficult to make the width of the opening or the dry film 40 or the interval distance between the openings smaller than 10 μm due to the center line surface roughness (Ra) of the plating layer 30. Thus, it is difficult to refine the width and the spacing distance of the circuit pattern to 10 μm or less.

Therefore, the embodiment allows the center line surface roughness (Ra) of the plating layer used as the seed layer in the process of plating the circuit pattern to be reduced as compared with the comparative example. Accordingly, the embodiment allows the area of the non-contact region between the dry film and the plating layer to be reduced, thereby enabling miniaturization of the circuit pattern.

However, even if the center line surface roughness (Ra) of the plating layer is too small, the adhesion between the plating layer and the dry film may be problematic. Therefore, compared to the comparative example, the embodiment allows refinement of the circuit pattern without the problem of adhesion between the plating layer and the dry film. For this reason, the embodiment allows the center line surface roughness (Ra) of the plating layer to be reduced as compared with the comparative example.

Electronic device-

Before describing the embodiments, an electronic device to which the semiconductor package of the embodiments is applied will be briefly described. The electronic device comprises a motherboard (not shown). The motherboard may be physically and/or electrically connected to various components. For example, a motherboard may be connected to the semiconductor package of the embodiment. Various semiconductor devices may be mounted on a semiconductor package.

The semiconductor devices may include active devices and/or passive devices. The active device may be a semiconductor chip in the form of an Integrated Circuit (IC), where hundreds to millions of devices are integrated in one chip. The semiconductor device may be a logic chip, a memory chip, or the like. The logic chip may be a Central Processing Unit (CPU), a Graphics Processor (GPU), or the like. For example, the logic chip may be an Application Processor (AP) chip including at least one of a Central Processing Unit (CPU), a Graphics Processor (GPU), a digital signal processor, an encryption processor, a microprocessor and a microcontroller, or an analog-to-digital converter, an Application Specific IC (ASIC), etc., or a chipset including a specific combination of those listed so far.

The memory chip may be a stacked memory such as an HBM. The memory chip may also include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, and the like.

On the other hand, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (chip scale package), FC-CSP (flip chip-chip scale package), FC-BGA (flip chip ball grid array), POP (stacked package), and SIP (system-in-package), but is not limited thereto.

In addition, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automobile, or the like. However, the embodiment is not limited thereto, and may be any other electronic device that processes data other than these.

Hereinafter, a semiconductor package including a circuit board according to an embodiment will be described. The semiconductor package of the embodiment may have various package structures including a circuit board to be described later. In addition, the circuit board in one embodiment may be a package substrate described below, and the circuit board in another embodiment may be an interposer described below.

Fig. 2a is a sectional view showing a semiconductor package according to a first embodiment, fig. 2b is a sectional view showing a semiconductor package according to a second embodiment, fig. 2c is a sectional view showing a semiconductor package according to a third embodiment, fig. 2d is a sectional view showing a semiconductor package according to a fourth embodiment, fig. 2e is a sectional view showing a semiconductor package according to a fifth embodiment, fig. 2f is a sectional view showing a semiconductor package according to a sixth embodiment, and fig. 2g is a sectional view showing a semiconductor package according to a seventh embodiment.

Referring to fig. 2a, a semiconductor package according to a first embodiment may include a first circuit board 1100, a second circuit board 1200, and a semiconductor device 1300.

The first circuit board 1100 refers to a package substrate.

For example, the first circuit board 1100 may provide a space to which at least one external substrate is coupled. The external substrate may refer to a second circuit board 1200 coupled to the first circuit board 1100. Further, the external substrate may refer to a main board included in an electronic device coupled to a lower portion of the first circuit board 1100.

Further, although not shown in the drawings, the first circuit board 1100 may provide a space in which at least one semiconductor device is mounted.

The first circuit board 1100 includes at least one insulating layer, an electrode disposed on the at least one insulating layer, and a penetration portion penetrating the at least one insulating layer.

The second circuit board 1200 is disposed on the first circuit board 1100.

The second circuit board 1200 may be an interposer. For example, the second circuit board 1200 may provide a space in which at least one semiconductor device is mounted. The second circuit board 1200 may be connected to at least one semiconductor device 1300. For example, the second circuit board 1200 may provide a space in which the first semiconductor device 1310 and the second semiconductor device 1320 are mounted. The second circuit board 1200 may electrically connect the first semiconductor device 1310 and the second semiconductor device 1320 and electrically connect to the first circuit board 1100 while simultaneously electrically connecting the first semiconductor device 1310 and the second semiconductor device 1320. That is, the second circuit board 1200 may perform a horizontal connection function between a plurality of semiconductor devices and a vertical connection function between the semiconductor devices and the package substrate.

Fig. 2 shows that the first semiconductor device 1310 and the second semiconductor device 1320 are disposed on the second circuit board 1200, but is not limited thereto. For example, one semiconductor device may be provided on the second circuit board 1200, or alternatively, three or more semiconductor devices may be provided.

The second circuit board 1200 may be disposed between the semiconductor device 1300 and the first circuit board 1100.

In one embodiment, the second circuit board 1200 may be an active interposer that serves as a semiconductor device. When the second circuit board 1200 is used as a semiconductor device, the package of the embodiment may have a structure in which a plurality of logic chips are mounted on the first circuit board 1100 in a vertically stacked structure. In addition, a first logic chip corresponding to the active interposer among the logic chips may perform a signal transfer function between a second logic chip disposed thereon and the first circuit board 1100 while serving as a corresponding logic chip.

According to another embodiment, the second circuit board 1200 may be a passive interposer. For example, the second circuit board 1200 may serve as a signal relay between the semiconductor device 1300 and the first circuit board 1100. For example, the number of terminals of the semiconductor device 1300 is gradually increasing due to 5G, internet of things (IOT), improvement in image quality, and improvement in communication speed. That is, the number of terminals provided in the semiconductor device 1300 increases, whereby the width of the terminals or the intervals between the plurality of terminals decreases. In this case, the first circuit board 1100 is connected to the main board of the electronic device. There is a problem in that in order to make the electrodes provided on the first circuit board 1100 have a certain width and interval to be connected to the semiconductor device 1300 and the main board, respectively, the thickness of the first circuit board 1100 is increased or the layer structure of the first circuit board 1100 becomes complicated. Accordingly, in the first embodiment, the second circuit board 1200 is disposed on the first circuit board 1100 and the semiconductor device 1300. In addition, the second circuit board 1200 may include electrodes having fine widths and intervals corresponding to terminals of the semiconductor device 1300.

The semiconductor device 1300 may be an Application Processor (AP) chip including at least one of a Central Processing Unit (CPU), a Graphics Processor (GPU), a digital signal processor, an encryption processor, a microprocessor and microcontroller, or an analog-to-digital converter, an Application Specific IC (ASIC), etc., or a chipset including a specific combination of those listed so far. The memory chip may be a stacked memory such as an HBM. The memory chip may also include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, and the like.

Meanwhile, the semiconductor package of the first embodiment may include a connection portion.

For example, the semiconductor package includes a first connection portion 1410 disposed between the first circuit board 1100 and the second circuit board 1200. The first connection portion 1410 electrically connects the second circuit board 1200 to the first circuit board 1100 while coupling them.

For example, the semiconductor package may include a second connection portion 1420 disposed between the second circuit board 1200 and the semiconductor device 1300. The second connection portion 1420 may electrically connect the semiconductor device 1300 to the second circuit board 1200 while coupling them.

The semiconductor package includes a third connection portion 1430 disposed on a lower surface of the first circuit board 1100. The third connection portion 1430 may connect the first circuit board 1100 to the main board while coupling them.

At this time, the first, second and third connection parts 1410, 1420 and 1430 may be electrically connected between the plurality of parts by using at least one bonding method of wire bonding, solder bonding and metal-to-metal direct bonding.

That is, since the first, second and third connection parts 1410, 1420 and 1430 have a function of electrically connecting a plurality of parts, when metal-to-metal bonding is used, the connection part of the semiconductor package may be understood as an electrical connection part, not a solder or a wire.

The wire bonding method may refer to electrically connecting a plurality of components using a conductive wire such as gold (Au). In addition, the solder bonding method may electrically connect a plurality of components using a material containing at least one of Sn, ag, and Cu. In addition, the metal-to-metal direct bonding method may refer to recrystallization by applying heat and pressure between a plurality of components in the absence of solder, wires, conductive adhesives, or the like, and is used for direct bonding between the plurality of components. In addition, the metal-to-metal direct bonding method may refer to a bonding method through the second connection portion 1420. In this case, the second connection portion 1420 may represent a metal layer formed between the plurality of parts by recrystallization.

Specifically, the first, second and third connection parts 1410, 1420 and 1430 may couple the plurality of parts to each other by a thermo-compression (TC) bonding method. TC bonding may refer to a method of directly coupling a plurality of components by applying heat and pressure to the first, second, and third connection portions 1410, 1420, 1430.

In this case, at least one of the first circuit board 1100 and the second circuit board 1200 may include protrusions provided in the electrodes on which the first, second, and third connection parts 1410, 1420, and 1430 are provided. The protrusion may protrude outward from the first circuit board 1100 or the second circuit board 1200.

The protrusions may be referred to as bumps. The protrusions may also be referred to as posts. The protrusions may also be referred to as struts. Preferably, the protrusion may refer to an electrode of the electrodes of the second circuit board 1200 on which the second connection portion 1420 for coupling with the semiconductor device 1300 is disposed. That is, as the pitch of the terminals of the semiconductor device 1300 decreases, a short circuit may occur in the second connection portions 1420 respectively connected to the terminals of the semiconductor device 1300. Accordingly, in an embodiment, the protrusion is included in the electrode of the second circuit board 1200 on which the second connection portion 1420 is disposed, so as to reduce the volume of the second connection portion 1420. The protrusion may improve the matching between the electrode of the second circuit board 1200 and the terminal of the semiconductor device 1300 and prevent the diffusion of the second connection portion 1420.

Meanwhile, referring to fig. 2b, the semiconductor package of the second embodiment is different from the semiconductor package of the first embodiment in that a connection member 1210 is provided on a second circuit board 1200. The connection member 1210 may be referred to as a bridging substrate. For example, the connection member 1210 may include a redistribution layer.

In an embodiment, the connection member 1210 may be a silicon bridge. That is, the connection member 1210 may include a silicon substrate and a redistribution layer disposed on the silicon substrate.

In another embodiment, the connection member 1210 may be an organic bridge. For example, the connection member 1210 may include an organic material. For example, the connection member 1210 includes an organic substrate including an organic material instead of a silicon substrate.

The connection member 1210 may be embedded in the second circuit board 1200, but is not limited thereto. For example, the connection member 1210 may be provided on the second circuit board 1200 to have a protruding structure.

Further, the second circuit board 1200 may include a cavity, and the connection member 1210 may be disposed in the cavity of the second circuit board 1200.

The connection member 1210 may horizontally connect a plurality of semiconductor devices disposed on the second circuit board 1200.

Referring to fig. 2c, the semiconductor package according to the third embodiment includes a second circuit board 1200 and a semiconductor device 1300. In this case, the semiconductor package of the third embodiment has a structure in which the first circuit board 1100 is removed, compared to the semiconductor package of the second embodiment.

That is, the second circuit board 1200 of the third embodiment may serve as a package substrate while performing an intermediate layer function.

The first connection portion 1410 provided on the lower surface of the second circuit board 1200 may couple the second circuit board 1200 to a main board of the electronic device.

Referring to fig. 2d, the semiconductor package according to the fourth embodiment includes a first circuit board 1100 and a semiconductor device 1300.

In this case, the semiconductor package of the fourth embodiment has a structure in which the second circuit board 1200 is removed, as compared with the semiconductor package of the second embodiment.

That is, the first circuit board 1100 of the fourth embodiment may serve as an interposer connecting the semiconductor device 1300 and the motherboard while serving as a package substrate. For this, the first circuit board 1100 may include a connection member 1110 for connecting a plurality of semiconductor devices. The connection member 1110 may be a silicon bridge or an organic material bridge connecting a plurality of semiconductor devices.

Referring to fig. 2e, the semiconductor package of the fifth embodiment further includes a third semiconductor device 1330, as compared to the semiconductor package of the fourth embodiment.

For this, the fourth connecting portion 1440 is disposed on the lower surface of the first circuit board 1100.

In addition, a third semiconductor device 1330 may be disposed on the fourth connection portion 1400. That is, the semiconductor package of the fifth embodiment may have a structure in which semiconductor devices are mounted on an upper side and a lower side, respectively.

In this case, the third semiconductor device 1330 may have a structure disposed on the lower surface of the second circuit board 1200 in the semiconductor package of fig. 2 c.

Referring to fig. 2f, the semiconductor package according to the sixth embodiment includes a first circuit board 1100.

The first semiconductor device 1310 may be disposed on the first circuit board 1100. For this, the first connection portion 1410 is disposed between the first circuit board 1100 and the first semiconductor device 1310.

In addition, the first circuit board 1100 includes a conductive coupling portion 1450. The conductive coupling portion 1450 may further protrude from the first circuit board 1100 toward the second semiconductor device 1320. The conductive coupling portion 1450 may be referred to as a bump or, alternatively, may also be referred to as a post. The conductive coupling portion 1450 may be provided to have a protruding structure on an electrode disposed at the uppermost side of the first circuit board 1100.

The second semiconductor device 1320 is disposed on the conductive coupling portion 1450 of the first circuit board 1100. In this case, the second semiconductor device 1320 may be connected to the first circuit board 1100 through the conductive coupling portion 1450. In addition, the second connection portion 1420 may be disposed on the first semiconductor device 1310 and the second semiconductor device 1320.

Accordingly, the second semiconductor device 1320 may be electrically connected to the first semiconductor device 1310 through the second connection portion 1420.

That is, the second semiconductor device 1320 is connected to the first circuit board 1100 through the conductive coupling portion 1450, and is also connected to the first semiconductor device 1310 through the second connection portion 1420.

In this case, the second semiconductor device 1320 may receive the power signal through the conductive coupling portion 1450. In addition, the second semiconductor device 1320 may transmit and receive communication signals to and from the first semiconductor device 1310 through the second connection portion 1420.

The semiconductor package according to the sixth embodiment supplies a power signal to the second semiconductor device 1320 through the conductive coupling portion 1450, thereby supplying sufficient power to drive the second semiconductor device 1320. Accordingly, the embodiment can improve the driving characteristics of the second semiconductor device 1320. That is, the embodiment can solve the problem of insufficient power supplied to the second semiconductor device 1320. Further, in an embodiment, the power signal and the communication signal of the second semiconductor device 1320 are provided through different paths via the conductive coupling portion 1450 and the second connection portion 1420. Thus, the embodiment can solve the problem that the communication signal is lost due to the power signal. For example, embodiments may minimize mutual interference between the power signal and the communication signal. Meanwhile, the second semiconductor device 1320 according to the sixth embodiment may have a POP structure and be disposed on the first circuit board 1100. For example, the second semiconductor device 1320 may be a memory package including a memory chip. In addition, a memory package may be coupled to the conductive coupling portion 1450. In this case, the memory package may not be connected to the first semiconductor device 1310.

Referring to fig. 2g, the semiconductor package according to the seventh embodiment includes a first circuit board 1100, a first connection portion 1410, a semiconductor device 1300, and a third connection portion 1430.

In this case, the semiconductor package of the seventh embodiment is different from the semiconductor package of the fourth embodiment in that the first circuit board 1100 includes a plurality of substrate layers while the connection member 1110 is removed.

The first circuit board 1100 includes a plurality of substrate layers. For example, the first circuit board 1100 may include a first substrate layer 1100A corresponding to the package substrate and a second substrate layer 1100B corresponding to the redistribution layer of the connection member.

That is, in the first circuit board 1100, the second substrate layer 1100B corresponding to the redistribution layer is disposed on the first substrate layer 1100A.

That is, the semiconductor package of the seventh embodiment includes the first substrate layer 1100A and the second substrate layer 1100B integrally formed. The material of the insulating layer of the second substrate layer 1100B may be different from that of the insulating layer of the first substrate layer 1100A. For example, the material of the insulating layer of the second substrate layer 1100B may include a photocurable material. For example, the second substrate layer 1100B may be a photoimageable dielectric (PID). In addition, since the second substrate layer 1100B includes a photocurable material, the electrode can be miniaturized. Accordingly, in the seventh embodiment, the second substrate layer 1100B may be formed by sequentially stacking insulating layers of a photocurable material on the first substrate layer 1100A and forming miniaturized electrodes on the insulating layers of the photocurable material. Thus, the second substrate 1100B may be a redistribution layer including miniaturized electrodes.

Hereinafter, a circuit board of an embodiment will be described.

Before describing the circuit board of the embodiment, the circuit board described below may represent any one of a plurality of circuit boards included in the previous semiconductor package.

For example, in one embodiment, the circuit board described below may refer to the first circuit board 1100 shown in any one of fig. 2 a-2 g. In addition, the circuit board described below in another embodiment may refer to the second circuit board 1200 shown in any one of fig. 2a to 2 g.

Circuit board-

Fig. 3 is a view showing a circuit board according to the first embodiment, fig. 4a is an enlarged view of a certain area of fig. 3, fig. 4b is a view showing a SAM photo of a corresponding product in fig. 4a, and fig. 4c is a view for explaining a center line surface roughness (Ra) of an upper surface of the first insulating layer in fig. 4 a.

Hereinafter, a circuit board according to an embodiment will be described in detail with reference to fig. 3, 4a, 4b, 4c, and 5.

The circuit board of the embodiment provides a mounting space in which at least one chip can be mounted. The number of chips mounted on the circuit board of the embodiment may be one, may be two, or may be three or more, alternatively. For example, one processor chip may be mounted on a circuit board, alternatively, at least two processor chips having different functions may be mounted on a circuit board, alternatively, one memory chip may be mounted together with one processor chip, and alternatively, at least two processor chips and at least one memory chip having different functions may be mounted.

The circuit board includes an insulating layer 110. The insulating layer 110 has a structure of at least one layer. At this time, although fig. 2 shows that the circuit board has a three-layer structure based on the number of layers of the insulating layer 110, the embodiment is not limited thereto. For example, the circuit board may have a stacked structure of two or less layers, or may have a stacked structure of four or more layers, based on the number of insulating layers 110.

Hereinafter, however, for convenience of explanation, the circuit board will be described as having a three-layer structure based on the number of the insulating layers 110.

The insulating layer 110 may include a prepreg (PPG). The prepreg may be formed by impregnating a fibrous layer in the form of a fabric sheet (e.g. a glass fabric woven with glass yarns) with an epoxy resin and then performing hot pressing. However, the embodiment is not limited thereto, and the prepreg constituting the insulating layer 110 may include a fiber layer in the form of a fabric sheet woven with carbon fiber yarns.

The insulating layer 110 may include a resin and reinforcing fibers disposed in the resin. The resin may be an epoxy resin, but is not limited thereto. The resin is not particularly limited to an epoxy resin, and for example, may include one or more epoxy groups in a molecule, or may include two or more epoxy groups, or may include four or more epoxy groups. In addition, the resin of the insulating layer 110 may include a naphthalene group, for example, may be an aromatic amine type, but is not limited thereto. For example, the resin may include bisphenol a type epoxy resin, bisphenol F type epoxy resin, bisphenol S type epoxy resin, phenol novolac type epoxy resin, alkylphenol novolac type epoxy resin, biphenyl type epoxy resin, aralkyl type epoxy resin, dicyclopentadiene type epoxy resin, naphthalene type epoxy resin, naphthol type epoxy resin, epoxy resin of a condensate of phenol and aromatic aldehyde having a phenolic hydroxyl group, biphenyl aralkyl type epoxy resin, fluorene type epoxy resin, xanthene type epoxy resin, triglycidyl isocyanurate, rubber modified epoxy resin, phosphorus based epoxy resin, and the like, as well as naphthalene based epoxy resin, bisphenol a type epoxy resin and phenol novolac epoxy resin, cresol novolac epoxy resin, rubber modified epoxy resin, and phosphorus based epoxy resin. In addition, the reinforcing fibers may include glass fibers, carbon fibers, aramid fibers (e.g., aramid-based organic materials), nylon, silica-based inorganic materials, or titania-based inorganic materials. Reinforcing fibers may be arranged in the resin to cross each other in the plane direction.

Meanwhile, glass fibers, carbon fibers, aramid fibers (e.g., aramid-based organic materials), nylon, silica-based inorganic materials, or titania-based inorganic materials may be used.

However, the embodiment is not limited thereto, and the insulating layer 110 may include other insulating materials.

For example, the insulating layer 110 may be rigid or may be flexible. For example, the insulating layer 110 may include glass or plastic. In detail, the insulating layer 110 may include chemically strengthened/semi-tempered glass, such as soda lime glass or aluminosilicate glass, or strengthened or flexible plastic, such as Polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), and Polycarbonate (PC), or sapphire. For example, the insulating layer 110 may include an optically isotropic film. For example, the insulating layer 110 may include COC (cyclic olefin copolymer), COP (cyclic olefin polymer), photo-isotropic polycarbonate (polycarbonate, PC), or photo-isotropic polymethyl methacrylate (PMMA). For example, the insulating layer 110 may be formed of a material including an inorganic filler and an insulating resin. For example, the insulating layer 110 may be formed of a material including an inorganic filler and an insulating resin. For example, the insulating layer 110 may be formed of a thermosetting resin such as an epoxy resin, a resin containing a reinforcing material such as an inorganic filler (such as silica and alumina), and a thermoplastic resin such as polyimide, and in particular, an Ajinomoto build-up film (ABF), FR-4, bismaleimide Triazine (BT), a photoimageable dielectric resin (PID), BT, or the like may be used.

The insulating layer 110 may include a first insulating layer 111, a second insulating layer 112, and a third insulating layer 113 from the uppermost side.

The first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may each have a thickness ranging from 5 μm to 80 μm. For example, the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may have a thickness ranging from 10 μm to 60 μm. For example, the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may each have a thickness ranging from 12 μm to 40 μm. If the thickness of each of the first, second and third insulating layers 111, 112 and 113 is less than 5 μm, the circuit pattern included in the circuit board may not be stably protected. If the thickness of each of the first, second and third insulating layers 111, 112 and 113 exceeds 80 μm, the total thickness of the circuit board may increase. In addition, if the thickness of each of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 exceeds 80 μm, the thickness of the circuit pattern or the penetrating portion increases, respectively, and the loss of the signal transmitted through the circuit pattern may increase accordingly.

At this time, the thicknesses of the first, second, and third insulating layers 111, 112, and 113 may correspond to distances in the thickness direction between circuit patterns disposed at different layers.

For example, the thickness of the first insulating layer 111 may represent a linear distance between the lower surface of the first circuit pattern 121 and the upper surface of the second circuit pattern 122. For example, the thickness of the second insulating layer 112 may represent a linear distance between the lower surface of the second circuit pattern 122 and the third circuit pattern 123. For example, the thickness of the third insulating layer 113 may represent a straight line distance between the lower surface of the third circuit pattern 123 and the fourth circuit pattern 124.

Meanwhile, the first insulating layer 111 may be a first outermost insulating layer disposed at a first outermost side of the circuit board of the embodiment. For example, the first insulating layer 111 may be an uppermost insulating layer disposed at an uppermost side of the circuit board.

In addition, in the circuit board of the embodiment, the third insulating layer 113 may be a second outermost insulating layer disposed at a second outermost side opposite to the first insulating layer 111. For example, the third insulating layer 113 may be a lowermost insulating layer disposed at a lowermost side of the circuit board.

In addition, the second insulating layer 112 may be an inner insulating layer disposed between the first outermost insulating layer and the second outermost insulating layer. At this time, when the circuit board has a four-layer or more layer structure, the inner insulating layer may have a two-layer or more layer structure.

The circuit pattern is disposed on a surface of the insulating layer 110.

For example, the first circuit pattern 121 is disposed on the upper surface of the first insulating layer 111. For example, the second circuit pattern 122 is disposed on the lower surface of the first insulating layer 111 or the upper surface of the second insulating layer 112. For example, the third circuit pattern 123 is disposed on the lower surface of the second insulating layer 112 or the upper surface of the third insulating layer 113. For example, the fourth circuit pattern 124 is disposed on the lower surface of the third insulating layer 113.

In an embodiment, the circuit board may be manufactured using an Embedded Trace Substrate (ETS) method. Accordingly, at least one of the circuit patterns included in the circuit board may have an ETS structure. Here, having the ETS structure may mean having a structure in which an outermost circuit pattern provided at an outermost portion is embedded in an outermost insulating layer. That is, a cavity recessed toward the lower side is formed on the upper surface of the uppermost insulating layer provided on the uppermost side of the circuit board in the ETS structure, and thus, this may mean that the circuit pattern provided on the uppermost side of the circuit board has a structure provided in the cavity of the uppermost insulating layer.

For example, among the circuit patterns provided on each layer of the circuit board, the circuit pattern provided on at least one layer may have a structure embedded in an insulating layer. For example, in an embodiment, the circuit pattern disposed on the upper surface of the first outermost insulating layer may have an ETS structure. For example, in an embodiment, the first circuit pattern 121 disposed on the upper surface of the first insulating layer 111 may have an ETS structure. However, the embodiment is not limited thereto, and the circuit pattern disposed on the lowermost side of the circuit board may have an ETS structure depending on the arrangement direction of the circuit board. Hereinafter, for convenience of description of the embodiments, a circuit pattern disposed on the uppermost side of a circuit board will be described as having an ETS structure.

The first circuit pattern 121 may have a structure embedded in the first insulating layer 111. Preferably, the entire region of the first circuit pattern 121 may have a structure embedded in the insulating layer 110. For example, the fact that the entire region of the first circuit pattern 121 has a structure embedded in the first insulating layer 111 may mean that the entire side surface 121S of the first circuit pattern 121 is covered by the first insulating layer 111. For example, the fact that the entire region of the first circuit pattern 121 has a structure embedded in the first insulating layer 111 may indicate that a portion of the side surface 121S of the first circuit pattern 121 does not protrude on the upper surface 121T of the first insulating layer 111 (preferably, the uppermost portion of the upper surface of the first insulating layer).

In addition, the fact that the first circuit pattern 121 has an ETS structure may mean that at least a portion of the upper surface 121T of the first circuit pattern 121 does not overlap with the upper surface 111T of the first insulating layer 111 in the vertical direction. However, the entire region of the upper surface 121T of the first circuit pattern 121 may not overlap the upper surface 111T of the first insulating layer 111 in the vertical direction, or, differently, only some regions of the upper surface 121T of the first circuit pattern 121 may not overlap the upper surface 111T of the first insulating layer 111 in the vertical direction. That is, in the process of forming the first insulating layer 111 on the first circuit pattern 121, at least a portion of the first insulating layer 111 may penetrate into the inside of the first circuit pattern 121. In this case, at least a portion of the edge region of the upper surface 121T of the first circuit pattern 121 may overlap with the upper surface 111T of the first insulating layer 111 in the vertical direction.

In addition, the entire lower surface 121B of the first circuit pattern 121 may be covered with the first insulating layer 111.

For example, the upper surface 111T of the first insulating layer 111 may include a cavity (C) recessed toward the lower surface 111B of the first insulating layer 111. At this time, the depth of the cavity (C) may be greater than the thickness of the first circuit pattern 121. Therefore, at least a portion of the inner surface CS of the cavity (C) may not contact the side surface 121S of the first circuit pattern 121. For example, at least a portion of the inner surface CS of the cavity (C) contacts the side surface 121S of the first circuit pattern 121, and at least another portion of the inner surface CS of the cavity (C) may not contact the side surface 121S of the first circuit pattern 121.

At this time, the first insulating layer 111 includes an upper surface 111T and a lower surface 111B. In addition, the upper surface 111T of the first insulating layer 111 includes a cavity (C) recessed toward the lower surface 111B. In addition, the first circuit pattern 121 may be disposed in the cavity (C). For example, the cavity (C) may overlap the first circuit pattern 121 in a vertical direction.

Accordingly, the first insulating layer 111 may include an inner surface CS of the cavity (C) contacting the side surface 121S of the first circuit pattern 121, and a bottom surface CB of the cavity (C) contacting the lower surface 121B of the first circuit pattern 121. Here, the center line surface roughness (Ra) of the upper surface 111T, the center line surface roughness (Ra) of the lower surface 111B, the center line surface roughness (Ra) of the inner surface CS of the cavity (C), and the center line surface roughness (Ra) of the bottom surface CB of the first insulating layer 111 may be different from each other. This will be described in more detail below.

For example, the upper surface 111T of the first insulating layer 111 may have a first center line surface roughness.

Also, the inner surface CS of the cavity (C) and the bottom surface CB of the cavity (C) of the first insulating layer 111 may have a second center line surface roughness different from the first center line surface roughness of the upper surface 111T.

The first center line surface roughness of the upper surface 111T of the first insulating layer 111 may satisfy a range of 0.01 μm to 0.5 μm. For example, the first center line surface roughness of the upper surface 111T of the first insulating layer 111 may satisfy a range of 0.015 μm to 0.4 μm. For example, the first center line surface roughness of the upper surface 111T of the first insulating layer 111 may satisfy a range of 0.02 μm to 0.2 μm.

If the first center line surface roughness of the upper surface 111T of the first insulating layer 111 is less than 0.01 μm, during the process of stacking the dry films for forming the first circuit pattern 121, the bonding force between the dry films and the seed layer of the first circuit pattern 121 is reduced, and as a result, physical reliability may be lowered. In addition, if the first center line surface roughness of the upper surface 111T of the first insulating layer 111 is greater than 0.5 μm, it may be difficult to form a fine circuit pattern having a line width and a space of less than 10 μm as in the comparative example.

Specifically, the first center line surface roughness of the upper surface 111T of the first insulating layer 111 may correspond to the center line surface roughness of the seed layer for electrolytic plating the first circuit pattern 121. For example, (a) of fig. 3c shows the upper surface of the first insulating layer or the upper surface of the seed layer of the first circuit pattern in the comparative example, and (b) of fig. 3c shows the upper surface of the first insulating layer or the upper surface of the seed layer of the first circuit pattern in the embodiment. Therefore, if the surface roughness of the upper surface of the first insulating layer or the upper surface of the seed layer of the first circuit pattern has a center line surface roughness (Ra 1) exceeding 0.5 μm as in the comparative example, it may be difficult to form the first circuit pattern having a width and a spacing of 10 μm or less. In contrast, the embodiment allows the upper surface of the first insulating layer or the upper surface of the seed layer of the first circuit pattern to have a center line surface roughness (Ra 2) of 0.5 μm or less so that the width and interval of the first circuit pattern 121 is in the range of 2 μm to 8 μm.

Meanwhile, the inner surface CS of the cavity (C) and the bottom surface CB of the cavity (C) of the first insulating layer 111 have a center line surface roughness (Ra) greater than that of the upper surface 111T of the first insulating layer 111.

That is, the inner surface CS and the bottom surface CB of the cavity (C) of the first insulating layer 111 may be in contact with the side surface 121S and the lower surface 121B of the first circuit pattern 121. And thus, the inner surface CS and the bottom surface CB of the cavity (C) of the first insulating layer 111 may have the same center line surface roughness as the side surfaces 121S and the lower surface 121B of the first circuit pattern 121.

For example, the center line surface roughness (Ra) of the inner surface (CS) of the cavity (C) of the first insulating layer 111 may be the same as the center line surface roughness (Ra) of the side surface 121S of the first circuit pattern 121. In addition, the center line surface roughness (Ra) of the bottom surface CB of the cavity (C) of the first insulating layer 111 may be the same as the center line surface roughness (Ra) of the lower surface 121B of the first circuit pattern 121.

At this time, the first circuit pattern 121 is formed by electrolytic plating, and thus, the center line surface roughness (Ra) of the first circuit pattern 121 may be greater than the center line surface roughness (Ra) of the upper surface 111T of the first insulating layer 111. Further, in order to improve the adhesion of the first circuit pattern 121 to the first insulating layer 111, a pretreatment (e.g., etching process) process is performed after the electrolytic plating process. Accordingly, each center line surface roughness (Ra) of the inner surface CS of the cavity (C) of the first insulating layer 111, the bottom surface CB of the cavity (C) of the first insulating layer 111, the side surface 121S of the first circuit pattern 121, and the lower surface 121B of the first circuit pattern 121 may be smaller than the center line surface roughness (Ra) of the upper surface 111T of the first insulating layer 111.

Preferably, the side surface 121S and the lower surface 121B of the first circuit pattern 121 may have the same center line surface roughness (Ra) by performing the same pretreatment process. Accordingly, the inner surface CS and the bottom surface CB of the cavity (C) may have the same center line surface roughness (Ra).

Meanwhile, during a process of removing the seed layer after a process of manufacturing the circuit board, the upper surface 121T of the first circuit pattern 121 may be partially removed together with the seed layer. Accordingly, the center line surface roughness (Ra) of the upper surface 121T of the first circuit pattern 121 may be different from the center line surface roughness (Ra) of the side surface 121S of the first circuit pattern 121 and the center line surface roughness (Ra) of the lower surface 121B of the first circuit pattern 121.

Further, the upper surface 121T of the first circuit pattern 121 has a center line surface roughness Ra corresponding to the center line surface roughness Ra of the seed layer before the seed layer removal process, and thus the upper surface 121T of the first circuit pattern 121 has the same center line surface roughness (Ra) as the upper surface 111T of the first insulating layer 111. However, in the process of removing the seed layer, a portion of the first circuit pattern 121 is removed together with the seed layer, and thus, in the finally manufactured circuit board, the center line surface roughness (Ra) of the upper surface 121T of the first circuit pattern 121 may be different from the center line surface roughness (Ra) of the upper surface 111T of the first insulating layer 111.

Meanwhile, the lower surface 111B of the first insulating layer 111 may have a center line surface roughness (Ra) different from that of the upper surface 111T of the first insulating layer 111. For example, the lower surface 111B of the first insulating layer 111 has a center line surface roughness (Ra) corresponding to a copper foil layer or a seed layer formed by plating. For example, unlike the first circuit pattern 121, the second circuit pattern 122 formed on the lower surface 111B of the first insulating layer 111 does not need to be miniaturized, and thus, a seed layer of the second circuit pattern 122 may be formed by plating. Accordingly, the lower surface 111B of the first insulating layer 111 may have a center line surface roughness (Ra) greater than that of the upper surface 111T of the first insulating layer 111. However, the embodiment is not limited thereto, and the center line surface roughness (Ra) of the lower surface 111B of the first insulating layer 111 may be the same as the center line surface roughness (Ra) of the upper surface of the first insulating layer 111.

Meanwhile, a step SP may be provided at the upper surface 111T of the first insulating layer 111. For example, the upper surface 111T of the first insulating layer 111 may have a curvature. For example, a concave portion that is concave downward may be provided at the upper surface 111T of the first insulating layer 111. At this time, the cavity (C) is disposed in a region overlapping the first circuit pattern 121 in the vertical direction at the upper surface 111T of the first insulating layer 111. In addition, a concave portion corresponding to the step SP may be provided at a region at the upper surface 111T of the first insulating layer 111 that does not overlap the first circuit pattern 121 in the vertical direction.

For example, in the process of removing the seed layer of the first circuit pattern 121, the first insulating layer 111 is partially removed, and thus, it may have a step, a curved surface, or a concave portion as shown in fig. 3 a.

Accordingly, the upper surface 111T of the first insulating layer 111 may include a first portion 111T1 positioned higher than the upper surface 121T of the first circuit pattern 121 and a second portion 111T2 positioned lower than the upper surface 121T of the first circuit pattern 121. Further, the first portion 111T1 and the second portion 111T2 of the upper surface 111T of the first insulating layer 111 may have steps SP of different heights. At this time, the first portion 111T1 of the upper surface 111T of the first insulating layer 111 may be positioned adjacent to the side surface 121S of the first circuit pattern 121, as compared to the second portion 111T2. For example, the second portion 111T2 of the upper surface 111T of the first insulating layer 111 may be positioned farther from the side surface 121S of the first circuit pattern 121 than the first portion 111T 1. Accordingly, the step SP of the upper surface 111T of the first insulating layer 111 may have a height that decreases as it moves away from the side surface 121S of the first circuit pattern 121.

Thus, the embodiment can improve the electrical reliability of the circuit board. In particular, a recent high integration of the circuit board is required, and therefore, the line width and pitch of the first circuit pattern 121 become finer. In this case, an insulating layer, such as a protective layer, may not be placed on the circuit board. At this time, a space for disposing a connection portion (e.g., solder) for attaching a chip or an interposer may not be secured on the first circuit pattern 121. As a result, a short circuit problem may occur at the connection of adjacent circuit patterns due to the flow of the connection portion. In contrast, the embodiment may block the flow of the connection portion through the second portion 111T2 of the upper surface 111T of the first insulating layer 111. Further, the embodiment can increase the length of the upper surface 111T of the first insulating layer 111 by the second portion 111T2, and as a result, even if the connection portion flows, it can be prevented from contacting the adjacent circuit pattern.

Also, in the embodiment, the second, third, and fourth circuit patterns 122, 123, and 124 other than the first circuit pattern 121 may have a structure protruding from the surface of the insulating layer 110.

Meanwhile, as shown in fig. 5, the first circuit pattern 121 may include a pad 121-1 and a trace 121-2 depending on functions. The pad 121-1 may be a pad on which a chip is mounted or a pad coupled to an external substrate. Trace 121-2 may be a signal wire connecting multiple pads. The trace 121-2 is a fine pattern, and thus, the line width W1 between the plurality of traces ranges from 2 μm to 8 μm, and the interval W2 of each trace may range from 2 μm to 8 μm. Specifically, in an embodiment, the line width and the interval of the trace 121-2 of the first circuit pattern 121 may be formed to 8 μm or less, which may be achieved by the center line surface roughness (Ra) of the upper surface 111T of the first insulating layer 111. This means that the line width and the interval of the trace 121-2 of the first circuit pattern 121 may be formed to 8 μm or more, and in this embodiment, the line width and the interval may be formed to be less than 8 μm unlike the comparative example. Accordingly, the embodiment may allow the first circuit patterns 121 to be densely arranged in a narrow space through miniaturization of the first circuit patterns 121.

Meanwhile, the second circuit pattern 122 may be disposed on the lower surface of the first insulating layer 111. The second circuit pattern 122 may protrude below the first insulating layer 111. The side surfaces and the lower surface of the second circuit pattern 122 may be covered with the second insulating layer 112.

For example, the third circuit pattern 123 may be disposed on a lower surface of the second insulating layer 112. The third circuit pattern 123 may protrude below the second insulating layer 112. For example, the side surfaces and the lower surface of the third circuit pattern 123 may be covered with the third insulating layer 113.

For example, the fourth circuit pattern 124 may be disposed on the lower surface of the third insulating layer 113. The fourth circuit pattern 124 may protrude under the third insulating layer 113.

The circuit pattern as described above may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). In addition, the circuit pattern may be formed of paste or solder paste including at least one metal material having an excellent bonding force selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Preferably, the first, second, third and fourth circuit patterns 121, 122, 123 and 124 may be formed of copper (Cu) having high conductivity and relatively inexpensive price.

Each of the first, second, third and fourth circuit patterns 121, 122, 123 and 124 may have a thickness in a range of 5 to 20 μm. For example, each of the first, second, third, and fourth circuit patterns 121, 122, 123, and 124 may have a thickness in a range of 6 to 17 μm. Each of the first, second, third and fourth circuit patterns 121, 122, 123 and 124 may have a thickness in a range of 7 to 16 μm. When the thickness of each of the first, second, third, and fourth circuit patterns 121, 122, 123, and 124 is less than 5 μm, the resistance of the circuit patterns may increase, and thus the signal transmission efficiency may decrease. For example, when the thicknesses of the first and second circuit patterns 121 and 350 are less than 5 μm, signal transmission loss may increase. For example, when the thickness of each of the first, second, third, and fourth circuit patterns 121, 122, 123, and 124 exceeds 20 μm, the line width of the circuit pattern increases, and thus, the total volume of the circuit board may increase.

The circuit board of an embodiment includes a through portion.

The penetrating portion penetrates through the insulating layer 110 included in the circuit board, and thus, circuit patterns disposed on different layers may be electrically connected. At this time, the penetrating portion may be formed to penetrate only one insulating layer, or alternatively, the penetrating portion may be formed to commonly penetrate at least two or more insulating layers.

For example, the circuit board includes a first through portion 131. The first penetrating portion 131 may be formed to penetrate the first insulating layer 111. The first through portion 131 may electrically connect the first circuit pattern 121 and the second circuit pattern 122. For example, the upper surface of the first penetrating portion 131 may be directly connected to the lower surface of the first circuit pattern 121. For example, the lower surface of the first penetrating portion 131 may be directly connected to the upper surface of the second circuit pattern 122. In addition, the first and second circuit patterns 121 and 122 may be electrically connected to each other through the first through portion 131 to transmit signals.

For example, the circuit board includes a second through portion 132. The second penetration portion 132 may be formed to pass through the second insulation layer 112. The second penetration portion 132 may electrically connect the second circuit pattern 122 and the third circuit pattern 123. For example, the upper surface of the second penetration portion 132 may be directly connected to the lower surface of the second circuit pattern 122. For example, the lower surface of the second penetration portion 132 may be directly connected to the upper surface of the third circuit pattern 123. Accordingly, the second and third circuit patterns 122 and 123 may be directly electrically connected to each other through the second penetration portion 132 and transmit signals.

For example, the circuit board includes a third penetration portion 133. The third penetration portion 133 may be formed to pass through the third insulating layer 113. The third penetration portion 133 may electrically connect the third circuit pattern 123 and the fourth circuit pattern 124. For example, the upper surface of the third penetration portion 133 may be directly connected to the lower surface of the third circuit pattern 123. For example, the lower surface of the third penetration portion 133 may be directly connected to the upper surface of the fourth circuit pattern 124. Accordingly, the third circuit pattern 123 and the fourth circuit pattern 124 may be electrically connected to each other and transmit signals.

The penetrating portion of the circuit board including the first penetrating portion 131, the second penetrating portion 132, and the third penetrating portion 133 as described above may be formed by forming a through hole penetrating the insulating layer 110 and filling the inside of the formed through hole with a conductive material.

The via holes may be formed by any one of mechanical, laser, and chemical processes. When the through-holes are formed by machining, methods such as milling, drilling, and wiring may be used, when formed by laser processing, UV or CO ₂ laser methods may be used, and when formed by chemicals, chemicals containing aminosilanes, ketones, and the like may be used. Thus, at least one of the plurality of insulating layers may be open.

Meanwhile, laser treatment is a cutting method that concentrates light energy on a surface to melt and evaporate a portion of a material to take a desired shape, and thus, complex formations can be easily processed by a computer program, and even composite materials that are difficult to cut by other methods can be processed.

Furthermore, the laser treatment has a cutting diameter of at least 0.005mm and has a wide range of possible thicknesses.

As laser processing drilling, a YAG (yttrium aluminum garnet) laser, a CO ₂ laser, or an Ultraviolet (UV) laser is preferably used. YAG laser is a laser that can handle both copper foil and insulating layers, while CO ₂ laser is a laser that can only handle insulating layers.

When forming the through hole, the penetrating portion may be formed by filling the inside of the through hole with a conductive material. The metal material forming the penetrating portion may be any one material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). Further, the conductive material filling may use any one or a combination of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjet, and dispensing.

Meanwhile, the circuit board of the embodiment may include a first protective layer 140 and a second protective layer 150. The first protective layer 140 and the second protective layer 150 may be disposed at the outermost side of the circuit pattern 121.

For example, the first protective layer 140 may be disposed at a first outermost side or an uppermost side of the circuit board. For example, the first protective layer 140 may be disposed on an upper surface of the first insulating layer 111. For example, the second protective layer 150 may be disposed at a second outermost or lowermost side of the circuit board. For example, the second protective layer 150 may be disposed on the lower surface of the third insulating layer 113.

The first protection layer 140 may include at least one Opening (OR). For example, the first protective layer 140 may include an opening OR overlapping the upper surface of the first circuit pattern 121 in the vertical direction. In addition, a connection portion (e.g., a solder ball) for chip mounting may be disposed on an upper surface of the first circuit pattern 121 overlapping the opening OR of the first protective layer 140 in a vertical direction.

At this time, the lower surface of the first protective layer 140 may contact the upper surface 111T of the first insulating layer 111. Here, the embodiment allows the center line surface roughness (Ra) of the upper surface 111T of the first insulating layer 111 to be 0.01 μm to 0.5 μm to miniaturize the first circuit pattern 121. At this time, if the center line surface roughness (Ra) of the upper surface 111T of the first insulating layer 111 is 0.01 μm to 0.5 μm, although the first circuit pattern 121 may be miniaturized, there may be a problem in terms of adhesion to the first protective layer 140. At this time, in the embodiment, the upper surface 111T of the first insulating layer 111 is provided with a concave portion such as a step SP. In addition, the first protective layer 140 may be formed by filling a concave portion of the step SP on the upper surface 111T of the first insulating layer 111. In addition, the concave portion such as the step SP can increase the contact area between the upper surface 111T of the first insulating layer 111 and the lower surface of the first protective layer 140, and thus, the adhesion between the first insulating layer 111 and the first protective layer 140 can be improved.

The second protective layer 150 may include at least one opening (not shown).

For example, the second protective layer 150 may have an opening overlapping the lower surface of the fourth circuit pattern 124 in the vertical direction. For example, the second protective layer 150 may have an opening overlapping in the vertical direction with an area (e.g., a terminal pad portion connected to an external substrate) of the lower surface of the fourth circuit pattern 124 where a solder ball will be placed later.

At this time, although not shown in the drawings, a surface treatment layer (not shown) may be disposed on a lower surface of the fourth circuit pattern 124 overlapping with the opening of the second protective layer 150 in the vertical direction. The surface treatment layer may be formed to improve the soldering characteristics while preventing corrosion and oxidation of the fourth circuit pattern 124 exposed through the second protective layer 150.

The surface treatment layer may be an Organic Solderability Preservative (OSP) layer. For example, the surface treatment layer may be an organic layer formed of an organic material such as benzimidazole coated on the lower surface of the fourth circuit pattern 124.

However, the embodiment is not limited thereto. For example, the surface treatment layer may be a plating layer. For example, the surface treatment layer may include at least one of a nickel (Ni) plating layer, a palladium (Pd) plating layer, and a gold (Au) plating layer. In addition, the surface treatment layer may be exposed through the first protective layer 140, or may be formed on an upper surface of the first circuit pattern 121 where the first protective layer 140 is not disposed.

Meanwhile, as shown in fig. 5, in an embodiment, the circuit pattern and the penetration portion may have a multi-layered structure. However, in the embodiment, the first circuit pattern 121 among the circuit patterns has an ETS structure, and thus, the layer structure of the first circuit pattern 121 having the ETS structure may be different from that of other circuit patterns or the penetrating portion.

For example, the layer structure of the first circuit pattern 121 may be different from the layer structures of the second, third, and fourth circuit patterns 122, 123, and 124. For example, the number of layers of the first circuit pattern 121 may be smaller than that of each of the second, third, and fourth circuit patterns 122, 123, and 124.

For example, the first circuit pattern 121 may include only electrolytic plating. Or the second, third and fourth circuit patterns 122, 123 and 124 may each include a seed layer and an electrolytic plating layer. For example, the second circuit pattern 122 may include a seed layer 122-1 and an electrolytic plating layer 122-2. For example, the third circuit pattern 123 may include a seed layer 123-1 and an electrolytic plating layer 123-2. For example, the fourth circuit pattern 124 may include a seed layer 124-1 and an electrolytic plating layer 124. Accordingly, the penetrating portion included in the circuit board may include a seed layer and an electrolytic plating layer. For example, the first penetrating portion 131 may include a seed layer 131-1 and an electrolytic plating layer 131-2. For example, the second penetration portion 132 may include a seed layer 132-1 and an electrolytic plating layer 132-2. For example, the third penetration portion 133 may include a seed layer 133-1 and an electrolytic plating layer 133-2.

The circuit board of the embodiment includes a first insulating layer and a first circuit pattern. The first insulating layer is an uppermost insulating layer, and the first circuit pattern is an uppermost circuit pattern disposed on an upper surface of the uppermost insulating layer. At this time, the first circuit pattern is embedded in the first insulating layer. For example, at least a portion of the upper surface of the first circuit pattern does not overlap with the upper surface of the first insulating layer in the vertical direction. At this time, the upper surface of the first insulating layer in the embodiment has a center line surface roughness (Ra) in the range of 0.01 μm to 0.5 μm. And, the center line surface roughness of the upper surface of the first insulating layer corresponds to the center line surface roughness of the sputtered layer serving as the seed layer of the first circuit pattern. At this time, if the center line surface roughness (Ra) of the seed layer of the first circuit pattern exceeds 0.6 μm and the center line surface roughness (Ra) of the upper surface of the first insulating layer correspondingly exceeds 0.6 μm, there is a space portion between the dry film and the seed layer, and thus it is difficult to refine the line width and the space of the first circuit pattern to 10 μm or less. In contrast, the embodiment allows the center line surface roughness (Ra) of the seed layer and the center line surface roughness (Ra) of the upper surface of the first insulating layer to be in the range of 0.01 μm to 0.5 μm. Accordingly, the embodiment can increase a contact area between the seed layer and the dry film, thereby enabling miniaturization of the first circuit pattern. Accordingly, in an embodiment, the line width and the interval of the first circuit pattern may be formed to 8 μm or less, and thus the circuit integration may be improved, and furthermore, the horizontal width and the vertical thickness of the circuit board may be reduced.

In addition, in the embodiment, a step is formed at the upper surface of the first insulating layer. The step may be formed by removing a portion of the upper surface of the first insulating layer when the seed layer of the first circuit pattern is removed. At this time, if the center line surface roughness (Ra) of the upper surface of the first insulating layer is 0.5 μm or less, the first circuit pattern can be miniaturized. However, it may cause a problem of adhesion to the first protective layer (such as a solder resist). Here, the embodiment forms a step such as a concave portion on the upper surface of the first insulating layer, and allows the first protective layer to fill the concave portion of the upper surface of the first insulating layer during the formation of the first protective layer. Accordingly, the embodiment can increase the contact area between the upper surface of the first insulating layer and the lower surface of the first protective layer, and thus, can improve the adhesion between the first insulating layer and the first protective layer.

In addition, the embodiment can improve the electrical reliability of the circuit board due to the step of the upper surface of the first insulating layer. In particular, a recent high integration of the circuit board is required, and therefore, the line width and pitch of the first circuit pattern become finer. In this case, an insulating layer, such as a protective layer, may not be placed on the circuit board. At this time, a space for disposing a connection portion (e.g., solder) for attaching the chip or the interposer may not be secured on the first circuit pattern. As a result, a short circuit problem may occur at the connection of adjacent circuit patterns due to the flow of the connection portion. In contrast, the embodiment may block the flow of the connection portion through the second portion of the upper surface of the first insulating layer. Further, the embodiment can increase the length of the upper surface of the first insulating layer by the second portion, and as a result, even if the connection portion flows, it can be prevented from contacting the adjacent circuit pattern.

Packaging substrate-

Fig. 7 is a view illustrating a package substrate according to an embodiment.

Referring to fig. 7, the package substrate of the embodiment includes the circuit board shown in fig. 2, at least one chip mounted on the circuit board, a molding layer for molding the chip, and a connection portion for coupling the chip or the external board. For example, the package substrate of fig. 7 may represent a portion of the semiconductor package of fig. 2A-2F.

Hereinafter, a package substrate including the circuit board of fig. 3 will be described.

For example, the package substrate 200 includes a connection portion 210 disposed on the first circuit pattern 121, the first circuit pattern 121 being disposed at the outermost side of the circuit board. The connection portion 210 may be disposed on a plurality of pads of the circuit board. For example, the connection portion 210 may include a first connection portion 211 disposed on a first pad of the first circuit pattern 121 and a second connection portion 212 disposed on a second pad of the first circuit pattern 121.

The first and second connection portions 211 and 212 may have a hexahedral shape. For example, the cross-sections of the first and second connection portions 211 and 212 may have a rectangular shape. The cross-sections of the first and second connection portions 211 and 212 may include rectangular or square shapes. For example, the first and second connection portions 211 and 212 may have a spherical shape. For example, the cross-sections of the first and second connection portions 211 and 212 may include a circular shape or a semicircular shape. For example, the cross-sections of the first and second connection portions 211 and 212 may include a partially or completely circular shape. The cross-sectional shapes of the first and second connection portions 211 and 212 may be flat on one side and curved on the other side. The first and second connection portions 211 and 212 may be solder balls, but are not limited thereto.

Meanwhile, the embodiment may include a chip 220 disposed on the connection portion 210. The chip 220 may be a processor chip. For example, the chip may be an Application Processor (AP) chip in a central processing unit (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller. The terminals 230 of the chip 220 may be connected to the first and second pads of the first circuit pattern 121 through the connection portion 210.

In addition, although not shown in the drawings, the package substrate of the embodiment may further include additional chips. For example, in an embodiment, at least two chips of a central processing unit (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller may be disposed on a circuit board at regular intervals. For example, the chip 220 in the embodiment may include a central processor chip and a graphic processor chip, but is not limited thereto.

Meanwhile, a plurality of chips may be spaced apart from each other at predetermined intervals on the circuit board. For example, the spacing between the plurality of chips may be 150 μm or less. For example, the spacing between the plurality of chips may be 120 μm or less. For example, the spacing between the plurality of chips may be 100 μm or less.

Preferably, the interval between the plurality of chips may have a range of 60 μm to 150 μm. Preferably, the interval between the plurality of chips may have a range of 70 μm to 120 μm. Preferably, the interval between the plurality of chips may have a range of 80 μm to 110 μm. When the interval between the plurality of chips is less than 60 μm, a problem of operational reliability may occur due to interference between the plurality of chips. When the interval between the plurality of chips is greater than 150 μm, the signal transmission loss may increase as the distance between the plurality of chips increases. When the interval between the plurality of chips is greater than 150 μm, the volume of the package substrate 200 may increase.

The package substrate 200 may include a molding layer 240. The molding layer 240 may be disposed to cover the chip 220. For example, the molding layer 240 may be EMC (epoxy molding compound) formed to protect the mounted chip 220, but is not limited thereto.

At this time, the molding layer 240 may have a low dielectric constant to increase heat dissipation characteristics. For example, the dielectric constant (Dk) of the molding layer 240 may be 0.2 to 10. For example, the dielectric constant (Dk) of the molding layer 240 may be 0.5 to 8. For example, the dielectric constant (Dk) of the molding layer 240 may be 0.8 to 5. Accordingly, in an embodiment, the molding layer 250 has a low dielectric constant to improve heat dissipation characteristics of heat generated from the chip 220.

Meanwhile, the package substrate 200 may include a connection portion 250 disposed at the lowermost side of the circuit board. The connection portion 250 may be disposed on the lower surface of the fourth circuit pattern 124 exposed through the second protective layer 150.

Manufacturing method-

Hereinafter, a method of manufacturing a circuit board according to the first embodiment will be described in the order of processing.

Referring to fig. 8a, in an embodiment, a base material for manufacturing a circuit board may be prepared using an ETS method.

For example, in an embodiment, the carrier plate 310 may be prepared with a carrier insulating layer 311 and a metal layer 312 disposed on at least one surface of the carrier insulating layer 311. At this time, the metal layer 312 may be disposed on only one of the first surface and the second surface of the carrier insulating layer 311, or may be disposed on both surfaces. For example, the metal layer 312 is provided only on one surface of the carrier insulating layer 311, and thus, the ETS process for manufacturing a circuit board may be performed only on the one surface. Alternatively, the metal layer 312 may be disposed on both surfaces of the carrier insulating layer 311, and thus, the ETS process for manufacturing the circuit board may be simultaneously performed on both surfaces of the carrier board 311. In this case, two circuit boards can be manufactured at a time.

At this time, the carrier insulating layer 311 and the metal layer 312 may be CCL (copper clad laminate).

Meanwhile, hereinafter, the following processes of manufacturing the circuit boards are simultaneously performed on the metal layers 312 provided on the upper and lower surfaces of the carrier insulating layer 311, and thus, two circuit boards can be simultaneously manufactured. However, for convenience of explanation, the embodiment will describe that the circuit board is manufactured only on the metal layer 312 provided on the lower surface of the carrier insulating layer 311.

Next, referring to fig. 8b, a sputtered layer 400 is formed on the lower surface of the metal layer 312, the sputtered layer 400 to be used as a seed layer for electrolytic plating of the first circuit pattern 121. The sputtered layer 400 may be formed on the metal layer 312 by a sputtering process. When the metal layer is formed by the sputtering process, the thickness of the metal layer may be thinner than that of the metal layer formed by the electroless copper plating process, and the center line surface roughness (Ra) of the metal layer may be reduced.

For example, in the case of forming a metal layer by electroless copper plating treatment, the center line surface roughness (Ra) exceeds 0.08 μm. In this case, as shown in fig. 1a and 1b, there is a problem in that it is difficult to miniaturize the first circuit pattern.

In contrast, in the case of forming the metal layer (sputtered layer 400) by sputtering, the center line surface roughness (Ra) is 0.05 μm or less. That is, in the case where the sputtered layer 400 is formed by sputtering in the embodiment, the center line surface roughness (Ra) may range from 0.01 μm to 0.5 μm. In this case, in order to miniaturize the first circuit pattern 121, the adhesion between the dry film and the sputtered layer 400 can be maintained even if the spacing distance between the openings of the dry film is 8 μm or less.

Next, referring to fig. 8c, in an embodiment, a first dry film 320 is formed on the sputtering layer 400. At this time, the first dry film 320 may be disposed to cover the entire lower surface of the sputtering layer 400. Next, the embodiment may perform a process of exposing and developing the formed first dry film 320.

Specifically, the embodiment may perform a process of forming the opening 321 by performing a process of exposing and developing the first dry film 320, the opening 321 overlapping a region on the lower surface of the sputtering layer 400 where the first circuit pattern is to be formed in a vertical direction.

At this time, the embodiment may perform a process of curing the first dry film 320 having the opening 321 formed by exposure and development.

The process of curing the first dry film 320 may include a process of curing using ultraviolet rays and a process of curing using infrared rays.

For example, in an embodiment, the first dry film 320 may be cured using ultraviolet rays in a range of 5mV to 100 mV. Or in an embodiment, the first dry film 320 may be cured by infrared thermal curing.

As described above, the embodiment may further perform a process of curing the first dry film 320, so that the adhesion between the sputtered layer 400 and the first dry film 320 may be improved. Accordingly, the embodiment may improve the adhesion between the first dry film 320 and the metal layer 312, and thus, the adhesion between the sputtered layer 400 and the first dry film 320 may be maintained, so that the first circuit pattern 121 filling the opening 321 may be miniaturized. For example, in an embodiment, the line width and the interval of the trace of the first circuit pattern 121 may be reduced by additionally performing a process of curing the first dry film 320. Further, by additionally performing the process of curing the first dry film 320, the embodiment may allow the interval between the traces to be smaller than the line width of the trace of the first circuit pattern 121.

Next, referring to fig. 8d, the embodiment may perform a process of forming the first circuit pattern 121 by performing electrolytic plating using the sputtering layer 400 as a seed layer, the first circuit pattern 121 filling the opening 321 of the cured first dry film 320.

Next, referring to fig. 8e, when the plating of the first circuit pattern 121 is completed, the embodiment may perform a process of removing the first dry film 320 formed on the lower surface of the sputtering layer 400.

Next, referring to fig. 8f, the embodiment may perform a process of forming the first insulating layer 111 covering the first circuit pattern 121 on the sputtered layer 400. At this time, the upper surface 111T of the first insulating layer 111 may directly contact the lower surface of the sputtered layer 400. Accordingly, the center line surface roughness (Ra) of the upper surface 111T of the first insulating layer 111 may be the same as the center line surface roughness (Ra) of the lower surface of the sputtered layer 400. For example, the upper surface of the first insulating layer 111 may have a center line surface roughness (Ra) in the range of 0.01 μm to 0.5 μm.

Next, referring to fig. 8g, the embodiment may perform a process of forming a Via Hole (VH) in the first insulating layer 111. The Via Hole (VH) may be formed by laser processing, but is not limited thereto.

Next, referring to fig. 8h, the embodiment may perform a process of forming the first through portion 131 and the second circuit pattern 122.

Specifically, the embodiment may perform a process of forming a seed layer on the lower surface of the first insulating layer 111 and the inner wall of the via hole VH, and a process of forming the second circuit pattern 122 and the first through portion 131 by electrolytic plating using the seed layer.

Next, referring to fig. 8i, the embodiment may perform the stacking process by repeating the processes shown in fig. 8f to 8 h.

Specifically, the embodiment may perform a process of forming the second insulating layer 112 covering the second circuit pattern 122 on the lower surface of the first insulating layer 111. Next, the embodiment may perform a process of forming the second penetration portion 132 penetrating the second insulating layer 112 and the third circuit pattern 123 protruding from the lower surface of the second insulating layer 112.

Next, referring to fig. 8j, the embodiment may perform additional stacking processing by repeating the processing shown in fig. 8 i.

Specifically, the embodiment may perform a process of forming the third insulating layer 113 covering the third circuit pattern 123 on the lower surface of the second insulating layer 112. Next, the embodiment may perform a process of forming the third penetration portion 133 penetrating the third insulating layer 113 and the fourth circuit pattern 124 protruding from the lower surface of the third insulating layer 113.

Next, referring to fig. 8k, the embodiment may perform a process of removing the carrier plate from the circuit board manufactured as described above. For example, the embodiment may perform a process of separating the carrier insulating layer 311 and the metal layer 312 based on an interface between the metal layer 312 of the carrier insulating layer 311 and the sputtered layer 400.

Next, referring to fig. 8l, the embodiment may perform a process of etching and removing the sputtered layer 400 remaining on the upper surface of the first insulating layer 111 of the circuit board. Thus, the embodiment can perform a process of exposing the upper surface of the first insulating layer 111 disposed on the uppermost side of the circuit board.

At this time, in the process of removing the sputtered layer 400, a portion of the upper surface 111T of the first insulating layer 111 and a portion of the upper surface 111T of the first circuit pattern 121 may also be removed.

Accordingly, the upper surface of the first insulating layer 111 has a step SP including a first portion 111T1 and a second portion 111T2 having different heights.

In addition, the upper surface 111T of the first circuit pattern 121 may be positioned lower than the upper surface of the first insulating layer 111, preferably lower than the first portion 111T1.

Next, referring to fig. 8m, the embodiment may perform a process of forming the first protective layer 140 on the upper surface of the first insulating layer 111 and a process of forming the second protective layer 150 having an opening on the lower surface of the third insulating layer 113.

Hereinafter, a circuit board according to a second embodiment will be described.

At this time, the overall structure of the circuit board of the second embodiment is the same as that of the circuit board of the first embodiment shown in fig. 3. Accordingly, hereinafter, the circuit board according to the second embodiment will be described using the same reference numerals as in fig. 3.

Fig. 9 is a view for explaining surface roughness of a circuit board and a first circuit pattern according to a second embodiment, fig. 10 is a view for explaining surface roughness of an internal circuit pattern or a second circuit pattern of fig. 9, and fig. 11 is a view for explaining a process of soft etching a lower surface of the first circuit pattern according to an embodiment.

Hereinafter, a circuit board according to a second embodiment will be described in detail with reference to fig. 9 to 11.

Hereinafter, a detailed description of substantially the same portions as the circuit board of the first embodiment will be omitted.

At least a portion or all of the first circuit pattern 121 may have a structure embedded in the first insulating layer 111. For example, the first circuit pattern 121 may be an outermost circuit pattern or an uppermost circuit pattern disposed at the outermost side of the circuit board. Accordingly, at least a portion of the side surface 121S of the first circuit pattern 121 may be covered by the first insulating layer 111.

Meanwhile, the upper surface 121T of the first circuit pattern 121 may be located on the same plane as the upper surface of the first insulating layer 111. Or the upper surface 121T of the first circuit pattern 121 may be positioned lower than the upper surface of the first insulating layer 111. This is because, in the process of etching the seed layer (not shown) of the first circuit pattern 121, a portion of the first circuit pattern 121 may also be removed.

The second circuit pattern 122 may be disposed at a lower surface of the first insulating layer 111. The second circuit pattern 122 may protrude below the first insulating layer 111. The side surfaces and the lower surface of the second circuit pattern 122 may be covered with the second insulating layer 112.

For example, the third circuit pattern 123 may be disposed at a lower surface of the second insulating layer 112. The third circuit pattern 123 may protrude below the second insulating layer 112. For example, the side surfaces and the lower surface of the third circuit pattern 123 may be covered with the third insulating layer 113.

At this time, in the second embodiment, a certain degree of surface roughness may be provided to the circuit pattern of the circuit board.

In the second embodiment, the first circuit pattern 121 disposed on the uppermost side may include an upper surface 121T, a side surface 121S, and a lower surface 121B.

The upper surface 121T of the first circuit pattern 121 does not overlap with the upper surface of the first insulating layer 111 in the vertical direction. For example, when the first circuit pattern is disposed at the first insulating layer 111, the upper surface 121T of the first circuit pattern 121 may be exposed to the upper side of the first insulating layer 111.

At this time, in an embodiment, the upper surface 121T, the side surface 121S, and the lower surface 121B of the first circuit pattern 121 may have different surface roughness. At this time, the surface roughness may be center line surface roughness (Ra), or it may be ten-point average roughness (Rz).

Here, in the circuit board of the comparative example, the upper surface of the first circuit pattern has a surface roughness different from that of the side surfaces and the lower surface of the first circuit pattern. However, in the circuit board of the comparative example, the side surface and the lower surface of the first circuit pattern have the same surface roughness as each other. For example, the side surfaces and the lower surface of the first circuit pattern are surfaces formed by plating, which have substantially the same surface roughness due to the same pretreatment process performed after the plating process.

In contrast, the side surface 121S and the lower surface 121B of the first circuit pattern 121 in the embodiment may have different surface roughness. This is because the preprocessing is performed at least twice on the lower surface 121B of the first circuit pattern 121 in order to perform the AOI of the first circuit pattern 121, while the preprocessing is performed less times on the side surface 121S of the first circuit pattern 121 than the lower surface 121B.

Accordingly, in an embodiment, the surface roughness of the side surface 121S of the first circuit pattern 121 may be smaller than the surface roughness of the lower surface 121B of the first circuit pattern 121.

For example, the pretreatment process performed on the lower surface 121B of the first circuit pattern 121 is performed at least once more than the pretreatment process performed on one side of the first circuit pattern 121, and thus, a surface roughness greater than that of the side surface of the first circuit pattern 121 may be applied.

The side surface 121S of the first circuit pattern 121 may have a surface roughness greater than 0 μm. For example, the side surface 121S of the first circuit pattern 121 may have a center line surface roughness (Ra) ranging from 0.05 μm to 0.6 μm. For example, the side surface 121S of the first circuit pattern 121 may have a center line surface roughness (Ra) ranging from 0.08 μm to 0.55 μm. For example, the side surface 121S of the first circuit pattern 121 may have a center line surface roughness (Ra) ranging from 0.1 μm to 0.45 μm. If the center line surface roughness (Ra) of the side surface 121S of the first circuit pattern 121 is less than 0.05 μm, the adhesion between the first insulating layer 111 and the side surface 121S of the first circuit pattern 121 may be reduced. If the center line surface roughness (Ra) of the side surface 121S of the first circuit pattern 121 is greater than 0.6 μm, transmission loss of a signal transmitted through the side surface 121S of the first circuit pattern 121 may increase. For example, the high-frequency signal has a characteristic of moving along the surface of the circuit pattern due to the skin effect. At this time, if the surface roughness of the circuit pattern increases, the resistance increases, and thus the signal transmission loss due to the skin effect may increase.

The lower surface 121B of the first circuit pattern 121 may have a center line surface roughness (Ra) greater than that of the side surface 121S of the first circuit pattern 121. This is because after the plating of the first circuit pattern 121 is completed in the manufacturing process of the first circuit pattern 121, an additional pretreatment process is performed only on the lower surface 121B of the first circuit pattern 121 in order to perform AOI on the first circuit pattern 121.

The lower surface 121B of the first circuit pattern 121 may have a center line surface roughness that may be greater than a center line surface roughness (Ra) of the side surface 121S of the first circuit pattern 121 within a range of the center line surface roughness (Ra) of the side surface 121S of the first circuit pattern 121.

For example, the center line surface roughness (Ra) of the lower surface 121B of the first circuit pattern 121 may be in a range between 110% and 170% of the center line surface roughness (Ra) of the side surface 121S of the first circuit pattern 121. For example, the center line surface roughness (Ra) of the lower surface 121B of the first circuit pattern 121 may be in a range between 120% and 160% of the center line surface roughness (Ra) of the side surface 121S of the first circuit pattern 121. For example, the center line surface roughness (Ra) of the lower surface 121B of the first circuit pattern 121 may be in a range between 125% and 150% of the center line surface roughness (Ra) of the side surface 121S of the first circuit pattern 121.

If the center line surface roughness (Ra) of the lower surface 121B of the first circuit pattern 121 is less than 110% of the center line surface roughness (Ra) of the side surface 121S of the first circuit pattern 121, inspection accuracy may be degraded when AOI of the lower surface 121B of the first circuit pattern 121 is performed. For example, in order to perform AOI of the lower surface 121B of the first circuit pattern 121, the center line surface roughness (Ra) of the lower surface 121B of the first circuit pattern 121 must be higher than a certain level. At this time, if the center line surface roughness (Ra) of the lower surface 121B of the first circuit pattern 121 is less than 110% of the center line surface roughness (Ra) of the side surface 121S of the first circuit pattern 121, this means that when AOI is performed, the center line surface roughness (Ra) of the lower surface 121B of the first circuit pattern 121 is at a level that does not allow AOI to be performed, and thus, inspection accuracy of the first circuit pattern 121 may be lowered. For example, if the center line surface roughness (Ra) of the lower surface 121B of the first circuit pattern 121 is less than 110% of the center line surface roughness (Ra) of the side surface 121S of the first circuit pattern 121, this means that the oxide on the lower surface 121B of the first circuit pattern 121 is not completely removed during AOI, and as a result, the inspection accuracy may be lowered. For example, after the formation of the first circuit pattern 121 is completed, the side surface 121S of the first circuit pattern 121 is covered with a dry film (not shown), and a soft etching process may be performed on the lower surface 121B of the first circuit pattern 121.

For example, as shown in fig. 11 (a), when plating of the first circuit pattern 121 is completed in the formation process of the first circuit pattern 121, the side surface 121S and the lower surface 121B of the first circuit pattern 121 may have substantially the same center line surface roughness (Ra). At this time, the lower surface 121B of the first circuit pattern 121 may have an oxide formed through a plating process. In addition, when the oxide is formed, the AOI accuracy of the lower surface 121B of the first circuit pattern 121 may be reduced. Further, when the plating of the first circuit pattern 121 is completed, the center line surface roughness (Ra) formed by the plating is not the center line surface roughness (Ra) capable of AOI, and thus the AOI accuracy may be lowered.

Accordingly, the embodiment allows the soft etching process to be performed only on the lower surface 121B of the first circuit pattern 121 after the plating of the first circuit pattern 121 is completed, and thus, provides the lower surface 121B of the first circuit pattern 121 with the center line surface roughness (Ra) allowing AOI while removing the oxide film on the lower surface 121B of the first circuit pattern 121.

Therefore, in the embodiment, the side surface 121S and the lower surface 121B of the first circuit pattern 121 have different center line surface roughness (Ra).

Meanwhile, in the etching process, the upper surface 121T of the first circuit pattern 121 is etched together with the seed layer to remove the seed layer for plating the first circuit pattern 121, and thus, the center line surface roughness (Ra) thereof may be lower than the center line surface roughness of the side surfaces 121S and the lower surface 121B of the first circuit pattern 121. At this time, in the process of etching the seed layer of the first circuit pattern 121, the side surface 121S and the lower surface 121B of the first circuit pattern 121 are covered with the first insulating layer 111 and are not etched.

Meanwhile, in an embodiment, the side surfaces and the lower surface of the circuit patterns other than the first circuit pattern 121 may have the same center line surface roughness (Ra).

For example, the side surface 122S and the lower surface 122B of the second circuit pattern 122 may have the same center line surface roughness (Ra). This is because the process of removing the seed layer of the second circuit pattern 122 is performed before the additional insulating layer is laminated, and it is not necessary to perform a soft etching process such as the first circuit pattern 121 with respect to the lower surface 121B of the first circuit pattern 121.

Accordingly, the side surface 122S and the lower surface 122B of the second circuit pattern 122 may have a center line surface roughness (Ra) corresponding to the side surface 121S of the first circuit pattern 121. The correspondence may mean that the center line surface roughness (Ra) of the side surface 122S and the lower surface 122B of the second circuit pattern 122 is the same as the center line surface roughness (Ra) of the side surface 121S of the first circuit pattern 121. In contrast, the correspondence may mean that the center line surface roughness (Ra) of the side surface 122S and the lower surface 122B of the second circuit pattern 122 has a range between 97% and 103% of the center line surface roughness (Ra) of the side surface 121S of the first circuit pattern 121. That is, the center line surface roughness (Ra) of the side surface 122S and the lower surface 122B of the corresponding representation second circuit pattern 122 is the same as or almost no different from the center line surface roughness (Ra) of the side surface 121S of the first circuit pattern 121.

As described above, the embodiment allows additional pretreatment processing (e.g., soft etching processing) to be performed only on the lower surface 121B of the first circuit pattern 121 after the first circuit pattern 121 is formed by the ETS method, and thus, AOI of the lower surface of the first circuit pattern 121 is possible. Accordingly, the side surface 121S and the lower surface 121B of the first circuit pattern 121 in the embodiment may have different center line surface roughness (Ra).

In addition, in the embodiment, unlike the first circuit pattern 121, the second circuit pattern 122 other than the first circuit pattern 121 does not require a soft etching process. Therefore, unlike the first circuit pattern 121, the side surface 122s of the second circuit pattern 122 and the lower surface 122b of the second circuit pattern 122 may have the same center line surface roughness (Ra).

The circuit board in the embodiment is disposed on the uppermost side and includes a first circuit pattern embedded in an insulating layer. At this time, the first circuit pattern includes an upper surface, a side surface, and a lower surface. In addition, the side surfaces and the lower surface of the first circuit pattern may be covered with an insulating layer. In addition, the side surfaces and the lower surface of the first circuit pattern in the embodiment may have different center line surface roughness (Ra). For example, the lower surface of the first circuit pattern may have a center line surface roughness (Ra) greater than that of the side surface of the first circuit pattern. This may be due to the additional soft etch process being performed during the formation process of the first circuit pattern to perform AOI on the lower surface of the first circuit pattern. Thus, embodiments may allow AOI to be performed on a lower surface of the first circuit pattern before removing the seed layer of the first circuit pattern and after forming the first circuit pattern. Therefore, the AOI accuracy of the first circuit pattern can be improved, and the inspection efficiency can be improved.

Hereinafter, a method of manufacturing a circuit board and a method of inspecting a circuit board according to the second embodiment will be described. Specifically, hereinafter, the manufacturing method of the circuit board shown in fig. 9 will be described in the process order.

Referring to fig. 12, in an embodiment, a base material for manufacturing a circuit board may be prepared using an ETS method.

For example, in an embodiment, the carrier plate 310 may be prepared with a carrier insulating layer 311 and a metal layer 312 disposed on at least one surface of the carrier insulating layer 311. At this time, the metal layer 312 may be disposed on only one of the first surface and the second surface of the carrier insulating layer 311, or may be disposed on both surfaces. For example, the metal layer 312 is provided only on one surface of the carrier insulating layer 311, and thus, the ETS process for manufacturing a circuit board may be performed only on the one surface. Or the metal layer 312 may be disposed on both surfaces of the carrier insulating layer 311, and thus, ETS processing for manufacturing a circuit board may be simultaneously performed on both surfaces of the carrier board 311. In this case, two circuit boards can be manufactured at a time.

The metal layer 312 may be formed by electroless plating on the carrier insulating layer 311. In contrast, the carrier insulating layer 311 and the metal layer 312 may be CCLs (copper clad laminates).

Next, referring to fig. 13, the embodiment performs a process of forming a first dry film 320 on the metal layer 312. At this time, the first dry film 320 may be disposed to entirely cover the metal layer 312. Next, the embodiment may perform a process of exposing and developing the formed first dry film 320.

Specifically, the embodiment may perform a process of forming an opening 321 overlapping in a vertical direction with a region where the first circuit pattern 121 is to be formed among the surface of the metal layer 312 by performing a process of exposing and developing the first dry film 320.

The opening 321 may be formed on the surface of the metal layer 312 to correspond to a region where the first circuit pattern 121 is to be formed.

At this time, the embodiment may perform a process of curing the first dry film 320 in which the opening 321 is formed by exposure and development.

For example, in an embodiment, the first dry film 320 may be cured using ultraviolet rays in a range of 5mV to 100 mV. Or embodiments may perform infrared thermal curing of the first dry film 320.

As described above, the embodiment further performs a process of curing the first dry film 320, so that the adhesiveness between the metal layer 312 and the first dry film 320 may be improved. Accordingly, the embodiment can improve the bonding strength between the first dry film 320 and the metal layer 312, and can miniaturize the first circuit pattern 121 formed in the opening 321. For example, the embodiment may further perform a process of curing the first dry film 320 to reduce the line width and the interval of the trace of the first circuit pattern 121. In addition, the embodiment may further perform a process of curing the first dry film 320 to allow a space between the traces of the first circuit pattern 121 to be smaller than a line width of the traces.

Next, referring to fig. 14, the embodiment may perform a process of forming the first circuit pattern 121 by forming a plating layer in the opening 321 of the cured first dry film 320 using the metal layer 312 as a seed layer.

Thereafter, in an embodiment, the first dry film 320 is not removed immediately after the first circuit pattern 121 is formed. Accordingly, in an embodiment, the AOI of the first circuit pattern 121 is performed while the first dry film 320 is laminated.

For this reason, referring to fig. 15, in an embodiment, a soft etching process may be performed on the lower surface 121B of the first circuit pattern 121 overlapped with the first dry film 320 in the vertical direction using the soft etching apparatus 300. Thus, after the soft etching process is performed, the side surface 121S of the first circuit pattern 121 covered by the first dry film 320 and the lower surface of the first circuit pattern 121 have different center line surface roughness (Ra).

The lower surface 121B of the first circuit pattern 121 is given a certain level of center line surface roughness (Ra) by a soft etching process, so that oxides formed on the surface can be removed.

Thus, referring to fig. 16, an embodiment may perform AOI on the lower surface 121B of the first circuit pattern 121 that is soft etched using the AOI device 400 while providing the first dry film 320.

Next, when the AOI is completed, a process of removing the first dry film 320 may be performed, as shown in fig. 17.

Next, the embodiment may perform a pretreatment process on the side surface 121S and the lower surface 121B of the first circuit pattern 121.

At this time, the side surface 121S and the lower surface (121B) of the first circuit pattern 121 before the pretreatment have different center line surface roughness (Ra), and the side surface 121S and the lower surface 121B of the first circuit pattern 121 after the pretreatment have different center line surface roughness (Ra).

Next, in an embodiment, as shown in fig. 18, a first insulating layer 111 covering the first circuit pattern 121 may be formed on the metal layer 312.

Next, referring to fig. 19, the embodiment may perform a process of forming a via VH in the first insulating layer 111. The Via Hole (VH) may be formed by laser processing, but is not limited thereto.

Next, referring to fig. 20, the embodiment may perform a process of forming the first through portion 131 and the second circuit pattern 122.

Specifically, the embodiment may perform a process of forming a seed layer on the lower surface of the first insulating layer 111 and the inner wall of the via hole VH, and a process of forming the second circuit pattern 122 and the first through portion 131 by performing electrolytic plating using the seed layer.

Next, as shown in fig. 21, in the embodiment, the stacking process may be performed by repeating the processes shown in fig. 18 to 20.

Specifically, the embodiment may perform a process of forming the second insulating layer 112 covering the second circuit pattern 122 on the lower surface of the first insulating layer 111. Next, the embodiment may perform a process of forming the second penetration portion 132 penetrating the second insulating layer 112 and a process of forming the third circuit pattern 123 protruding from the lower surface of the second insulating layer 112.

Next, as shown in fig. 22, in the embodiment, additional stacking processing may be performed by repeating the processing shown in fig. 21.

Specifically, the embodiment may perform a process of forming the third insulating layer 113 covering the third circuit pattern 123 on the lower surface of the second insulating layer 112. Next, the embodiment may perform a process of forming the third penetration portion 133 penetrating the third insulating layer 113 and a process of forming the fourth circuit pattern 124 protruding from the lower surface of the third insulating layer 113.

Next, as shown in fig. 23, the embodiment may perform a process of removing the carrier plate from the circuit board manufactured as described above. For example, a process may be performed to separate the carrier insulating layer 311 and the metal layer 312 of the carrier plate 310 from each other.

Next, as shown in fig. 24, the embodiment may perform a process of etching and removing the metal layer 312 remaining on the upper surface of the first insulating layer 111 of the circuit board. Thus, the embodiment may allow the upper surface of the first insulating layer 111 disposed on the uppermost side of the circuit board to be exposed.

At this time, after the metal layer 312 is removed, the upper surface of the first insulating layer 111 may be located on the same plane as the upper surface 121T of the first circuit pattern 121.

In contrast, after the metal layer 312 is removed, the upper surface of the first insulating layer 111 may be located higher than the upper surface 121T of the first circuit pattern 121.

At this time, when the metal layer 312 is removed, a portion of the first circuit pattern 121 may be removed together such that the upper surface 121T of the first circuit pattern 121 has a lower center line surface roughness (Ra) than the side surfaces 121S and the lower surface 121B of the first circuit pattern 121.

Next, as shown in fig. 25, the embodiment may perform a process of forming the first protective layer 140 on the upper surface of the first insulating layer 111 and a process of forming the second protective layer 150 having an opening on the lower surface of the third insulating layer 113.

Features, structures, effects, and the like described in the above-described embodiment are included in at least one embodiment, and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, and the like shown in each embodiment may be combined or modified for other embodiments by those of ordinary skill in the art to which the embodiment belongs. Accordingly, matters related to such combinations and variations are to be interpreted as being included within the scope of the embodiments.

In the foregoing, the embodiments have been mainly described, but this is merely an example and not a limitation of the embodiments, and it will be understood by those of ordinary skill in the art to which the embodiments pertain that various modifications and applications not shown above are possible without departing from the essential features of the embodiments. For example, each of the components specifically shown in the embodiments may be realized by modification. And differences related to such modifications and applications should be construed as being included in the scope of the embodiments set forth in the appended claims.

Claims

1. A circuit board, comprising:

a first insulating layer including an upper surface and a lower surface; and

A first circuit pattern embedded at the upper surface of the first insulating layer,

Wherein the upper surface of the first insulating layer includes a portion that does not overlap the first circuit pattern in a vertical direction, and

Wherein the portion of the upper surface of the first insulating layer has a step.

2. The circuit board of claim 1, wherein the portion of the first insulating layer comprises a recessed portion having a height that decreases as the recessed portion moves away from the first circuit pattern in a horizontal direction.

3. The circuit board of claim 1, wherein at least a portion of the first insulating layer is located at a position higher than an upper surface of the first circuit pattern.

4. The circuit board of claim 1, wherein a centerline surface roughness (Ra) of the upper surface of the first insulating layer is different from a centerline surface roughness (Ra) of the upper surface of the first circuit pattern.

5. The circuit board of claim 4, wherein the centerline surface roughness (Ra) of the upper surface of the first insulating layer ranges between 0.01 μιη to 0.5 μιη.

6. The circuit board according to claim 4, wherein the first insulating layer is an uppermost insulating layer provided at an uppermost side among a plurality of insulating layers, and

Wherein at least a portion of an upper surface of the first circuit pattern does not overlap with the upper surface of the first insulating layer in a vertical direction.

7. The circuit board of claim 4, wherein the first insulating layer includes a cavity overlapping the first circuit pattern in a vertical direction,

Wherein the cavity comprises:

An inner surface in contact with a side surface of the first circuit pattern, an

A bottom surface in contact with a lower surface of the first circuit pattern,

Wherein a center line surface roughness (Ra) of the upper surface of the first insulating layer is different from a center line surface roughness (Ra) of the inner surface of the cavity and a center line surface roughness (Ra) of the bottom surface of the cavity.

8. The circuit board of claim 7, wherein the centerline surface roughness (Ra) of the inner surface of the cavity is the same as the centerline surface roughness (Ra) of the bottom surface of the cavity.

9. The circuit board of claim 7, wherein the centerline surface roughness (Ra) of the upper surface of the first insulating layer is less than the centerline surface roughness (Ra) of the inner surface of the cavity and the centerline surface roughness (Ra) of the bottom surface of the cavity.

10. The circuit board of claim 4, wherein a centerline surface roughness (Ra) of the upper surface of the first insulating layer is less than a centerline surface roughness (Ra) of a lower surface of the first insulating layer.