KR20230040822A - Circuit board and package substrate having the same - Google Patents

Abstract

A circuit board according to an embodiment comprises: a first insulation layer; a first circuit pattern layer disposed on the first insulation layer; and a second insulation layer disposed on the first insulation layer and the first circuit pattern layer and comprising a cavity, wherein the first circuit pattern layer comprises a first pad part vertically overlapping the cavity wherein a chip mounted thereon and a connection part connected to the first pad part, and the connection part comprises a first part vertically overlapping the cavity and a second part that does not overlap vertically with the cavity. Therefore, the present invention is capable of providing the circuit board of a new structure.

Description

Circuit board and package substrate including the same {CIRCUIT BOARD AND PACKAGE SUBSTRATE HAVING THE SAME}

The embodiment relates to a circuit board and a package board including the circuit board.

As high-performance electric/electronic products progress, technologies for attaching a larger number of packages to a substrate of a limited size have been proposed and researched. However, since a general package is based on mounting one semiconductor chip, there is a limit to obtaining desired performance.

A typical package substrate has a form in which a processor package on which a processor chip is disposed and a memory package on which a memory chip is attached are connected as one. Such a package substrate has the advantage of reducing the mounting area of the chip and enabling high-speed signals through a short path by manufacturing a processor chip and a memory chip in one integrated package.

Due to these advantages, the above package substrate is widely applied to mobile devices and the like.

On the other hand, recently, the size of a package has been increased due to the high specification of electronic devices such as mobile devices and the adoption of HBM (High Bandwidth Memory), and accordingly, a package substrate including an interposer is mainly used. At this time, the interposer is composed of a silicon substrate.

However, in the case of an interposer such as a silicon substrate, not only the material cost for manufacturing the interposer is high, but also the formation of a TSV (Through Silicon Via) is complicated and expensive.

In addition, conventionally, a substrate including a silicon-based interconnect bridge is used as a package substrate. However, in the case of a silicon-based interconnect bridge, there is a reliability issue due to a Coefficient of Thermal Expansion (CTE) mismatch between the silicon material of the bridge and the organic material of the substrate, and there is a problem in that power integrity characteristics are deteriorated.

In the embodiment, it is possible to provide a circuit board having a new structure and a package board including the circuit board.

In addition, in the embodiment, it is possible to provide a circuit board having a slim structure and a package substrate including the circuit board.

In addition, an embodiment is intended to provide a circuit board capable of forming a cavity without including a stop layer and a package substrate including the circuit board.

In addition, the embodiment aims to provide a circuit board capable of minimizing the length of a signal connection line connected to a device and a package substrate including the circuit board.

The technical tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks not mentioned are clear to those skilled in the art from the description below to which the proposed embodiment belongs. will be understandable.

A circuit board according to an embodiment includes a first insulating layer; a first circuit pattern layer disposed on the first insulating layer; a second insulating layer disposed on the first insulating layer and the first circuit pattern layer and including a cavity, the first circuit pattern layer vertically overlapping the cavity, and mounting a chip; 1 pad part; and a connection portion connected to the first pad portion, wherein the connection portion includes: a first portion vertically overlapping the cavity; and a second portion that does not vertically overlap the cavity.

Also, a width of the first pad part is greater than a width of the connection part, and the connection part includes a trace.

In addition, the first circuit pattern layer includes a second pad portion that does not vertically overlap the cavity, one end of the first portion of the connection portion directly contacts the first pad portion, and the second portion of the connection portion One end of is in direct contact with the second pad part.

In addition, the second insulating layer including the cavity has an inclined surface whose width gradually decreases toward the first insulating layer.

In addition, the connecting portion vertically overlaps the inclined surface of the second insulating layer.

The inclined surface of the second insulating layer may include an overlapping region vertically overlapping the first circuit pattern layer including the connecting portion; and a non-overlapping area that does not vertically overlap the first circuit pattern layer.

Also, the first and second portions of the connection portion are positioned on the same plane, and an upper surface of the second portion of the connection portion is covered with the second insulating layer.

In addition, the first insulating layer includes a first insulating material, and the second insulating layer includes a second insulating material different from the first insulating material.

In addition, the first insulating layer includes prepreg, and the second insulating layer includes photoimageable dielectics (PID).

In addition, the circuit board may include a first conductive coupling part disposed on the first pad part; and a chip disposed on the first conductive coupling part.

In addition, the circuit board may include a second circuit pattern layer disposed on the second insulating layer; and a second conductive coupling portion disposed on the second circuit pattern layer, wherein an uppermost portion of the second conductive coupling portion is lower than an uppermost portion of the element.

In addition, the first insulating layer and the second insulating layer include the same first insulating material, the first insulating material includes photoimageable dielectics (PID), and the bottom surface of the cavity includes the first pad portion. It is located higher than the lower surface and is located lower than the upper surface of the first pad part.

In addition, the first circuit pattern layer protrudes above the top surface of the first insulating layer, and the second insulating layer vertically overlaps the cavity and includes a supporting insulating part disposed between the first pad part and the connection part. include

In addition, the thickness of the supporting insulation part satisfies a range between 20% and 95% of the thickness of the first circuit pattern layer.

In addition, the circuit board includes a third insulating layer disposed under the second insulating layer, the third insulating layer includes a second insulating material different from the first and second insulating layers, and the second insulating layer The insulating material includes prepreg.

Meanwhile, a package substrate according to an embodiment includes a first circuit board including a first cavity; and a second circuit board including a second cavity vertically overlapping the first cavity and coupled to the first circuit board, wherein the first circuit board includes: a first insulating layer; a first circuit pattern layer disposed on the first insulating layer; a second insulating layer disposed on the first insulating layer and the first circuit pattern layer and including the first cavity; a second circuit pattern layer disposed on the second insulating layer; and a first conductive coupling part disposed on the first circuit pattern layer vertically overlapping the first cavity; a processor chip disposed on the first conductive coupling part; and a second conductive coupling part disposed on the second circuit pattern layer and coupled to the second circuit board, wherein at least a portion of the processor chip is disposed in the second cavity.

In addition, the top of the processor chip is located higher than the top of the second conductive coupling part.

It may also include a third circuit board disposed on the second circuit board, the third circuit board including a memory chip, and the second circuit board between the first circuit board and the third circuit board. It is an interposer board that connects

Also, a memory chip mounted on the second circuit board is included, and the second circuit board is a memory board connected to the first circuit board.

In addition, the first cavity includes a 1-1 cavity and a 1-2 cavity spaced apart in a longitudinal direction or a width direction, and the processor chip includes a first processor chip disposed in the 1-1 cavity; a second processor chip disposed in the first-second cavity, wherein the first circuit pattern layer includes a connection part connecting the first processor chip and the second processor chip; A first portion vertically overlapping the -1 cavity and connected to the first processor chip, and a second portion vertically overlapping the 1-2 cavities and connected to the second processor chip; and a third portion directly connected between the second portions and covered with the second insulating layer between the first-first and first-second cavities.

In an embodiment, a first insulating layer and a second insulating layer are included. At this time, the second insulating layer includes a cavity. And, the second insulating layer includes a photosensitive material. Accordingly, the cavity may be formed by performing a photolithography process on the second insulating layer. At this time, in the embodiment, the cavity may be selectively formed only in the second insulating layer within a range in which the first insulating layer is not damaged even without a stop layer. At this time, a first circuit pattern layer is disposed between the first insulating layer and the second insulating layer. The first circuit pattern layer includes a first pad portion vertically overlapping the cavity and a second pad portion not vertically overlapping the cavity. Also, the first circuit pattern layer includes a connection part directly connecting the first pad part and the second pad part. The connection portion may refer to a trace of the first circuit pattern layer. One end of the connection part may be directly connected to the first pad part. In addition, the other end of the connection part may be directly connected to the second pad part.

Through this, the embodiment may have a structure in which the first pad part and the second pad part are directly connected to each other through the connection part, thereby improving signal transmission characteristics or operational reliability.

For example, in the Comparative Example, a stop layer is required to form a cavity, and accordingly, a connection portion as in the Example cannot be formed. Accordingly, in the comparative example, at least two penetration electrodes were required to connect the first pad part and the second pad part. For example, in the comparative example, a gap between the first pad part and the second pad part is used by using a first through electrode vertically overlapping the first pad part and a second through electrode vertically overlapping the second pad part. are connected to each other Accordingly, in the comparative example, compared to the embodiment, in order to connect between the first pad part and the second pad part, a signal path including the first through electrode and the second through electrode must additionally exist. There is a problem in that the signal line between the first pad part and the second pad part increases.

In contrast, in the embodiment, the first pad part 131 and the second pad part may be directly connected using the connection part. Through this, in the embodiment, it is possible to minimize the signal transmission distance between the first pad part and the second pad part. Accordingly, in the embodiment, a separate through electrode for connecting the first pad part and the second pad part is unnecessary, and accordingly, an additional circuit pattern layer can be disposed in a space corresponding to the through electrode. Circuit integration can be improved.

In addition, in the embodiment, a signal transmission distance between the first pad part and the second pad part corresponds to the distance of the connection part. Through this, in the embodiment, compared to the comparative example, it is possible to reduce the distance corresponding to the path including at least two through electrodes in the signal transmission distance, and accordingly, the signal transmission distance between the first pad part and the second pad part. can be minimized. Furthermore, in the embodiment, as the signal transmission distance between the first pad part and the second pad part is reduced, the effect of noise that increases in proportion to the signal transmission distance can be minimized. Accordingly, in the embodiment, signal transmission characteristics between the first pad part and the second pad part may be improved, and furthermore, operation reliability of the circuit board may be improved.

Also, in the embodiment, the connection part corresponds to a trace that is a fine pattern connecting between the first pad part and the second pad part. In this case, when the connection part vertically overlaps the cavity in a structure in which the connection part protrudes from the upper surface of the first insulating layer, a physical reliability problem in which the connection part collapses may occur due to various factors. At this time, in the embodiment, a supporting insulating part, which is a part of the second insulating layer, is formed in a region vertically overlapping the cavity. In addition to protecting the upper surface of the first insulating layer, the support insulating part may serve to protect the first pad part and the connection part vertically overlapping the cavity. That is, in the embodiment, the connection part is supported in a region vertically overlapping the cavity by using the supporting insulation part, and through this, a physical reliability problem such as collapsing of the connection part can be solved.

Meanwhile, in the embodiment, as a chip is mounted on a circuit board including a cavity, the height of the circuit board can be reduced by the depth of the cavity, and thus the overall thickness of the package board can be reduced.

In addition, in the embodiment, in a structure of a package substrate in which different substrates are connected to each other, cavities vertically overlapping each substrate are formed. Also, the chips mounted on the package substrate may be respectively disposed in cavities respectively formed in the different substrates. For example, a portion of the chip may be disposed in a first cavity formed on a first circuit board, and a remaining portion may be disposed in a second cavity formed on a second circuit board. Through this, in the embodiment, the overall thickness of the package substrate can be reduced.

1 is a cross-sectional view illustrating a package substrate according to a comparative example.
2 is a cross-sectional view showing a circuit board according to the first embodiment.
FIG. 3A is a plan view of the circuit board of FIG. 2 with some components removed.
FIG. 3B is a plan view illustrating the first circuit pattern layer in a state in which the second insulating layer is disposed in FIG. 3A.
4A is a cross-sectional view of a circuit board including a cavity of the first comparative example.
Figure 4b is a plan view of the circuit board of Figure 4a.
4C is a cross-sectional view of a circuit board including a cavity of a second comparative example.
5A is a diagram illustrating a circuit board according to a second embodiment.
FIG. 5B is a cross-sectional view of the circuit board of FIG. 5A in the AA′ direction of FIG. 3B.
6 is a diagram illustrating a circuit board according to a third embodiment.
7 is a view illustrating a first package substrate according to an embodiment.
8 is a view illustrating a second package substrate according to an embodiment.
9 is a view illustrating a third package substrate according to an embodiment.
10 is a view illustrating a fourth package substrate according to an embodiment.
11A to 11J are diagrams illustrating a manufacturing method of the circuit board shown in FIG. 2 in order of processes.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

However, the technical idea of the present invention is not limited to some of the described embodiments, but may be implemented in a variety of different forms, and if it is within the scope of the technical idea of the present invention, one or more of the components among the embodiments can be selectively implemented. can be used by combining and substituting.

In addition, terms (including technical and scientific terms) used in the embodiments of the present invention, unless explicitly specifically defined and described, can be generally understood by those of ordinary skill in the art to which the present invention belongs. It can be interpreted as meaning, and commonly used terms, such as terms defined in a dictionary, can be interpreted in consideration of contextual meanings of related technologies. In addition, terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention.

In this specification, the singular form may also include the plural form unless otherwise specified in the phrase, and when described as "at least one (or more than one) of A and (and) B and C", A, B, and C are combined. may include one or more of all possible combinations. Also, terms such as first, second, A, B, (a), and (b) may be used to describe components of an embodiment of the present invention.

These terms are only used to distinguish the component from other components, and the term is not limited to the nature, order, or order of the corresponding component. And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, the component is not only directly connected to, combined with, or connected to the other component, but also with the component. It may also include the case of being 'connected', 'combined', or 'connected' due to another component between the other components.

In addition, when it is described as being formed or disposed on the "top (above) or bottom (bottom)" of each component, the top (top) or bottom (bottom) is not only a case where two components are in direct contact with each other, but also one A case in which another component above is formed or disposed between two components is also included. In addition, when expressed as "up (up) or down (down)", it may include the meaning of not only an upward direction but also a downward direction based on one component.

-Comparison example-

1 is a cross-sectional view illustrating a package substrate according to a comparative example.

Referring to FIG. 1 , in the comparison example, at least two packages are required to transmit signals to the main board of the electronic device.

A package substrate included in the electronic device of Comparative Example may be in a state in which at least two or more packages are combined.

A package substrate according to the comparative example includes a first package 10 and a second package 20 .

The first package 10 is a processor package in which the processor chip 12 is mounted. And, the second package 20 is a memory package in which the memory chip 23 is mounted.

The first package 10 includes a first substrate 11 on which a processor chip 12 is mounted. The first substrate 11 has a multilayer structure, and includes one side where the processor chip 12 is disposed and the other side where the first adhesive ball 16 is disposed. The first package 10 has a fan-out structure and is attached to a main board (not shown) of an electronic device using first adhesive balls 16 disposed on the other side.

A processor chip 12 is mounted on the first substrate 11 . The processor chip 12 is an integrated processor chip in which various functions are integrated. Accordingly, the size of the processor chip 12 increases in proportion to the number of functions provided. That is, the first board 11 has the processor chip 12 mounted thereon, and has a function of connecting the processor chip 12 and the main mode of the electronic device.

Meanwhile, the first package 10 of the comparative example further includes a second substrate 15 . The second substrate 15 is an interposer interconnecting the first package 10 and the second package 20 .

That is, the package substrate in the comparative example essentially includes an interposer like the second substrate 15 . And, the package substrate in the comparative example has a problem in that the total volume increases in proportion to the thickness of the interposer. Accordingly, in the package substrate of the comparative example, the thickness of the electronic device increases, and thus there is a limit to slimming.

In addition, the package substrate in the comparative example has a problem in that the length of the signal transmission line increases as the first package 10 and the second package 20 are interconnected using the second substrate 15. there is. That is, in the package substrate of the comparative example, in order to transmit signals of the processor chip 12 and signals of the memory chip 23 to each other, at least the second substrate 15 must pass through, and accordingly, the second substrate ( Corresponding to the length of the signal transmission line in 15), the signal transmission distance between the processor chip 12 and the memory chip 23 increases. Accordingly, in the comparative example, high-speed communication between the processor chip 12 and the memory chip 23 is difficult due to the second substrate 15 . Furthermore, in the comparative example, as the signal transmission distance by the second substrate 15 increases, it is vulnerable to noise and thus has a problem in that communication performance decreases.

Meanwhile, in the first package 10 of the comparative example, the second adhesive ball 13 disposed on the first substrate 11 and the first adhesive ball 13 and the processor chip 12 are molded. A molding layer 14 is included. At this time, the first molding layer 14 protects the processor chip 12 and the second adhesive ball 13 . Accordingly, the thickness of the first molding layer 14 is determined by the heights of the processor chip 12 and the second adhesive ball 13 . However, in the comparative example, the second substrate 15 is additionally disposed on the first molding layer 14, and thus the thickness of the first molding layer 14 is affected by the second substrate 15. It should also be taken into account, which has a problem of increasing the thickness.

In addition, the second package 20 of the comparative example includes a third substrate 22 , a memory chip 23 and a second molding layer 24 disposed on the third substrate 22 .

As described above, in the comparative example, at least three substrates are required to electrically connect the processor chip 12 and the memory chip 23 to each other. In addition, in the comparative example, a process for bonding at least three substrates to each other is required, resulting in an increase in the number of manufacturing processes and a decrease in yield due to complexity. Specifically, in the comparative example, at least three substrates are required because of the difficulty of arranging different chips on one substrate.

Also, in the comparative example, at least two bonding balls are required to bond at least three substrates together.

That is, in the comparative example, the second adhesive ball 13 for connecting the first substrate 11 and the second substrate 15 and the third adhesive ball 13 for connecting the second substrate 15 and the third substrate 22 A glue ball (21) is required. Accordingly, since the package substrate according to the comparative example requires at least two or more adhesive balls for mutual bonding of a plurality of substrates, the reliability of the package substrate may be deteriorated due to poor connection of the adhesive balls. In addition, the two or more adhesive balls have a structure in which they are disposed in the thickness direction, and the thickness of the package substrate and, further, the thickness of the electronic device increases by the thickness of the adhesive balls.

Specifically, the first thickness t1 of the first substrate 11 is 120 μm to 150 μm. The second thickness t2 including the first molding layer 14, the processor chip 12, and the second adhesive ball 13 is 145 μm to 160 μm. In addition, the third thickness t3 of the second substrate 15 is 90 μm to 110 μm. In addition, the fourth thickness t4 of the first adhesive ball 16 is 130 μm to 150 μm.

Accordingly, the total thickness t8 of the first package 10 including the first to fourth thicknesses t1 , t2 , t3 , and t4 is 480 μm to 550 μm.

In addition, the fifth thickness t5 of the third adhesive ball 21 is 145 μm to 180 μm. Also, the sixth thickness t6 of the third substrate 22 is 90 μm to 110 μm. In addition, the seventh thickness t7 including the memory chip 23 and the second molding layer 24 is 370 μm to 400 μm. Accordingly, the total thickness t9 of the second package 20 including the fifth to seventh thicknesses t5 , t6 , and t7 is 610 μm to 700 μm. Therefore, the total thickness of the package substrate of the comparative example has 1100 μm or more.

Meanwhile, due to recent slimming of electronic devices, the required thickness of the package substrate is 1100 μm or less. Also, in recent years, the type of electronic device is mainly made up of foldable products, and due to the characteristics of the foldable product, restrictions in the length direction are small, while restrictions in the thickness direction are large. However, since the package substrate of the comparative example has a structure in which a plurality of substrates are bonded to each other via a plurality of adhesive balls in the thickness direction, there is a problem in that the specifications required by the electronic device are not satisfied.

In addition, as high-performance electric/electronic products have recently progressed, technologies for attaching a larger number of packages to a substrate of a limited size have been studied, and thus miniaturization of circuit patterns is required. However, in the case of the package substrate of the comparative example, there is a limit to miniaturization of the circuit pattern. The circuit pattern included in the package substrate of the comparative example has a line width of at least 10 μm or more and a spacing of 10 μm or more. In addition, with the recent increase in functions processed by an application processor (AP), it is becoming difficult to implement them with a single chip. However, in the case of the circuit pattern provided in the comparison example, it is difficult to mount two application processors (APs) having different functions on the one first board 11 .

Embodiments are intended to solve the problems of these comparative examples, and provide a circuit board having a novel structure on which a plurality of application processor chips can be mounted on one board and a package board including the circuit board.

Furthermore, the embodiment is to solve the problems of these comparative examples, and to provide a circuit board having a new structure on which an application processor chip and a memory chip can be mounted side by side and a package substrate including the same. .

-Electronic device-

Prior to the description of the embodiment, an electronic device including the package substrate of the embodiment will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and/or electrically connected to various components. For example, the main board may be connected to the package substrate of the embodiment. Various chips may be mounted on the package substrate. Broadly, the package substrate includes memory chips such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), and flash memory, a central processor (eg, CPU), a graphic processor (eg, GPU), Application processor chips such as digital signal processors, cryptographic processors, microprocessors and microcontrollers, and logic chips such as analog-to-digital converters and application-specific ICs (ASICs) may be mounted.

In addition, the embodiment provides a package substrate capable of mounting at least two chips of different types on one substrate while reducing the thickness of the package substrate connected to the main board of the electronic device.

At this time, the electronic device includes a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, and a computer. ), a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, and the like. However, it is not limited thereto, and may be any other electronic device that processes data in addition to these.

embodiment

Hereinafter, a circuit board according to an embodiment and a package substrate including the circuit board will be described in detail.

2 is a cross-sectional view showing a circuit board according to the first embodiment, FIG. 3A is a plan view in which some components are removed from the circuit board of FIG. 2, and FIG. 3B is a second insulating layer disposed in FIG. 3A. It is a plan view showing one circuit pattern layer, and FIG. 4A is a cross-sectional view of the circuit board including the cavity of the first comparative example. FIG. 4B is a plan view of the circuit board of FIG. 4A, and FIG. 4C is a cross-sectional view of the circuit board including the cavity of the second comparative example.

Hereinafter, a circuit board including a cavity according to an embodiment will be described in detail with reference to FIGS. 2 to 4C .

The circuit board of the embodiment includes a plurality of insulating layers. Here, each of the plurality of insulating layers may have a single-layer structure, or may be composed of a plurality of layers differently.

Specifically, the circuit board includes a first insulating layer 110 and a second insulating layer 120 .

The first insulating layer 110 may have a single layer structure as shown in FIG. 2, or may have a plurality of layer structure differently.

In addition, the second insulating layer 120 is disposed on the first insulating layer 110 . And, the second insulating layer 120 may have a single-layer structure, or may have a plurality of layer structure differently.

In the first embodiment, the first insulating layer 110 and the second insulating layer 120 may include different insulating materials.

For example, the first insulating layer 110 may include a first insulating material, and the second insulating layer 120 may include a second insulating material different from that of the first insulating layer 110 .

For example, the first insulating material constituting the first insulating layer 110 may include prepreg (PPG). The prepreg may be formed by impregnating a fiber layer in the form of a fabric sheet, such as a glass fabric woven with glass yarn, with an epoxy resin, and then performing thermal compression. However, the embodiment is not limited thereto, and the prepreg constituting the first insulating layer 110 may include a fiber layer in the form of a fabric sheet woven with carbon fiber threads.

The first insulating layer 110 may include a resin and reinforcing fibers disposed in the resin. The resin may be an epoxy resin, but is not limited thereto. The resin is not particularly limited to an epoxy resin, and for example, one or more epoxy groups may be included in the molecule, two or more epoxy groups may be included, and, alternatively, four or more epoxy groups may be included. In addition, the resin of the first insulating layer 110 may include a naphthalene group, and may be, for example, an aromatic amine type, but is not limited thereto. For example, the resin is bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol S type epoxy resin, phenol novolak type epoxy resin, alkylphenol novolak type epoxy resin, biphenyl type epoxy resin, aralkyl type epoxy Resins, dicyclopentadiene type epoxy resins, naphthalene type epoxy resins, naphthol type epoxy resins, epoxy resins of condensates of phenols and aromatic aldehydes having a phenolic hydroxyl group, biphenyl aralkyl type epoxy resins, fluorene type epoxies resins, xanthene-type epoxy resins, triglycidyl isocyanurate, rubber-modified epoxy resins, and phosphorous-type epoxy resins; naphthalene-type epoxy resins, bisphenol A-type epoxy resins, and phenol novolac epoxy resins; , cresol novolak epoxy resins, rubber-modified epoxy resins, and phosphorus-based epoxy resins. In addition, the reinforcing fibers may be glass fibers, carbon fibers, aramid fibers (eg, aramid-based organic materials), nylon, silica-based inorganic materials, or titania-based inorganic materials. can The reinforcing fibers may be arranged to cross each other in a planar direction within the resin.

Meanwhile, glass fibers, carbon fibers, aramid fibers (eg, aramid-based organic materials), nylon, silica-based inorganic materials, or titania-based inorganic materials may be used.

A second insulating material constituting the second insulating layer 120 is different from the first insulating material. For example, the second insulating layer 120 may include a photosensitive material. For example, the second insulating material constituting the second insulating layer 120 may include PID (Photo Imagable Dielectric). However, the embodiment is not limited thereto, and the second insulating material constituting the second insulating layer 120 may be a through hole (not shown) for forming a through electrode through a photolithography process, or an element. Any photosensitive material capable of forming a cavity for mounting may be included therein.

Each of the first insulating layer 110 and the second insulating layer 120 may have a thickness ranging from 10 μm to 60 μm. For example, each of the first insulating layer 110 and the second insulating layer 120 may have a thickness ranging from 15 μm to 55 μm. For example, each of the first insulating layer 110 and the second insulating layer 120 may have a thickness ranging from 20 μm to 50 μm. If the thickness of the first insulating layer 110 and the second insulating layer 120 is less than 10 μm, the circuit pattern layer included in the circuit board may not be stably protected. If each thickness of the first insulating layer 110 and the second insulating layer 120 exceeds 60 μm, the overall thickness of the circuit board may increase. In addition, when the thickness of each of the first insulating layer 110 and the second insulating layer 120 exceeds 60 μm, the thickness of the circuit pattern layer or through electrode increases correspondingly, and through the circuit pattern accordingly The loss of the transmitted signal may increase.

In this case, the thicknesses of the first insulating layer 110 and the second insulating layer 120 may correspond to a distance in a thickness direction between circuit pattern layers disposed on different layers.

For example, the thickness of the first insulating layer 110 may mean a straight line distance between the lower surface of the first circuit pattern layer 130 and the upper surface of the third circuit pattern layer 150 . For example, the thickness of the second insulating layer 120 may mean a straight line distance between the upper surface of the first circuit pattern layer 130 and the lower surface of the second circuit pattern layer 140 .

The first insulating layer 110 may refer to an uppermost insulating layer disposed adjacent to the uppermost side of the circuit board. In addition, the second insulating layer 120 may refer to a lowermost insulating layer disposed adjacent to the lowermost side of the circuit board.

In an embodiment, circuit pattern layers are disposed on surfaces of the first insulating layer 110 and the second insulating layer 120 .

For example, the first circuit pattern layer 130 may be disposed between the upper surface of the first insulating layer 110 and the lower surface of the second insulating layer 120 . For example, the second circuit pattern layer 140 may be disposed on the upper surface of the second insulating layer 120 . For example, the third circuit pattern layer 150 may be disposed on the lower surface of the first insulating layer 110 .

The first circuit pattern layer 130 may be disposed within the first insulating layer 110 . For example, at least a portion of the first circuit pattern layer 130 may be disposed within the first insulating layer 110 . For example, at least a portion of a side surface of the first circuit pattern layer 130 may be covered with the first insulating layer 110 .

The second circuit pattern layer 140 may protrude from the upper surface of the second insulating layer 120 . The second circuit pattern layer 140 may refer to an uppermost circuit pattern layer disposed on the uppermost side of the circuit board.

The third circuit pattern layer 150 may protrude below the lower surface of the first insulating layer 110 . The third circuit pattern layer 150 may refer to a lowermost circuit pattern layer disposed on the lowermost side of the circuit board.

Each of the first circuit pattern layer 130 , the second circuit pattern layer 140 , and the third circuit pattern layer 150 may include pads and traces according to their functions. The pad may be a mounting pad on which a device or chip is mounted or a terminal pad connected to an external board. The trace may be a long signal wiring line connecting a plurality of pads. The trace is a fine pattern having a width smaller than that of the pad. For example, the interval between the plurality of traces in the embodiment may range from 2 μm to 15 μm, and the line width of each trace may range from 2 μm to 15 μm. And, the pad of the first circuit pattern layer 130 may correspond to the first pattern part and the second pattern part described below. In addition, the trace of the first circuit pattern layer 130 may mean a connection part described below. This will be described in more detail below.

The circuit pattern layers as described above are made of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). can be formed In addition, the circuit pattern layers are at least one selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which have excellent bonding strength. It may be formed of a paste containing a metal material or a solder paste. Preferably, the first circuit pattern layer 130, the second circuit pattern layer 140, and the third circuit pattern layer 150 may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

Each of the first circuit pattern layer 130 , the second circuit pattern layer 140 , and the third circuit pattern layer 150 may have a thickness ranging from 5 μm to 20 μm. For example, each of the first circuit pattern layer 130 , the second circuit pattern layer 140 , and the third circuit pattern layer 150 may have a thickness ranging from 6 μm to 17 μm. Each of the first circuit pattern layer 130 , the second circuit pattern layer 140 , and the third circuit pattern layer 150 may have a thickness ranging from 7 μm to 16 μm.

When the thickness of each of the first circuit pattern layer 130, the second circuit pattern layer 140, and the third circuit pattern layer 150 is less than 5 μm, the resistance of the circuit pattern increases, resulting in signal transmission efficiency this may decrease For example, when the thickness of each of the first circuit pattern layer 130, the second circuit pattern layer 140, and the third circuit pattern layer 150 is less than 5 μm, signal transmission loss may increase. For example, when the thickness of each of the first circuit pattern layer 130, the second circuit pattern layer 140, and the third circuit pattern layer 150 exceeds 20 μm, the line width of the circuit patterns increases. Accordingly, the overall volume of the circuit board may increase.

The first circuit pattern layer 130, the second circuit pattern layer 140, and the third circuit pattern layer 150 are formed by an additive process, a subtractive process (which is a typical printed circuit board manufacturing process) Subtractive Process), MSAP (Modified Semi Additive Process) and SAP (Semi Additive Process) methods, etc., and detailed descriptions are omitted here.

The circuit board of the embodiment includes a through electrode. The through electrode may serve to electrically connect circuit pattern layers disposed on different layers to each other. The through electrode may also be referred to as a 'via'.

The penetration electrode penetrates the first insulating layer 110 and the second insulating layer 120 included in the circuit board, and thus, circuit patterns disposed on different layers can be electrically connected. In this case, the through electrode may be formed to pass through only one insulating layer, or may be formed to pass through at least two or more insulating layers in common.

For example, the circuit board includes the first through electrode V1. The first through electrode V1 may be formed to pass through the first insulating layer 110 . The first through electrode V1 may electrically connect the first circuit pattern layer 130 and the third circuit pattern layer 150 to each other. For example, an upper surface of the first through electrode V1 may be directly connected to a lower surface of the first circuit pattern layer 130 . For example, the lower surface of the first through electrode V1 may be directly connected to the third circuit pattern layer 150 .

Accordingly, the first circuit pattern layer 130 and the third circuit pattern layer 150 may be electrically connected to each other through the first through electrode V1 to transmit signals.

For example, the circuit board includes the second through electrode V2. The second through electrode V2 may be formed to pass through the second insulating layer 120 . The second through electrode V2 may electrically connect the first circuit pattern layer 130 and the second circuit pattern layer 140 to each other. For example, the lower surface of the second through electrode V2 may be directly connected to the first circuit pattern layer 130 . For example, an upper surface of the second through electrode V2 may be directly connected to the second circuit pattern layer 140 . Accordingly, the first circuit pattern layer 130 and the second circuit pattern layer 140 may be directly electrically connected to each other through the second through electrode V2 to transmit signals.

The first through electrode V1 and the second through electrode V2 form a through hole penetrating the first insulating layer 110 and the second insulating layer 120, and the inside of the formed through hole is made of a conductive material. It can be formed by filling with

The through hole may be formed by any one of mechanical processing, laser processing, and chemical processing. When the through hole is formed by machining, methods such as milling, drilling, and routing may be used, and when the through hole is formed by laser processing, a UV or CO ₂ laser method may be used. In the case of forming by chemical processing, at least one insulating layer among the plurality of insulating layers may be opened using a chemical containing aminosilane, ketones, or the like.

On the other hand, the laser processing is a cutting method that melts and evaporates a part of the material by concentrating optical energy on the surface to take a desired shape, and can easily process complex formations by computer programs, and other methods Even difficult composite materials can be machined.

In addition, the processing by the laser can cut a diameter of up to a minimum of 0.005 mm, and has the advantage of a wide range of processable thickness.

As the laser processing drill, it is preferable to use a YAG (Yttrium Aluminum Garnet) laser, a CO ₂ laser, or an ultraviolet (UV) laser. The YAG laser is a laser capable of processing both the copper foil layer and the insulating layer, and the CO ₂ laser is a laser capable of processing only the insulating layer.

When the through hole is formed, the inside of the through hole may be filled with a conductive material to form the first through electrode V1 and the second through electrode V2. Metal materials forming the first through electrode V1 and the second through electrode V2 are copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). ), and the conductive material filling is any one of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, ink jetting and dispensing Alternatively, a combination of these methods may be used.

Meanwhile, the circuit board of the embodiment may include a first protective layer 160 and a second protective layer 170 . The first protective layer 160 and the second protective layer 170 may be disposed on the outermost side of the circuit board.

For example, the first protective layer 160 may be disposed on the first outermost or lowermost side of the circuit board. For example, the first protective layer 160 may be disposed on the lower surface of the first insulating layer 110 .

For example, the second protective layer 170 may be disposed on the second outermost or uppermost side of the circuit board. For example, the second protective layer 170 may be disposed on the upper surface of the second insulating layer 120 .

The first protective layer 160 may include at least one opening (not shown). For example, the first protective layer 160 may include an opening vertically overlapping at least one of the third circuit pattern layers 150 . For example, the first protective layer 160 may include an opening vertically overlapping a terminal pad (not shown) of the third circuit pattern layer 150 where a conductive coupling part for connection with an external substrate is disposed. there is.

The second protective layer 170 may include at least one opening (not shown). For example, the second protective layer 170 may include an opening vertically overlapping at least one of the second circuit pattern layers 140 . For example, the second passivation layer 170 has an opening vertically overlapping a terminal pad (not shown) of the second circuit pattern layer 140 where a conductive bonding portion for connection with a memory substrate or an interposer substrate is disposed. can include

The first protective layer 160 and the second protective layer 170 may include an insulating material. The first protective layer 160 and the second protective layer 170 may include various materials that can be cured by heating after being applied to protect the surfaces of the insulating layers and the circuit pattern layers. The first protective layer 160 and the second protective layer 170 may be resist layers. For example, the first protective layer 160 and the second protective layer 170 may be solder resist layers including organic polymer materials. For example, the first protective layer 160 and the second protective layer 170 may include an epoxy acrylate-based resin. In detail, the first protective layer 160 and the second protective layer 170 may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, and the like. However, the embodiment is not limited thereto, and the first protective layer 160 and the second protective layer 170 may be any one of a photo solder resist layer, a cover-lay, and a polymer material. am.

The thickness of the first protective layer 160 and the second protective layer 170 may be 1 μm to 20 μm. The thickness of the first protective layer 160 and the second protective layer 170 may be 1 μm to 15 μm. For example, the thickness of the first protective layer 160 and the second protective layer 170 may be 5 μm to 20 μm. When the thickness of the first protective layer 160 and the second protective layer 170 exceeds 20 μm, the thickness of the circuit board may increase. When the thickness of the first protective layer 160 and the second protective layer 170 is less than 1 μm, electrical reliability or physical reliability may deteriorate due to the circuit pattern layers included in the circuit board not being stably protected. .

At this time, although not shown in the drawings, surface treatment layers (not shown) may be disposed in the openings of the first protective layer 160 and the second protective layer 170, respectively. The surface treatment layer includes a third circuit pattern layer 150 vertically overlapping the opening of the first protective layer 160 and a second circuit pattern layer vertically overlapping the opening of the second protective layer 170 ( 140) may be formed to improve soldering characteristics while preventing corrosion and oxidation of the surface.

The surface treatment layer may be an organic solderability preservative (OSP) layer. For example, the surface treatment layer may be an organic layer formed of an organic material such as benzimidazole.

However, embodiments are not limited thereto. For example, the surface treatment layer may be a plating layer. For example, the surface treatment layer may include at least one of a nickel (Ni) plating layer, a palladium (Pd) plating layer, and a gold (Au) plating layer.

Meanwhile, in the embodiment, the second insulating layer 120 may include a cavity 121 . The cavity 121 may pass through upper and lower surfaces of the second insulating layer 120 . The cavity 121 may vertically overlap the first circuit pattern layer 130 disposed on the top surface of the first insulating layer 110 .

The cavity 121 may be formed through a photolithography process. For example, the cavity 121 may be formed through an exposure and development process of the second insulating layer 120 .

Accordingly, in the embodiment, the stop layer required for forming the cavity 121 may be removed. For example, in the comparative example, a cavity is formed through a laser process, and accordingly, a stop layer for forming the cavity is required.

For example, first describing the comparison example, the circuit board according to the first comparison example includes a cavity C as shown in FIG. 4A . The circuit board according to Comparative Example 1 has a structure penetrating at least one insulating layer among a plurality of insulating layers, and a cavity C is formed.

Specifically, the circuit board of Comparative Example 1 includes a first insulating layer 10a and a second insulating layer 20a disposed on the first insulating layer 10a. And, the cavity (C) is formed penetrating the second insulating layer (20a). In addition, the circuit board includes a circuit pattern layer disposed on the surface of the insulating layer. For example, the circuit board includes a first circuit pattern layer 30a disposed on an upper surface of the first insulating layer 10a. In addition, the circuit board includes a second circuit pattern layer 40a disposed on the lower surface of the first insulating layer 10a. In addition, the circuit board includes a third circuit pattern layer 50a disposed on the upper surface of the second insulating layer 20a. In addition, the circuit board includes a penetration electrode 60a penetrating the first insulating layer 10a. The penetration electrode 60a electrically connects the first circuit pattern layer 30a disposed on the upper surface of the first insulating layer 10a and the second circuit pattern layer 40a disposed on the lower surface of the first insulating layer 10a.

The upper surface of the first insulating layer 10a includes a first region R1 vertically overlapping the cavity C and a second region R2 excluding the first region. Also, the first circuit pattern layer 30a may be disposed in the first region and the second region of the first insulating layer 10 , respectively.

At this time, in the first comparative example, the cavity C penetrating the second insulating layer 20a may be formed using a stop layer (not shown).

Accordingly, the first circuit pattern layer 30a includes the pad part 32a disposed in the first region on the upper surface of the first insulating layer 10a, and the second circuit pattern layer 32a on the upper surface of the first insulating layer 10a. and a stop pattern 34a disposed in the region. The stop pattern 34a may be disposed in a boundary region between the first region and the second region on the upper surface of the first insulating layer 10 . For example, the stop pattern 34a may be disposed in the second region of the upper surface of the first insulating layer 10a, and a side surface may constitute a part of an inner wall of the cavity C. For example, the cavity C of the first comparative example may include a first inner wall including the second insulating layer 20a and a second inner wall including the stop pattern 34a.

At this time, as shown in FIG. 4B , in the first comparative example, the stop pattern 34a is disposed on the upper surface of the first insulating layer 10a, surrounding the boundary region between the first and second regions. Accordingly, the first comparative example includes a process of forming a stop layer to form the cavity C and a process of forming the stop pattern 34a by removing the stop layer, and the manufacturing process accordingly is complicated. There is a problem with the cancellation. In addition, in the first comparative example, in the etching process of removing the stop layer, there is a problem in that a part of the pad part 32a of the first circuit pattern layer 30a is also etched, and accordingly, the pad part 32a There is a problem that deformation of occurs. Also, in the first comparative example, when the pad part 32a is deformed, a reliability problem may occur in which a connection part such as a solder ball is not stably seated on the pad part 32a.

Further, in the first comparative example, the pad part 32a in the first region on the upper surface of the first insulating layer 10a is another pattern part disposed on the second region on the upper surface of the first insulating layer 10a ( 36a), there is a problem that cannot be directly connected. For example, in the first comparative example, a stop pattern 34a is disposed in a boundary region corresponding to the cavity C. Accordingly, when there is a connection part such as a trace T connecting the pad part 32a and the pattern part 36, the trace T comes into electrical contact with the stop pattern 34a. Electrical reliability problems may occur. For example, in the first comparison example, when there are at least two or more traces T, a problem in that the traces T are electrically connected to each other by the stop pattern 34a may occur. Thus, a short circuit problem may occur due to the pad parts to be electrically separated from each other electrically connected to each other by the stop pattern 34a.

Accordingly, in the first comparative example, the pad part 32a and the pattern part 36a have a structure in which they are connected through a through electrode 60a, rather than a structure in which they are directly connected to each other through a trace. Therefore, in the first comparative example, since the pad part 32a and the pattern part 36a do not have a structure in which they are directly connected to each other on the upper surface of the first insulating layer 10a, the signal transmission line between them There is a problem in that the length of the signal transmission line is increased, and as the length of the signal transmission line is increased, there is a problem in that signal transmission loss increases due to vulnerability to noise.

Also, as shown in FIG. 4C , in the second comparative example, the widths of the stop layer and the cavity C are equal to each other so that the stop pattern 34a is not left on the circuit board. However, due to process errors in the laser process, it is not easy to form the cavity (C) to substantially correspond to the width of the stop layer, and when the width of the stop layer is greater than the width of the cavity (C), There is a problem that part of the stop pattern 34a as shown in FIG. 4a remains. In addition, in the second comparison example, when the width of the stop layer is smaller than the width of the cavity C, the cavity C is also formed in an area where the stop layer is not disposed, and thus the first insulating layer There is a problem that the recessed portion 10r is formed on the upper surface of (10a). In addition, the recessed portion 10r has a problem in that damage occurs to the second circuit pattern layer 40a disposed on the lower surface of the first insulating layer 10a, and thus electrical reliability or physical reliability problems may occur. can

In contrast, in the embodiment, the second insulating layer 120 is made of a photosensitive material as described above, and thus the cavity 121 penetrating the second insulating layer 120 is formed through a photolithography process rather than a laser process. form

Accordingly, in the embodiment, in the first circuit pattern layer 130, a pattern portion vertically overlapping with the cavity 121 and a pattern portion not vertically overlapping with the cavity 121 may be directly connected to each other. there is.

For example, referring to FIG. 3A , the upper surface of the first insulating layer 110 in the embodiment includes a first region R1 vertically overlapping the cavity 121 and the first region R1. It may include the excluded second region R2.

The first region R1 vertically overlaps the cavity 121, and thus may refer to an element arrangement region in which elements to be mounted on the circuit board of the embodiment are disposed.

The second region R2 does not vertically overlap the cavity 121 . Accordingly, the second region R2 of the first insulating layer 110 and the first circuit pattern layer 130 disposed on the second region R2 may be covered with the second insulating layer 120. can

In this case, the first circuit pattern layer 130 in the embodiment may be disposed on the first region R1 and the second region R2 of the first insulating layer 110, respectively.

For example, the first circuit pattern layer 130 may include a first pad part 131 disposed in the first region R1 of the first insulating layer 110 . For example, the first pad part 131 may mean a mounting pad on which a device is to be mounted among the first circuit pattern layer 130 . For example, the first pad part 131 vertically overlaps the cavity 121 , and thus may be disposed within the cavity 121 .

The first circuit pattern layer 130 according to the embodiment may include a second pad part 133 disposed in the second region R2 of the first insulating layer 110 . The second pad part 133 is disposed in the second region R2 of the first insulating layer 110, and thus the upper surface may be covered by the second insulating layer 120.

The second pad part 133 may mean a via pad. For example, the second pad part 133 does not vertically overlap the cavity 121 .

At this time, in the first and second comparative examples, the first pad part 131 and the second pad part 133 do not have a structure in which they are directly connected to each other. For example, in the first and second comparison examples, the first pad part 131 and the second pad part 133 do not have a structure in which they are directly connected to each other through traces of the first circuit pattern layer 130. couldn't This is because, as described with reference to FIGS. 4A to 4C , when a cavity is formed using a laser, a stop pattern is disposed in a region vertically overlapping an inclined surface of the cavity. For example, in the comparative example, stop patterns are disposed in all regions vertically overlapping the inclined surface of the cavity. Accordingly, in the comparative example, a trace that directly connects the first pad part and the second pad part to each other by the stop pattern cannot be disposed.

In contrast, in the embodiment, the cavity 121 is formed in the second insulating layer 120 made of a photosensitive material by using a photolithography process. Accordingly, in the embodiment, the stop layer required to form the cavity 121 in the second insulating layer 120 may be removed. Accordingly, in the embodiment, a connection part 132 directly connecting the first pad part 131 and the second pad part 133 may be included.

The connection part 132 may mean a trace of the first circuit pattern layer 130 .

Accordingly, the connection part 132 may have a width smaller than the width of the first pad part 131 or the width of the second pad part 133 .

One end of the connection part 132 may be directly connected to the first pad part 131 . Also, the other end of the connection part 132 may be directly connected to the second pad part 133 .

Through this, the embodiment may have a structure in which the first pad part 131 and the second pad part 133 are directly connected to each other through the connection part 132 .

For example, in the comparative example, at least two penetration electrodes are required to connect the first pad part and the second pad part. For example, in the comparative example, a gap between the first pad part and the second pad part is used by using a first through electrode vertically overlapping the first pad part and a second through electrode vertically overlapping the second pad part. are connected to each other Accordingly, in the comparative example, compared to the embodiment, in order to connect between the first pad part and the second pad part, a signal path including the first through electrode and the second through electrode must additionally exist. There is a problem in that the signal line between the first pad part and the second pad part increases.

In contrast, in the embodiment, the first pad part 131 and the second pad part 133 may be directly connected using the connection part 132 . Through this, in the embodiment, the signal transmission distance between the first pad part 131 and the second pad part 133 can be minimized. Accordingly, in the embodiment, a separate through-electrode for connecting the first pad part 131 and the second pad part 133 is unnecessary, and accordingly, an additional circuit pattern layer is disposed in a space corresponding to the through-electrode. is possible, and through this, the degree of integration of the circuit can be improved.

Also, in the embodiment, a signal transfer distance between the first pad part 131 and the second pad part 133 corresponds to the distance of the connection part 132 . Through this, in the embodiment, compared to the comparative example, it is possible to reduce the distance corresponding to the path including at least two through electrodes in the signal transmission distance, and accordingly, the first pad part 131 and the second pad part 133 ) can be minimized. Furthermore, in the embodiment, as the signal transmission distance between the first pad part 131 and the second pad part 133 is reduced, the influence of noise that increases in proportion to the signal transmission distance can be minimized. Accordingly, in the embodiment, signal transfer characteristics between the first pad part 131 and the second pad part 133 can be improved, and furthermore, the operation reliability of the circuit board can be improved.

Meanwhile, the connection part 132 may be divided into a plurality of parts. At this time, the division of the connection part 132 into a plurality of parts is only a division according to the arrangement area, and does not mean that one connection part is divided into a plurality of parts separated from each other.

For example, the connection part 132 may include a first part 132 - 1 disposed adjacent to the first pad part 131 .

One end of the first part 132 - 1 of the connection part 132 may be directly connected to the first pad part 131 . The first part 132 - 1 of the connection part 132 may vertically overlap the cavity 121 .

Also, the connection part 132 may include a second part 132 - 2 disposed adjacent to the second pad part 133 .

The second part 132 - 2 of the connection part 132 is connected to the other end of the first part 132 - 1 , and one end may be directly connected to the second pad part 133 . The second part 132 - 2 of the connection part 132 may be covered with the second insulating layer 120 .

At least a portion of the connection portion 132 may vertically overlap the inclined surface 121S of the second insulating layer 120 including the cavity 121 . For example, the boundary between the first part 132-1 and the second part 132-2 of the connection part 132 is the inclined surface 121S of the second insulating layer 120 including the cavity 121. ) and can be vertically overlapped.

That is, the cavity 121 may include an inclined surface 121S whose width gradually decreases toward the upper surface of the first insulating layer 110 . In addition, the inclined surface 121S of the second insulating layer 120 including the cavity 121 may vertically overlap at least a portion of the connection portion 132 .

At this time, even in the comparative example, although there is a pattern layer vertically overlapping the inclined surface of the cavity, the pattern layer in the comparative example is a dummy pattern electrically separated (or insulated) from the first pad part or the second pad part ( For example, a stop pattern). In contrast, the connection portion 132 vertically overlapping the cavity in the embodiment is not a dummy pattern, but a wiring layer directly connecting the first pad portion 131 and the second pad portion 133.

Furthermore, in the comparative example, the pattern layer vertically overlaps the entire inclined surface of the cavity. Specifically, in the comparative example, the pattern layer is disposed in all regions vertically overlapping the inclined surface.

In contrast, in the embodiment, the connecting portion 132 may be disposed only in some areas among areas vertically overlapping the inclined surface 121S.

For example, as shown in FIGS. 3A and 3B , the first pad part 131 includes a plurality of first pads. And, the second pad part 133 includes a plurality of second pads. Also, the connection part 132 includes a plurality of connection parts respectively connecting a plurality of first pads and a plurality of second pads. And, the plurality of connection parts may be spaced apart from each other by a predetermined interval. Through this, a part of the inclined surface 121S of the second insulating layer 120 including the cavity 121 in the embodiment vertically overlaps the connection part 132 of the first circuit pattern layer 130, , at least a portion of the remaining portion may not vertically overlap the first circuit pattern layer 130 .

On the other hand, in the embodiment, the reason why the connection unit 132 can be configured as described above is that the second insulating layer 120 is made of a photosensitive material, and thus the second insulating layer ( This is because the cavity 121 is formed in 120. In this case, the first insulating layer 110 includes an insulating material different from that of the second insulating layer 120 . Accordingly, in the photolithography process for forming the cavity 121 in the second insulating layer 120, the first insulating layer 110 is not removed. Accordingly, in the embodiment, the cavity 121 passing through only the second insulating layer 120 may be formed.

In an embodiment, a first insulating layer and a second insulating layer are included. At this time, the second insulating layer includes a cavity. And, the second insulating layer includes a photosensitive material. Accordingly, the cavity may be formed by performing a photolithography process on the second insulating layer. At this time, in the embodiment, the cavity may be selectively formed only in the second insulating layer within a range in which the first insulating layer is not damaged even without a stop layer. At this time, a first circuit pattern layer is disposed between the first insulating layer and the second insulating layer. The first circuit pattern layer includes a first pad portion vertically overlapping the cavity and a second pad portion not vertically overlapping the cavity. Also, the first circuit pattern layer includes a connection part directly connecting the first pad part and the second pad part. The connection portion may refer to a trace of the first circuit pattern layer. One end of the connection part may be directly connected to the first pad part. In addition, the other end of the connection part may be directly connected to the second pad part.

Through this, the embodiment may have a structure in which the first pad part and the second pad part are directly connected to each other through the connection part, thereby improving signal transmission characteristics or operational reliability.

For example, in the Comparative Example, a stop layer is required to form a cavity, and accordingly, a connection portion as in the Example cannot be formed. Accordingly, in the comparative example, at least two penetration electrodes were required to connect the first pad part and the second pad part. For example, in the comparative example, a gap between the first pad part and the second pad part is used by using a first through electrode vertically overlapping the first pad part and a second through electrode vertically overlapping the second pad part. are connected to each other Accordingly, in the comparative example, compared to the embodiment, in order to connect between the first pad part and the second pad part, a signal path including the first through electrode and the second through electrode must additionally exist. There is a problem in that the signal line between the first pad part and the second pad part increases.

In contrast, in the embodiment, the first pad part 131 and the second pad part may be directly connected using the connection part. Through this, in the embodiment, it is possible to minimize the signal transmission distance between the first pad part and the second pad part. Accordingly, in the embodiment, a separate through electrode for connecting the first pad part and the second pad part is unnecessary, and accordingly, an additional circuit pattern layer can be disposed in a space corresponding to the through electrode. Circuit integration can be improved.

In addition, in the embodiment, a signal transmission distance between the first pad part and the second pad part corresponds to the distance of the connection part. Through this, in the embodiment, compared to the comparative example, it is possible to reduce the distance corresponding to the path including at least two through electrodes in the signal transmission distance, and accordingly, the signal transmission distance between the first pad part and the second pad part. can be minimized. Furthermore, in the embodiment, as the signal transmission distance between the first pad part and the second pad part is reduced, the effect of noise that increases in proportion to the signal transmission distance can be minimized. Accordingly, in the embodiment, signal transmission characteristics between the first pad part and the second pad part may be improved, and furthermore, operation reliability of the circuit board may be improved.

FIG. 5A is a diagram illustrating a circuit board according to the second embodiment, and FIG. 5B is a cross-sectional view of the circuit board of FIG. 5A taken in the direction A-A′ of FIG. 3B.

5A and 5B, the circuit board according to the second embodiment has a structure similar to that of the circuit board according to the first embodiment of FIG. 1 The position of the circuit pattern layer may be different.

Specifically, the circuit board according to the second embodiment includes a first insulating layer 210, a second insulating layer 220, a first circuit pattern layer 230, a second circuit pattern layer 240, and a third circuit pattern. A layer 250 , a first through electrode V1 , a second through electrode V2 , a first passivation layer 260 and a second passivation layer 270 may be included.

In the second embodiment, the first insulating layer 210 may include the same insulating material as the second insulating layer 220 .

For example, the first insulating layer 210 may include a photosensitive material that is the same insulating material as the second insulating layer 220 .

And, in the embodiment, the cavity 221 is formed by processing some of the insulating layers of the photosensitive material composed of a plurality of layers.

In this case, when the first insulating layer 210 and the second insulating layer 220 include the same material, the circuit board may be manufactured through an embedded trace substrate (ETS) method.

Accordingly, the first circuit pattern layer 230 may protrude above the top surface of the first insulating layer 210 .

In this case, in the embodiment, the first insulating layer 210 and the second insulating layer 220 include the same photosensitive material, and only the second insulating layer 220 is selectively processed to form a cavity 221. form

Here, in the embodiment, only the second insulating layer 220 is selectively processed from among the first insulating layer 210 and the second insulating layer 220 through a thinning method. The thinning method may mean a method of reducing the thickness of the unexposed and uncured region by unexposed and uncured regions to be processed.

At this time, in the embodiment, it is difficult to selectively process only the second insulating layer 220 from among the first insulating layer 210 and the second insulating layer 220 using the thinning method. Accordingly, in the embodiment, in the process of forming the cavity 221 in the second insulating layer 220, the second insulating layer 220 is not processed through the entirety of the second insulating layer 220, and only a part thereof is processed. Control process conditions and process time.

Accordingly, the bottom surface of the cavity 221 of the second insulating layer 220 in the embodiment may be positioned higher than the bottom surface of the first circuit pattern layer 230 .

For example, in the embodiment, the bottom surface of the cavity 221 of the second insulating layer 220 in a region vertically overlapping the cavity 221 is higher than the bottom surface of the first circuit pattern layer 230, It is positioned lower than the upper surface of the first circuit pattern layer 230 .

For example, in the embodiment, the second insulating layer 220 vertically overlaps the cavity 221 and may include a supporting insulating portion 220B. Also, an upper surface of the supporting insulating portion 220B may correspond to a bottom surface of the cavity 221 of the second insulating layer 220 .

The supporting insulating part 220B may be disposed between the first circuit pattern layers 230 in a region vertically overlapping the cavity 221 .

That is, in the second embodiment, the first circuit pattern layer 230 protrudes from the upper surface of the first insulating layer 210 . Also, the cavity 221 of the second insulating layer 220 may be formed in a structure that does not pass through the second insulating layer 221 .

For example, the first circuit pattern layer 230 includes a first pad part 231 and a connection part 232 vertically overlapping the cavity 221 .

In this case, each of the first pad part 231 and the connection part 232 may be configured in plurality.

And, as shown in FIGS. 5A and 5B , the support insulation part 220B is disposed between a plurality of first pad parts, between a plurality of connection parts, and between at least one first pad part and at least one connection part. It can be.

In this case, the supporting insulating part 220B may function to protect the first insulating layer 210 in the process of processing the cavity 221 .

Also, the connection part 232 corresponds to a trace that is a fine pattern connecting between the first pad part 231 and the second pad part 233 . In this case, when the connection part 232 vertically overlaps the cavity 221 in a structure protruding above the upper surface of the first insulating layer 210, the physical reliability of the connection part 232 collapses due to various factors. Problems can arise. At this time, in the embodiment, a supporting insulating portion 220B, which is a part of the second insulating layer 220, is formed in a region vertically overlapping the cavity 221. In addition to protecting the upper surface of the first insulating layer 210, the supporting insulating part 220B protects the first pad part 231 and the connection part 232 vertically overlapping with the cavity 221. function can be performed. For example, the connection part 232 may be supported by the support insulation part 220B in a region vertically overlapping the cavity 221, and thus, a physical reliability problem such as collapsing may be solved.

Meanwhile, the thickness of the supporting insulation part 220B may be in the range of 20% to 95% of the thickness of the first circuit pattern layer 230 . For example, the thickness of the supporting insulating portion 220B may range from 25% to 90% of the thickness of the first circuit pattern layer 230 . For example, the thickness of the supporting insulation portion 220B may be 30% to 85% of the thickness of the first circuit pattern layer 230 .

When the thickness of the supporting insulating part 220B is less than 20% of the thickness of the first circuit pattern layer 230, the first insulating layer 210 Even when the cavity 221 is formed, a problem may occur. When the thickness of the support insulation part 220B is less than 20% of the thickness of the first circuit pattern layer 230, the connection part 232 is not stably supported in a region vertically overlapping the cavity 221. A problem may occur, and through this, a physical reliability problem such as collapsing of the connection part may occur due to various factors.

When the thickness of the support insulation portion 220B exceeds 95% of the thickness of the first circuit pattern layer 230, the support insulation portion 220B A problem may occur in which at least a part of the upper surface of the first pad part 231 is covered, and accordingly, an electrical reliability problem in which an electrical connection with a device mounted on the first pad part 231 is not normally made may occur. can happen

6 is a diagram illustrating a circuit board according to a third embodiment.

Referring to FIG. 6 , the circuit board according to the third embodiment has a structure similar to that of the circuit board according to the second embodiment of FIG. 5 , except that a third insulating layer is additionally included.

Specifically, the circuit board according to the third embodiment includes a first insulating layer 310, a second insulating layer 320, a third insulating layer 380, a first circuit pattern layer 330, and a second circuit pattern layer. 340, a third circuit pattern layer 350, a fourth circuit pattern layer 390, a first through electrode V1, a second through electrode V2, a third through electrode V3, and a first protective layer (260) and a second protective layer (270).

In the third embodiment, the first insulating layer 310 may include the same insulating material as the second insulating layer 320 . For example, the first insulating layer 310 may include a photosensitive material that is the same insulating material as the second insulating layer 320 .

Meanwhile, the third insulating layer 380 is disposed on the lower surface of the first insulating layer 310 .

The third insulating layer 380 may include an insulating material different from that of the first insulating layer 310 . For example, the third insulating layer 380 may include prepreg. Specifically, in the circuit board, when the insulating layer is made of only a photosensitive material, a problem may occur in the rigidity of the circuit board, and furthermore, bending characteristics may be deteriorated. This is because a component such as glass fiber does not exist in the insulating layer including the photosensitive material.

Accordingly, in the embodiment, the third insulating layer 380 is additionally disposed under the first insulating layer 310 to improve the rigidity and bending characteristics of the circuit board.

Hereinafter, a package substrate according to an embodiment will be described.

7 is a view illustrating a first package substrate according to an embodiment.

Referring to FIG. 7 , the first package substrate includes a first circuit board.

The first circuit board may refer to the circuit board shown in any one of FIGS. 2 , 5 and 6 . Hereinafter, description will be made on the assumption that the first circuit board is the circuit board shown in FIG. 2 . However, the embodiment is not limited thereto, and the first circuit board may be composed of any one circuit board of FIGS. 5 and 6 .

The first package substrate includes a first conductive coupling part 410 disposed on the first pad part 131 of the first circuit board.

The first conductive coupling part 410 may be disposed on each of the plurality of first pad parts 131 of the first circuit board.

The first conductive coupling part 410 may have a spherical shape. For example, the cross section of the first conductive coupling part 410 may include a circular shape or a semicircular shape. For example, the cross section of the first conductive coupling part 410 may have a partially or entirely rounded shape. For example, the cross-sectional shape of the first conductive coupling part 410 may have a flat surface on one side and a curved surface on the other side. The first conductive coupling part 410 may be a solder ball, but is not limited thereto.

In an embodiment, a chip 420 or an element 420 disposed on the first conductive coupling part 410 may be included.

The chip 420 may be a processor chip. For example, the chip 420 may be an application processor (AP) chip of any one of a central processor (eg, CPU), a graphic processor (eg, GPU), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller. there is.

At this time, the lower surface of the chip 420 may include a terminal 425, and the terminal 425 connects to the first pad part 131 of the first circuit board through the first conductive coupling part 410. can be electrically connected.

Meanwhile, in the package substrate of the embodiment, a plurality of chips may be disposed on one circuit board while spaced apart from each other by a predetermined interval. For example, the chip 420 may include a first chip and a second chip spaced apart from each other.

For example, the first circuit board may include a plurality of cavities spaced apart in a width direction or a length direction. In addition, the first chip and the second chip may be respectively disposed in the plurality of cavities. At this time, at least one of the terminals of the first chip should be directly connected to at least one of the terminals of the second chip. At this time, the embodiment includes a connection part directly connected to the first pad part disposed in the cavity. In addition, a terminal of the first chip and a terminal of the second chip may be directly connected through the connection part. For example, the connection part may include a first portion vertically overlapping the first cavity in which the first chip is disposed, a second portion vertically overlapping the second cavity in which the second chip is disposed, and the first portion vertically overlapping the second cavity in which the second chip is disposed. It may include a third part that connects between the first part and the second part and does not vertically overlap the first and second cavities. Also, in the embodiment, a plurality of chips may be directly connected without through electrodes by using the structure of the connection unit.

Also, the first chip and the second chip may be application processor (AP) chips of different types.

Meanwhile, the first chip and the second chip may be spaced apart from each other by a predetermined distance on the circuit board. For example, the separation width between the first chip and the second chip may be 150 μm or less. For example, a separation width between the first chip and the second chip may be 120 μm or less. For example, a separation width between the first chip and the second chip may be 100 μm or less.

Preferably, for example, the spacing between the first chip and the second chip may have a range of 60 μm to 150 μm. For example, the distance between the first chip and the second chip may range from 70 μm to 120 μm. For example, the distance between the first chip and the second chip may range from 80 μm to 110 μm. For example, when the separation width between the first chip and the second chip is less than 60 μm, interference between the first chip and the second chip may cause the first chip or the second chip to deteriorate. Operational reliability problems may arise. For example, when the separation width between the first chip and the second chip is greater than 150 μm, signal transmission loss may increase as the distance between the first chip and the second chip increases.

Meanwhile, the first package substrate includes the second conductive bonding portion 430 disposed in the opening of the second protective layer 170 .

In this case, the second conductive coupling part 430 may be a solder ball, but is not limited thereto.

In an embodiment, the top of the second conductive coupling part 430 may be positioned lower than the top of the chip 420 .

For example, in the comparative example, the second conductive coupling part is used to couple the second circuit board to the first circuit board, and at this time, the second conductive coupling part is positioned higher than the chip. This is to prevent the chip 420 from being damaged by the second circuit board when the second circuit board is coupled.

In contrast, the second conductive coupling part 430 in the embodiment is located lower than the top of the chip 420 . And, in the embodiment, even if the second conductive coupling portion 430 is positioned lower than the chip 420, the chip 420 is coupled to the second circuit board on the second conductive coupling portion 430. ) can be prevented from being damaged.

Meanwhile, in the embodiment, a third conductive coupling part 440 disposed in the opening of the first protective layer 160 is included. The third conductive coupling part 440 may be for coupling the first package substrate and a main board (or motherboard) of an external device.

8 is a view illustrating a second package substrate according to an embodiment.

Referring to FIG. 8 , the second package substrate according to the embodiment further includes a second circuit board 500 coupled to the first package substrate of FIG. 7 .

The second circuit board 500 may be an interposer board.

The second circuit board 500 includes a plurality of insulating layers. For example, the second circuit board 500 may include a first insulating layer 510 and a second insulating layer 520 .

In addition, the second circuit board 500 may include circuit pattern layers 530 , 540 , and 550 disposed on surfaces of the first insulating layer 510 and the second insulating layer 520 . The circuit pattern layers 530 , 540 , and 550 of the second circuit board 500 may be formed to meet the terminal specifications between the first circuit board and a memory board (not shown). For example, the width or pitch of the pads of the second circuit pattern layers of the first circuit board may be different from the width or pitch of the pads of the memory substrate. Also, the second circuit board 500 may be disposed between the first circuit board having the above difference and the memory board to electrically connect them.

Meanwhile, the second circuit board 500 may include a second cavity 511 . In this case, the second cavity 511 of the second circuit board 500 may vertically overlap the cavity 121 of the first circuit board. For example, the second cavity 511 may be formed passing through the first insulating layer 510 of the second circuit board 500 facing the first circuit board.

In this case, at least a part of the chip 420 mounted on the first circuit board according to the embodiment may be disposed in the second cavity 511 of the second circuit board 500 . Accordingly, in the embodiment, the height of the second conductive coupling part 430 may be reduced by the depth corresponding to the second cavity 511, and thus the overall thickness of the second package substrate may be reduced.

Meanwhile, the first insulating layer 510 of the second circuit board 500 may include a prepreg or, differently, a PID of a photosensitive material. Also, when the first insulating layer 510 of the second circuit board 500 includes prepreg, the second cavity 511 may be formed through a laser process. Also, when the first insulating layer 510 of the second circuit board 500 includes a PID, the second cavity 511 may be formed through a photolithography process.

Accordingly, in the embodiment, in a package substrate structure in which different substrates are connected to each other, cavities vertically overlapping each substrate are formed. Also, the chips mounted on the package substrate may be respectively disposed in cavities respectively formed in the different substrates. For example, a portion of the chip may be disposed in a first cavity formed on a first circuit board, and a remaining portion may be disposed in a second cavity formed on a second circuit board. Through this, in the embodiment, the overall thickness of the package substrate can be reduced.

9 is a view illustrating a third package substrate according to an embodiment.

Referring to FIG. 9 , the third package substrate has a structure in which a memory substrate is additionally coupled to the second package substrate.

For example, the memory substrate includes an insulating layer 610 and circuit pattern layers 620 and 630 .

A memory chip 640 may be attached to the insulating layer 610 of the memory substrate. In this case, an adhesive layer (not shown) may be additionally disposed between the insulating layer 610 and the memory chip 640 .

Meanwhile, the memory substrate may include a connection member 650 electrically connecting the circuit pattern layers 620 and 630 and the terminal 645 of the memory chip 640 . The connection member 650 may be a wire, but is not limited thereto.

10 is a view illustrating a fourth package substrate according to an embodiment.

Referring to FIG. 10 , the fourth package substrate may have a structure in which a memory substrate is directly coupled to the first package substrate of FIG. 7 . For example, in the embodiment, the pad specification of the memory board corresponds to the pad specification of the first circuit board, and accordingly, a memory board serving as a second circuit board can be directly coupled to the first circuit board. do.

To this end, the memory substrate may include a plurality of insulating layers. The memory substrate may include a first insulating layer 710 and a second insulating layer 720 .

In addition, the memory substrate may include circuit pattern layers 730 , 740 , and 750 disposed on surfaces of the first insulating layer 710 and the second insulating layer 720 . The circuit pattern layers 730 , 740 , and 750 of the memory substrate may connect the chip 420 mounted on the first circuit board and the memory chip mounted on the memory board.

Meanwhile, the memory substrate may include a second cavity. In this case, the cavity of the memory substrate may vertically overlap the cavity 121 of the first circuit board. For example, the second cavity of the memory substrate may be formed through the first insulating layer 710 of the memory substrate facing the first circuit board.

In this case, at least a part of the chip 420 mounted on the first circuit board according to the embodiment may be disposed in the second cavity of the memory board. Accordingly, in the embodiment, the height of the second conductive coupling part 430 may be reduced by the depth corresponding to the second cavity, and thus the overall thickness of the fourth package substrate may be reduced.

Meanwhile, the first insulating layer 710 of the memory substrate may include a prepreg, or may include a PID of a photosensitive material differently. Also, when the first insulating layer 710 of the memory substrate includes prepreg, the second cavity may be formed through a laser process. Also, when the first insulating layer 710 of the memory substrate includes a PID, the second cavity may be formed through a photolithography process.

In an embodiment, a first insulating layer and a second insulating layer are included. At this time, the second insulating layer includes a cavity. And, the second insulating layer includes a photosensitive material. Accordingly, the cavity may be formed by performing a photolithography process on the second insulating layer. At this time, in the embodiment, the cavity may be selectively formed only in the second insulating layer within a range in which the first insulating layer is not damaged even without a stop layer. At this time, a first circuit pattern layer is disposed between the first insulating layer and the second insulating layer. The first circuit pattern layer includes a first pad portion vertically overlapping the cavity and a second pad portion not vertically overlapping the cavity. Also, the first circuit pattern layer includes a connection part directly connecting the first pad part and the second pad part. The connection portion may refer to a trace of the first circuit pattern layer. One end of the connection part may be directly connected to the first pad part. In addition, the other end of the connection part may be directly connected to the second pad part.

Through this, the embodiment may have a structure in which the first pad part and the second pad part are directly connected to each other through the connection part, thereby improving signal transmission characteristics or operational reliability.

For example, in the Comparative Example, a stop layer is required to form a cavity, and accordingly, a connection portion as in the Example cannot be formed. Accordingly, in the comparative example, at least two penetration electrodes were required to connect the first pad part and the second pad part. For example, in the comparative example, a gap between the first pad part and the second pad part is used by using a first through electrode vertically overlapping the first pad part and a second through electrode vertically overlapping the second pad part. are connected to each other Accordingly, in the comparative example, compared to the embodiment, in order to connect between the first pad part and the second pad part, a signal path including the first through electrode and the second through electrode must additionally exist. There is a problem in that the signal line between the first pad part and the second pad part increases.

In contrast, in the embodiment, the first pad part 131 and the second pad part may be directly connected using the connection part. Through this, in the embodiment, it is possible to minimize the signal transmission distance between the first pad part and the second pad part. Accordingly, in the embodiment, a separate through electrode for connecting the first pad part and the second pad part is unnecessary, and accordingly, an additional circuit pattern layer can be disposed in a space corresponding to the through electrode. Circuit integration can be improved.

In addition, in the embodiment, a signal transmission distance between the first pad part and the second pad part corresponds to the distance of the connection part. Through this, in the embodiment, compared to the comparative example, it is possible to reduce the distance corresponding to the path including at least two through electrodes in the signal transmission distance, and accordingly, the signal transmission distance between the first pad part and the second pad part. can be minimized. Furthermore, in the embodiment, as the signal transmission distance between the first pad part and the second pad part is reduced, the effect of noise that increases in proportion to the signal transmission distance can be minimized. Accordingly, in the embodiment, signal transmission characteristics between the first pad part and the second pad part may be improved, and furthermore, operation reliability of the circuit board may be improved.

Also, in the embodiment, the connection part corresponds to a trace that is a fine pattern connecting between the first pad part and the second pad part. In this case, when the connection part vertically overlaps the cavity in a structure in which the connection part protrudes from the upper surface of the first insulating layer, a physical reliability problem in which the connection part collapses may occur due to various factors. At this time, in the embodiment, a supporting insulating part, which is a part of the second insulating layer, is formed in a region vertically overlapping the cavity. In addition to protecting the upper surface of the first insulating layer, the support insulating part may serve to protect the first pad part and the connection part vertically overlapping the cavity. That is, in the embodiment, the connection part is supported in a region vertically overlapping the cavity by using the supporting insulation part, and through this, a physical reliability problem such as collapsing of the connection part can be solved.

Meanwhile, in the embodiment, as a chip is mounted on a circuit board including a cavity, the height of the circuit board can be reduced by the depth of the cavity, and thus the overall thickness of the package board can be reduced.

In addition, in the embodiment, in a structure of a package substrate in which different substrates are connected to each other, cavities vertically overlapping each substrate are formed. Also, the chips mounted on the package substrate may be respectively disposed in cavities respectively formed in the different substrates. For example, a portion of the chip may be disposed in a first cavity formed on a first circuit board, and a remaining portion may be disposed in a second cavity formed on a second circuit board. Through this, in the embodiment, the overall thickness of the package substrate can be reduced.

11A to 11J are diagrams illustrating a manufacturing method of the circuit board shown in FIG. 2 in order of processes.

Hereinafter, only the manufacturing method of the circuit board of FIG. 2 will be described. However, based on this method, the circuit board shown in FIG. 5 or 6 may be manufactured.

Referring to FIG. 11A , in an embodiment, basic materials for manufacturing a circuit board may be prepared. For example, in the embodiment, a carrier board may be prepared.

The carrier board may include a carrier insulating layer CB1 and a carrier metal layer CB2 disposed on at least one surface of the carrier insulating layer CB1. The carrier metal layer CB2 may be formed by electroless plating on the surface of the carrier insulating layer CB1.

Alternatively, the carrier board may be CCL (Copper Clad Laminate).

Next, as shown in FIG. 11B , in the embodiment, a process of applying a dry film DF1 to the lower surface of the carrier metal layer CB2 may be performed. Also, in the embodiment, a process of forming at least one opening in the dry film DF1 may be performed. For example, in the embodiment, a process of forming an opening vertically overlapping with a region where the first circuit pattern layer 130 is to be formed in the lower surface of the carrier metal layer CB2 may be performed on the dry film DF1. there is.

Thereafter, in the embodiment, a process of forming the first circuit pattern layer 130 in the opening of the dry film DF1 may be performed. For example, in the embodiment, the first circuit pattern layer 130 filling the opening of the dry film DF1 may be formed by electroplating the carrier metal layer CB2 as a seed layer.

Next, as shown in FIG. 11C , in the embodiment, a process of forming the first insulating layer 110 on the lower surface of the carrier metal layer CB2 and the lower surface of the first circuit pattern layer 130 may be performed. . In this case, in one embodiment, the first insulating layer 110 may be prepreg. Next, in the embodiment, a process of forming a through hole VH1 in the first insulating layer 110 may be performed. For example, in the embodiment, a process of forming a first through hole VH1 vertically overlapping an area where the first through electrode V1 is to be disposed may be performed by laser processing the first insulating layer 110 . there is.

Next, in the embodiment, as shown in FIG. 11D , in the embodiment, the first through hole VH1 is filled with a conductive material to form the first through electrode V1, and the first insulating layer 110 A process of forming the third circuit pattern layer 150 on the lower surface of ) may be performed.

Next, in the embodiment, as shown in FIG. 11E, a process of removing the carrier board may be performed. To this end, in the embodiment, a process of separating the carrier insulating layer CB1 from the carrier metal layer CB2 may be performed on the carrier board.

Next, in the embodiment, a process of etching the carrier metal layer CB2 may be performed.

Next, in the embodiment, as shown in FIG. 11F, a process of stacking the second insulating layer 120 on the upper surface of the first insulating layer 110 and the upper surface of the first circuit pattern layer 130 may be performed. there is. The second insulating layer 120 may include a photosensitive material.

Next, in the embodiment, as shown in FIG. 11G , a process of exposing and curing the second insulating layer 120 may be performed.

Specifically, in the embodiment, the rest of the second insulating layer 120 except for the area NE1 where the second through electrode V2 is to be disposed and the area NE2 where the cavity 121 is to be formed is exposed, Accordingly, a process of curing the exposed area may be performed.

Next, in the embodiment, as shown in FIG. 11H, a process of forming the second through hole VH2 and the cavity 121 may be performed by developing the areas NE1 and NE2 in which the exposure and curing are not performed. there is. The developing process is a process of removing the unexposed area using an organic alkaline compound containing tetramethylammonium hydroxide (TMAH) or trimethyl-2-hydroxyethylammonium hydroxide (choline). can be

Accordingly, in the embodiment, the second through hole VH2 and the cavity 121 may be formed in the second insulating layer 120 .

Next, in the embodiment, as shown in FIG. 11I, the inside of the second through hole VH2 is filled with a conductive material to form a second through electrode V2, and the upper surface of the second insulating layer 120 is formed. A process of forming the second circuit pattern layer 140 may be performed.

Next, in the embodiment, as shown in FIG. 11J, a first protective layer 160 is formed on the lower surface of the first insulating layer 110, and a second protective layer is formed on the upper surface of the second insulating layer 120. A process of forming 170 may proceed.

Features, structures, effects, etc. described in the embodiments above are included in at least one embodiment of the present invention, and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. illustrated in each embodiment can be combined or modified with respect to other embodiments by a person having ordinary knowledge in the field to which the embodiments belong. Therefore, contents related to these combinations and variations should be construed as being included in the scope of the present invention.

Claims (20)

a first insulating layer;
a first circuit pattern layer disposed on the first insulating layer;
a second insulating layer disposed on the first insulating layer and the first circuit pattern layer and including a cavity;
The first circuit pattern layer,
a first pad portion perpendicularly overlapping the cavity and on which a chip is mounted; and
A connection portion connected to the first pad portion;
The connection part,
a first portion vertically overlapping the cavity; and
Including a second part that does not overlap vertically with the cavity,
circuit board. According to claim 1,
The width of the first pad part is greater than the width of the connection part,
The connection part comprises a trace,
circuit board. According to claim 1,
The first circuit pattern layer,
A second pad portion that does not overlap vertically with the cavity,
One end of the first part of the connection part directly contacts the first pad part,
One end of the second part of the connection part directly contacts the second pad part,
circuit board. According to claim 1,
The second insulating layer including the cavity,
Having an inclined surface whose width gradually decreases toward the first insulating layer,
circuit board. According to claim 4,
The connecting portion vertically overlaps the inclined surface of the second insulating layer,
circuit board. According to claim 5,
The inclined surface of the second insulating layer,
an overlapping region vertically overlapping the first circuit pattern layer including the connecting portion; and
Including a non-overlapping region that does not vertically overlap with the first circuit pattern layer,
circuit board. According to any one of claims 1 to 6,
The first and second parts of the connecting portion are located on the same plane,
An upper surface of the second portion of the connection portion is covered with the second insulating layer,
circuit board. According to any one of claims 1 to 6,
The first insulating layer includes a first insulating material,
The second insulating layer includes a second insulating material different from the first insulating material,
circuit board. According to claim 8,
The first insulating layer includes prepreg,
The second insulating layer includes PID (Photoimageable dielectics),
circuit board. According to any one of claims 1 to 6,
a first conductive coupling part disposed on the first pad part; and
Including a chip disposed on the first conductive coupling portion,
circuit board. According to claim 10,
a second circuit pattern layer disposed on the second insulating layer; and
A second conductive coupling portion disposed on the second circuit pattern layer;
The uppermost end of the second conductive coupling part,
Located lower than the top of the element,
circuit board. According to any one of claims 1 to 6,
The first insulating layer and the second insulating layer include the same first insulating material,
The first insulating material includes photoimageable dielectics (PID),
The bottom surface of the cavity,
Located higher than the lower surface of the first pad portion and located lower than the upper surface of the first pad portion,
circuit board. According to claim 12,
The first circuit pattern layer protrudes above the top surface of the first insulating layer,
The second insulating layer,
Including a support insulation portion vertically overlapping the cavity and disposed between the first pad portion and the connection portion,
circuit board. According to claim 13,
The thickness of the supporting insulation part satisfies a range between 20% and 95% of the thickness of the first circuit pattern layer.
circuit board. According to claim 12,
A third insulating layer disposed under the second insulating layer,
The third insulating layer includes a second insulating material different from the first and second insulating layers,
The second insulating material includes prepreg,
circuit board. a first circuit board including a first cavity; and
A second circuit board including a second cavity vertically overlapping the first cavity and coupled to the first circuit board;
The first circuit board,
a first insulating layer;
a first circuit pattern layer disposed on the first insulating layer;
a second insulating layer disposed on the first insulating layer and the first circuit pattern layer and including the first cavity;
A second circuit pattern layer disposed on the second insulating layer;
a first conductive coupling part disposed on a first circuit pattern layer vertically overlapping the first cavity;
a processor chip disposed on the first conductive coupling part;
a second conductive coupling portion disposed on the second circuit pattern layer and coupled to the second circuit board;
At least a portion of the processor chip is disposed within the second cavity,
package substrate. According to claim 16,
The top of the processor chip is located higher than the top of the second conductive coupling part,
package substrate. The method of claim 16 or 17,
a third circuit board disposed on the second circuit board;
The third circuit board includes a memory chip,
The second circuit board,
An interposer board connecting between the first circuit board and the third circuit board,
package substrate. The method of claim 16 or 17,
a memory chip mounted on the second circuit board;
The second circuit board is a memory board connected to the first circuit board,
package substrate. The method of claim 16 or 17,
The first cavity includes a 1-1 cavity and a 1-2 cavity spaced apart in a longitudinal direction or a width direction,
The processor chip,
A first processor chip disposed in the 1-1 cavity;
A second processor chip disposed in the first-second cavity;
The first circuit pattern layer includes a connection portion connecting the first processor chip and the second processor chip,
The connection part,
A first portion vertically overlapping the 1-1 cavity and connected to the first processor chip;
a second portion vertically overlapping the first-second cavity and connected to the second processor chip;
A third part directly connected between the first and second parts and covered with the second insulating layer between the 1-1 and 1-2 cavities,
package substrate.

Images