KR20220149230A - Circuit board and package substrate including the same - Google Patents

Abstract

A circuit board according to an embodiment comprises: a first insulating layer; a first circuit pattern which is disposed on the first insulating layer, and includes a pad; and a bump which is disposed on the pad of the first circuit pattern. The bump includes: a first metal layer which is disposed on the pad of the first circuit pattern; and a second metal layer which is disposed on the first metal layer. The width of the first metal layer corresponds to the width of the second metal layer.

Description

Circuit board and package board including same

The embodiment relates to a circuit board and a package board including the same.

As the miniaturization, weight reduction, and integration of electronic components accelerate, the line width of circuits is becoming smaller. In particular, as design rules of semiconductor chips are integrated on a nanometer scale, the circuit line width of a package board or a printed circuit board on which a semiconductor chip is mounted is reduced to several micrometers or less.

In order to increase the degree of circuit integration of the printed circuit board, that is, to miniaturize the line width of the circuit, various methods have been proposed. In order to prevent loss of circuit line width in the etching step to form a pattern after copper plating, a semi-additive process (SAP) method and a modified semi-additive process (MSAP) are proposed. became

Thereafter, an Embedded Trace Substrate (hereinafter referred to as 'ETS') method in which a copper foil is buried in an insulating layer to implement a finer circuit pattern has been used in the art. The ETS method is advantageous in reducing the circuit pitch because there is no circuit loss due to etching because the copper foil circuit is manufactured by embedding it in the insulating layer instead of forming it on the surface of the insulating layer.

Meanwhile, recent efforts are being made to develop an improved 5 ^th generation (5G) communication system or a pre-5G communication system in order to meet the demand for wireless data traffic. Here, the 5G communication system uses a very high frequency (mmWave) band (sub 6 gigabytes (6GHz), 28 gigabytes 28GHz, 38 gigabytes 38GHz or higher frequencies) to achieve high data rates.

And, in order to alleviate the path loss of radio waves in the ultra-high frequency band and increase the propagation distance of radio waves, 5G communication systems integrate technologies such as beamforming, massive MIMO, and array antennas. are being developed Considering that these frequency bands can consist of hundreds of active antennas of wavelengths, the antenna system becomes relatively large.

Since these antennas and AP modules are patterned or mounted on a printed circuit board, low loss of the printed circuit board is very important. This means that several substrates constituting the active antenna system, ie, an antenna substrate, an antenna feeding substrate, a transceiver substrate, and a baseband substrate, must be integrated into one compact unit.

On the other hand, in recent years, due to the high specification of electronic devices such as mobile devices and the adoption of high bandwidth memory (HBM), a circuit board capable of mounting a plurality of chips on one package board is required.

However, the conventional circuit board for a package has a size limitation due to a design limitation of a pad on which a chip is mounted. For example, in a conventional circuit board for a package, the size of a minimum via, a size of a pad according to the size of the via, a size of a trace disposed between a plurality of pads, and an opening of a solder resist for opening the surface of the pad The size of the Solder resist open region (SOR) is limited. For example, in the conventional circuit board for package, the pitch of the pad for chip mounting exceeds 100 micrometers. Accordingly, when the conventional circuit board for a package is used, the number of chips that can be mounted in a limited space can be reduced. For example, in the related art, there is a problem in that the volume of the circuit board increases in order to mount all of the plurality of chips due to the limitation of the pitch of the pads.

In addition, recently, a circuit board having a fine pitch using a photosensitive material (eg, PID) has been developed. However, the circuit board made of the photosensitive material is vulnerable to warpage, and there is a problem in that the manufacturing cost is high compared to the circuit board manufactured using the prepreg.

In the embodiment, an object of the present invention is to provide a circuit board having a novel structure capable of minimizing the pitch of mounting pads and a package board including the same.

In addition, an embodiment is to provide a circuit board having a novel structure capable of minimizing the pitch of the post bumps, and a package board including the same.

In addition, an embodiment is to provide a circuit board having a novel structure capable of minimizing the width of the post bump and a package board including the same.

Another object of the present invention is to provide a circuit board having a novel structure capable of reducing the width of the post bump while maintaining the height of the post bump, and a package board including the same.

In addition, an embodiment is to provide a circuit board having a new structure from which the outermost solder resist is removed, and a package board including the same.

In addition, an embodiment is to provide a circuit board capable of completely removing the dry film remaining on the outermost side of the board without an additional process, and a package board including the same.

The technical tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks not mentioned are clear to those of ordinary skill in the art to which the proposed embodiment belongs from the description below. will be able to understand

A circuit board according to an embodiment includes a first insulating layer; a first circuit pattern disposed on the first insulating layer and including a pad; and a bump disposed on the pad of the first circuit pattern, wherein the bump comprises a first metal layer disposed on the pad of the first circuit pattern and a second metal layer disposed on the first metal layer. and a width of the first metal layer corresponds to a width of the second metal layer.

In addition, the first insulating layer is a first outermost insulating layer disposed on an uppermost side, and the first circuit pattern is a first outermost circuit pattern buried in an upper surface of the first outermost insulating layer.

In addition, the pad includes a first portion overlapping the bump in a vertical direction and a second portion other than the first portion, and the height of the upper surface of the first portion is equal to the height of the upper surface of the second portion different.

In addition, an upper surface of the first portion of the pad is disposed on the same plane as an upper surface of the first insulating layer.

In addition, an upper surface of the second portion of the pad is positioned lower than an upper surface of the first portion of the pad or the first insulating layer.

Also, the upper surface of the second portion of the pad includes a curved surface.

In addition, the first metal layer is a seed layer of the first circuit pattern and the second metal layer.

In addition, the width of the bump is less than 40% of the height of the bump.

In addition, the height of the bump is 100 μm or more.

In addition, the first circuit pattern includes a plurality of pads, the bumps include a plurality of bumps disposed on the plurality of pads, and an interval between centers of the plurality of bumps is 60 μm or less.

In addition, the first circuit pattern includes a trace, and at least a portion of an upper surface of the trace is positioned lower than an upper surface of the first insulating layer.

In addition, an upper surface of the trace of the first circuit pattern includes a curved surface.

On the other hand, the package substrate according to the embodiment includes a plurality of insulating layers; a first circuit pattern disposed on an upper surface of a first outermost insulating layer among the plurality of insulating layers and including a trace and a pad; a second circuit pattern and a third circuit pattern disposed between the plurality of insulating layers; a fourth circuit pattern disposed on a lower surface of the second outermost insulating layer among the plurality of insulating layers; a bump disposed on the pad of the first circuit pattern; a first connection part disposed on an upper surface of the pad; a chip disposed on the first connector; and a molding layer disposed on the first outermost insulating layer and molding the chip, wherein the bump includes a first metal layer disposed on the pad of the first circuit pattern; a second metal layer disposed on a first metal layer, wherein a width of the first metal layer corresponds to a width of the second metal layer, the pad includes a first portion overlapping the bump in a vertical direction; a second portion other than the portion, wherein a height of an upper surface of the first portion is different from a height of an upper surface of the second portion, and the first metal layer is a seed layer of the first circuit pattern and the second metal layer .

In addition, the molding layer is in direct contact with the upper surface of the insulating layer disposed on the first outermost side.

In addition, the second portion of the pad of the first circuit pattern includes a curved surface, and at least a portion of a lower surface of the molding layer includes a curved surface corresponding to the curved surface of the second portion.

In addition, the chip includes a first chip and a second chip disposed to be spaced apart from each other in a width direction, the first chip corresponding to a central processor (CPU), the second chip to the graphic processor (GPU) respond

In the embodiment, the manufacturing process of the circuit board may be simplified, and thus the manufacturing cost may be reduced.

Specifically, in the embodiment, a circuit pattern and bumps are respectively formed on both surfaces of a single seed layer. Accordingly, in the embodiment, in order to form the bump, the process of additionally forming the seed layer of the bump or the process of removing the additionally formed seed layer may be omitted, and thus the manufacturing process may be simplified.

Furthermore, in the embodiment, the bonding force between the bump and the circuit pattern may be improved. That is, in the embodiment, a circuit pattern plated by the seed layer and bumps plated by the seed layer are respectively disposed with one seed layer interposed therebetween. Accordingly, in the embodiment, an electrolytically plated circuit pattern and bumps are respectively formed on both sides of the single seed layer, thereby improving bonding strength between the circuit pattern and the bumps.

That is, in the comparative example, in order for the bump to have a certain height, the width of the bump had to be increased to correspond to the height of the bump. This is because a portion of the width of the bump had to include the thickness of the seed layer used to form the bump. In addition, the bump in the comparative example is formed by performing the process of forming a seed layer and an electrolytic plating layer on the pad. Accordingly, in the comparative example, as additional layers are sequentially formed on the pad, the bonding force between the pad and the bump is not secured compared to the present invention. Therefore, in the comparative example, the width of the bump had to be increased to a certain level or more in order to secure bonding force between the bump and the pad. In contrast, in the embodiment, both the circuit pattern and the bump are formed using one seed layer. Accordingly, in the embodiment, the bonding force between the circuit pattern and the bump may be secured.

Therefore, in the embodiment, the width of the bump can be reduced compared to the comparative example. Also, in the embodiment, even if the width of the bump is reduced, the bonding strength between the bump and the circuit pattern may be maintained.

Also, in the embodiment, as described above, both the first circuit pattern and the bump are formed using one seed layer. Accordingly, the metal layer used as the seed layer does not affect the width of the bump at all. For example, in the embodiment, the seed layer is disposed only on the lower surface of the bump, and is not disposed on the side surface of the bump. Accordingly, in the embodiment, the thickness of the seed layer does not affect the width of the bump at all, and accordingly, the width of the bump may be reduced.

In addition, in the embodiment, the solder resist disposed on the outermost side of the circuit board may be removed, thereby reducing the pitch between the plurality of bumps.

That is, in the embodiment, the protective layer disposed on the outermost side of the circuit board is removed as described above. For example, in the embodiment, the upper surface of the outermost insulating layer may be exposed to the outside. Accordingly, in the embodiment, as the protective layer disposed on the upper surface of the insulating layer is removed, the width of the pad of the circuit pattern must be maintained at a certain level or more due to the size limit of the open region SOR of the protective layer. solve the That is, in the embodiment, since the pad can be formed without considering the size of the open region SOR of the passivation layer, the width of the pad 121P can be reduced.

Accordingly, in an embodiment, the pitch of the bumps may be reduced, and accordingly, a space in which a plurality of different application processor chips may be disposed on the circuit pattern may be secured. Accordingly, in the embodiment, the volume of the circuit board and the package board including the same can be reduced.

In addition, in the embodiment, the outermost circuit pattern can be stably protected. For example, in the circuit board in the embodiment, a protective layer (eg, solder resist) is not disposed on the first outermost side corresponding to the uppermost side. For example, in the circuit board in the embodiment, the uppermost protective layer may be removed. In this case, the trace of the circuit pattern is a fine pattern, and is an outermost circuit pattern disposed on the outermost side of the circuit board. Accordingly, as the passivation layer is not disposed on the trace, the trace may be damaged in various use environments. In this case, in the embodiment, the upper surface of the trace has a curved surface concave in the downward direction. Accordingly, in the embodiment, the trace has a structure buried deeper than that of the comparative example in the upper surface of the insulating layer, and thus the trace can be stably protected in various use environments.

1 is a view showing a circuit board according to a comparative example.
2 is a view showing a circuit board according to the first embodiment.
FIG. 3 is an enlarged view for explaining the outermost region of FIG. 2 .
FIG. 4 is a view for explaining a layer structure of the circuit pattern of FIG. 2 .
5 is a view showing a package substrate according to an embodiment.
6 to 20 are views showing the manufacturing method of the circuit board shown in FIG. 2 in order of process.

Hereinafter, the embodiments disclosed in the present specification will be described in detail with reference to the accompanying drawings, but the same or similar components are assigned the same reference numerals regardless of reference numerals, and redundant description thereof will be omitted. The suffixes "module" and "part" for components used in the following description are given or mixed in consideration of only the ease of writing the specification, and do not have distinct meanings or roles by themselves. In addition, in describing the embodiments disclosed in the present specification, if it is determined that detailed descriptions of related known technologies may obscure the gist of the embodiments disclosed in the present specification, the detailed description thereof will be omitted. In addition, the accompanying drawings are only for easy understanding of the embodiments disclosed in this specification, and the technical idea disclosed herein is not limited by the accompanying drawings, and all changes included in the spirit and scope of the present invention , should be understood to include equivalents or substitutes.

Terms including ordinal numbers such as first, second, etc. may be used to describe various elements, but the elements are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another.

When a component is referred to as being “connected” or “connected” to another component, it may be directly connected or connected to the other component, but it is understood that other components may exist in between. it should be On the other hand, when it is said that a certain element is "directly connected" or "directly connected" to another element, it should be understood that the other element does not exist in the middle.

The singular expression includes the plural expression unless the context clearly dictates otherwise.

In the present application, terms such as “comprises” or “have” are intended to designate that a feature, number, step, operation, component, part, or combination thereof described in the specification exists, but one or more other features It is to be understood that this does not preclude the possibility of the presence or addition of numbers, steps, operations, components, parts, or combinations thereof.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

- Comparative Example -

Prior to the description of the embodiment, a comparative example compared with the circuit board of the embodiment of the present application will be described.

1 is a view showing a circuit board according to a comparative example.

Referring to FIG. 1 , the circuit board of the comparative example includes an insulating layer 11 .

In addition, the circuit board of the comparative example includes a circuit pattern disposed on the surface of the insulating layer 11 . For example, the circuit board of the comparative example includes a first circuit pattern 21 disposed on an upper surface of the insulating layer 11 and a second circuit pattern 22 disposed on a lower surface of the insulating layer 11 .

The circuit board of this comparative example is manufactured by ETS (Embedded Trace Substrate) method. Accordingly, in the circuit board of the comparative example, any one of the first circuit pattern 21 and the second circuit pattern 22 has a structure buried in the insulating layer 11 .

For example, in the circuit board of the comparative example, the first circuit pattern 21 has a structure buried in the upper surface of the insulating layer 11 . For example, an upper surface of the first circuit pattern 21 is positioned on the same plane as an upper surface of the insulating layer 11 .

The circuit board of the comparative example includes vias 31 .

The via 31 electrically connects circuit patterns disposed on different layers of the insulating layer 11 . For example, an upper surface of the via 31 is connected to a lower surface of the first circuit pattern 21 , and a lower surface of the via 31 is connected to an upper surface of the second circuit pattern 22 . Through this, the first circuit pattern 21 and the second circuit pattern 22 are electrically connected to each other.

The circuit board of the comparative example includes post bumps 50 . The post bump 50 is composed of a plurality of layers. For example, the post bump 50 includes a first metal layer 51 disposed on the first circuit pattern 21 and a second metal layer 52 disposed on the first metal layer 51 . .

The first metal layer 51 is a seed layer used to form the post bump 50 . For example, the first metal layer 51 is a chemical copper plating layer.

The second metal layer 52 is an electrolytic plating layer formed by performing electrolytic plating on the first metal layer 51 as a seed layer.

The second metal layer 52 is formed to protrude from the top surface of the first circuit pattern 21 with a predetermined height.

However, in the post bump 50 as described above, the first metal layer 51 is disposed to cover at least a portion of the side surface of the second metal layer 52 . For example, in the post bump 50 of the comparative example, the first metal layer 51 has a 'C' shape. For example, the first metal layer 51 in the comparative example is disposed to surround a portion of a lower surface of the second metal layer 52 and a side surface of the second metal layer 52 .

Accordingly, in the comparative example, the width of the post bump 50 is affected by the thickness of the first metal layer 51 . For example, at least a portion of the post bump 50 in the comparative example is composed of the first metal layer 51 , and accordingly, the width of the post bump 50 in the comparative example is the first metal layer 51 . increases by the thickness of

Therefore, there is a limit in reducing the width of the post bump 50 in the comparative example as described above.

In addition, the post bump 50 in the comparative example is disposed to have a predetermined height on the circuit board. At this time, the post bump 50 has a predetermined width in order to have a predetermined height. For example, the width of the post bump 50 is 40% or more of the height of the post bump 50 . For example, the width of the post bump 50 is 50% or more of the height of the post bump 50 . For example, the width of the post bump 50 is 60% of the height of the post bump 50 . This has a limit in reducing the width of the post bump 50 by the first metal layer 51 and further affects the width of the opening of the protective layer 40 disposed on the upper surface of the insulating layer 11 . because you receive

For example, in the comparative example, the protective layer 40 disposed on the upper surface of the insulating layer 11 is included. The protective layer 40 is disposed on the upper surface of the insulating layer 11 and has an opening exposing a portion of the upper surface of the first circuit pattern 21 . For example, the passivation layer 40 includes an opening exposing a region in which the post bump 50 is to be disposed among the upper surface of the first circuit pattern 21 .

In this case, the circuit board of the comparative example as described above includes the protective layer 40 , and there is a limitation in the size of a solder resist open region (SOR) corresponding to the opening of the protective layer 40 . That is, the opening of the protective layer 40 has a width of at least 40 μm. In addition, the width of the post bump 50 is affected by the width of the opening of the protective layer 40 . For example, the post bump 50 is formed to fill the opening of the protective layer 40 . Accordingly, the width of the post bump 50 corresponds to the width of the opening of the protective layer 40 . As described above, the post bump 50 of the comparative example is limited by the thickness of the first metal layer 51 and the size of the opening of the protective layer 40, and thus there is a limit in reducing the width or reducing the pitch. .

In addition, the first metal layer 51 in the comparative example is a seed layer of the second metal layer 52 . In this case, at least a portion of the first metal layer 51 is disposed between the first metal layer 51 and the second metal layer 52 . In this case, the first metal layer 51 is a layer that does not participate in the formation of the first circuit pattern 21 at all. That is, the first metal layer 51 is a layer formed after the first circuit pattern 21 is completed. Accordingly, in the comparative example, in the process of forming the post bump 50 , the process of forming the first metal layer 51 should be performed, and accordingly, after the second metal layer 52 is formed, the first There is a problem in that a process of etching and removing the metal layer 51 must be additionally performed.

Meanwhile, in the comparative example, the post bump 50 may be formed using a dry film (not shown). In this case, the post bump 50 generally has a height of 100 μm or more. Accordingly, the dry film has a thickness of 100 μm or more, corresponding to the height of the post bump 50 . In this case, when the thickness of the dry film exceeds 100 μm, a problem in peelability of the dry film may occur. For example, when the thickness of the dry film exceeds 100 μm, a residue may remain on the surface of the circuit board during the peeling process. Accordingly, in the comparative example, an additional process of removing the residue must be performed in the process of removing the dry film.

The embodiment is intended to solve the problems of the comparative example, and while simplifying the manufacturing process of the circuit board, the bonding force between the circuit pattern and the post bump can be improved, and further, the width of the post bump can be reduced. In addition, in the embodiment, as the width and pitch of the post bumps decrease, a plurality of chips can be mounted on one circuit board. For example, an embodiment provides a circuit board capable of mounting all of a plurality of processor chips or memory chips having different functions on a single circuit board, and a package board including the same.

-Electronic device-

Prior to the description of the embodiment, an electronic device including the package substrate of the embodiment will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and/or electrically connected to various components. For example, the main board may be connected to the package substrate of the embodiment. Various chips may be mounted on the package substrate. Broadly, the package substrate includes a volatile memory (eg, DRAM), a non-volatile memory (eg, ROM), a memory chip such as a flash memory, a central processor (eg, CPU), a graphics processor (eg, GPU), An application processor chip such as a digital signal processor, an encryption processor, a microprocessor, and a microcontroller, and a logic chip such as an analog-to-digital converter and an ASIC (application-specific IC) may be mounted.

In addition, the embodiment provides a circuit board and a package board capable of refining the pitch of the pads and capable of mounting at least two different types of chips on a single board according to the miniaturization of the pitch. Furthermore, the embodiment provides a circuit board and a package substrate in which more traces than in the comparative example can be disposed between mounting pads having a smaller pitch than in the comparative example.

In this case, the electronic device includes a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, and a computer. ), a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, and the like. However, the present invention is not limited thereto, and may be any other electronic device that processes data in addition to these.

Hereinafter, a circuit board according to an embodiment and a package board including the same will be described.

- Circuit board -

FIG. 2 is a view showing the circuit board according to the first embodiment, FIG. 3 is an enlarged view for explaining the outermost region of FIG. 2, and FIG. 4 is a view for explaining the layer structure of the circuit pattern of FIG. .

Hereinafter, a circuit board according to an embodiment will be described in detail with reference to FIGS. 2 to 4 .

The circuit board of the embodiment provides a mounting space in which at least one chip can be mounted. The number of chips mounted on the circuit board of the embodiment may be one, alternatively may be two, or alternatively there may be three or more. For example, one processor chip may be mounted on the circuit board, and at least two processor chips having different functions may be mounted on the circuit board. Alternatively, one memory chip may be mounted together with one processor chip. Alternatively, at least two processor chips and at least one memory chip having different functions may be mounted.

The circuit board includes an insulating layer 110 . The insulating layer 110 has a structure of at least one layer. At this time, although FIG. 1 illustrates that the circuit board has a three-layer structure based on the number of layers of the insulating layer 110 , the present invention is not limited thereto. For example, the circuit board may have a stacked structure of two or less layers based on the number of layers of the insulating layer 110 , or alternatively may have a stacked structure of four or more layers.

However, hereinafter, for convenience of explanation, the circuit board will be described as having a three-layer structure based on the number of layers of the insulating layer 110 .

The insulating layer 110 may include a prepreg (PPG, prepreg). The prepreg may be formed by impregnating a fiber layer in the form of a fabric sheet, such as a glass fabric woven with glass yarn, with an epoxy resin, and then performing thermocompression. However, the embodiment is not limited thereto, and the prepreg constituting the insulating layer 110 may include a fiber layer in the form of a fabric sheet woven with carbon fiber yarn.

The insulating layer 110 may include a resin and a reinforcing fiber disposed in the resin. The resin may be an epoxy resin, but is not limited thereto. The resin is not particularly limited to the epoxy resin, for example, one or more epoxy groups may be included in the molecule, and alternatively, two or more epoxy groups may be included. Alternatively, four or more epoxy groups may be included. In addition, the resin of the insulating layer 110 may include a naphthalene group, for example, may be an aromatic amine type, but is not limited thereto. For example, the resin is a bisphenol A type epoxy resin, a bisphenol F type epoxy resin, a bisphenol S type epoxy resin, a phenol novolak type epoxy resin, an alkylphenol novolak type epoxy resin, a biphenyl type epoxy resin, an aralkyl type epoxy resin Resin, dicyclopentadiene type epoxy resin, naphthalene type epoxy resin, naphthol type epoxy resin, epoxy resin of condensate of phenol and aromatic aldehyde having phenolic hydroxyl group, biphenyl aralkyl type epoxy resin, fluorene type epoxy resin resins, xanthene-type epoxy resins, triglycidyl isocyanurate, rubber-modified epoxy resins, phosphorous-based epoxy resins, and the like, and naphthalene-based epoxy resins, bisphenol A-type epoxy resins, and phenol novolac epoxy resins , cresol novolac epoxy resins, rubber-modified epoxy resins, and phosphorous-based epoxy resins. In addition, the reinforcing fiber is glass fiber, carbon fiber, aramid fiber (eg, aramid-based organic material), nylon (nylon), silica (silica)-based inorganic material or titania-based inorganic material is used. can The reinforcing fibers may be arranged in the resin to cross each other in a planar direction.

Meanwhile, the glass fiber, carbon fiber, aramid fiber (eg, aramid-based organic material), nylon, silica-based inorganic material or titania-based inorganic material may be used.

However, the embodiment is not limited thereto, and the insulating layer 110 may include other insulating materials.

For example, the insulating layer 110 may be rigid or flexible. For example, the insulating layer 110 may include glass or plastic. In detail, the insulating layer 110 may include chemically strengthened/semi-tempered glass such as soda lime glass or aluminosilicate glass, polyimide (PI), polyethylene terephthalate (PET), or the like. ), propylene glycol (PPG), reinforced or soft plastic such as polycarbonate (PC), or may include sapphire. For example, the insulating layer 110 may include an optical isotropic film. For example, the insulating layer 110 may include cyclic olefin copolymer (COC), cyclic olefin polymer (COP), photoisotropic polycarbonate (PC), or photoisotropic polymethyl methacrylate (PMMA). . For example, the insulating layer 110 may be formed of a material including an inorganic filler and an insulating resin. For example, the insulating layer 110 is a thermosetting resin such as an epoxy resin, a resin containing a reinforcing material such as an inorganic filler such as silica and alumina together with a thermoplastic resin such as polyimide, specifically ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), PID (Photo Imagable Dielectric resin), BT, etc. may be used.

The insulating layer 110 may include a first insulating layer 111 , a second insulating layer 112 , and a third insulating layer 113 from an uppermost side.

In this case, when the circuit board of the embodiment has a one-layer structure, the insulating layer 110 may include only the first insulating layer 111 . For example, when the circuit board of the embodiment has a two-layer structure, the insulating layer 110 may include the first insulating layer 111 and the third insulating layer 113 . For example, when the circuit board of the embodiment has a structure of four or more layers, the second insulating layer 112 may have a structure of a plurality of layers.

Each of the first insulating layer 111 , the second insulating layer 112 , and the third insulating layer 113 may have a thickness in a range of 10 μm to 100 μm. For example, the first insulating layer 111 , the second insulating layer 112 , and the third insulating layer 113 may have a thickness in a range of 15 μm to 80 μm. For example, each of the first insulating layer 111 , the second insulating layer 112 , and the third insulating layer 113 may have a thickness in a range of 20 μm to 50 μm.

In this case, the thickness of the first insulating layer 111 , the second insulating layer 112 , and the third insulating layer 113 may correspond to a distance in the thickness direction between circuit patterns disposed on different layers. .

For example, the thickness of the first insulating layer 111 may mean a linear distance between the lower surface of the first circuit pattern 121 and the upper surface of the second circuit pattern 122 . For example, the thickness of the second insulating layer 112 may mean a linear distance between the lower surface of the second circuit pattern 122 and the third circuit pattern 123 . For example, the thickness of the third insulating layer 113 may mean a linear distance between the lower surface of the third circuit pattern 123 and the fourth circuit pattern 124 .

Meanwhile, the first insulating layer 111 may be a first outermost insulating layer disposed on the first outermost side of the circuit board according to the embodiment. For example, the first insulating layer 111 may be an uppermost insulating layer disposed on the uppermost side of the circuit board.

In addition, the third insulating layer 113 may be a second outermost insulating layer disposed on the second outermost side opposite to the first insulating layer 111 in the circuit board of the embodiment. For example, the second insulating layer 112 may be a lowermost insulating layer disposed on the lowermost side of the circuit board.

Also, the second insulating layer 112 may be an inner insulating layer disposed between the first outermost insulating layer and the second outermost insulating layer. In this case, when the circuit board has a layer structure of four or more layers, the inner insulating layer may have a layer structure of two or more layers.

A circuit pattern is disposed on the surface of the insulating layer 110 .

For example, a first circuit pattern 121 is disposed on the upper surface of the first insulating layer 111 . For example, the second circuit pattern 122 is disposed on the lower surface of the first insulating layer 111 or the upper surface of the second insulating layer 112 . For example, a third circuit pattern 123 is disposed on a lower surface of the second insulating layer 112 or an upper surface of the third insulating layer 113 . For example, a fourth circuit pattern 124 is disposed on a lower surface of the third insulating layer 113 .

In an embodiment, the circuit board may be manufactured using an Embedded Trace Substrate (ETS) method. Accordingly, at least one of the plurality of circuit patterns included in the circuit board may have an ETS structure. For example, a circuit pattern disposed on at least one of the circuit patterns disposed on each layer of the circuit board may have a structure buried in the surface of the insulating layer. For example, in an embodiment, the circuit pattern disposed on the upper surface of the first outermost insulating layer may have an ETS structure. For example, in an embodiment, the first circuit pattern 121 disposed on the upper surface of the first insulating layer 111 may have an ETS structure.

Accordingly, the first circuit pattern 121 may have a structure buried in the upper surface of the first insulating layer 111 . And, in an embodiment, the second circuit pattern 122 , the third circuit pattern 123 , and the fourth circuit pattern 124 excluding the first circuit pattern 121 are formed from the surface of the insulating layer 110 . It may have a protruding structure.

For example, the first circuit pattern 121 may have a structure buried in the upper surface of the first insulating layer 111 . For example, the upper surface of the first circuit pattern 121 may be a circuit pattern disposed on the first outermost side of the circuit board. Accordingly, the first circuit pattern 121 may be exposed to the first outermost side of the circuit board. The first circuit pattern 121 may be surrounded by the first insulating layer 111 . For example, side surfaces and lower surfaces of the first circuit pattern 121 may be surrounded by the first insulating layer 111 .

Meanwhile, in an embodiment, the upper surface of the first circuit pattern 121 may be positioned lower than the upper surface of the first insulating layer 111 . For example, at least a portion of an upper surface of the first circuit pattern 121 may be positioned lower than an uppermost end of the first insulating layer 111 . For example, at least a portion of the upper surface of the first insulating layer 111 may be positioned higher than the upper surface of the first circuit pattern 121 . For example, at least a portion of the top surface of the first circuit pattern 121 may be located on the same plane as the top surface of the first insulating layer 111 . In summary, the first portion of the upper surface of the first circuit pattern 121 is disposed on the same plane as the upper surface of the first insulating layer 111 , and the second portion of the upper surface of the first circuit pattern 121 . may be positioned lower than the upper surface of the first insulating layer 111 . This will be described in more detail below.

For example, the second circuit pattern 122 may have a structure protruding downward from the lower surface of the first insulating layer 111 . For example, the second circuit pattern 122 may have a structure buried in the upper surface of the second insulating layer 112 . Side and lower surfaces of the second circuit pattern 122 may be surrounded by the second insulating layer 112 .

For example, the third circuit pattern 123 may have a structure protruding downward from the lower surface of the second insulating layer 112 . For example, the third circuit pattern 123 may have a structure buried in the upper surface of the third insulating layer 113 . Side and lower surfaces of the third circuit pattern 123 may be surrounded by the third insulating layer 113 .

For example, the fourth circuit pattern 124 may have a structure protruding downward from the lower surface of the third insulating layer 113 . For example, the fourth circuit pattern 124 may be a circuit pattern disposed on the second outermost side of the circuit board. Accordingly, a lower surface of the fourth circuit pattern 124 may be exposed to the second outermost portion of the circuit pattern 121 .

Meanwhile, the circuit patterns of the embodiment may include traces and pads. For example, the first circuit pattern 121 and the fourth circuit pattern 124 disposed on the first and second outermost sides of the circuit board may include a mounting pad on which a chip is mounted or a terminal pad connected to an external board. can In addition, the first circuit pattern 121 and the fourth circuit pattern 124 may include traces that are long wires connected to the mounting pad or the terminal pad.

The circuit patterns as described above are made of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). can be formed. In addition, the first circuit pattern 120 is selected from among gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding strength. It may be formed of a paste or solder paste including at least one metal material. Preferably, the first circuit pattern 121 , the second circuit pattern 122 , the third circuit pattern 123 , and the fourth circuit pattern 124 are formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive. can be

Each of the first circuit pattern 121 , the second circuit pattern 122 , the third circuit pattern 123 , and the fourth circuit pattern 124 may have a thickness in a range of 5 μm to 20 μm. For example, each of the first circuit pattern 121 , the second circuit pattern 122 , the third circuit pattern 123 , and the fourth circuit pattern 124 may have a thickness in the range of 6 μm to 17 μm. . Each of the first circuit pattern 121 , the second circuit pattern 122 , the third circuit pattern 123 , and the fourth circuit pattern 124 may have a thickness in a range of 7 μm to 13 μm. When the thickness of each of the first circuit pattern 121, the second circuit pattern 122, the third circuit pattern 123, and the fourth circuit pattern 124 is less than 5 μm, the resistance of the circuit pattern increases, Accordingly, signal transmission efficiency may decrease. For example, when the thickness of each of the first circuit pattern 121 , the second circuit pattern 122 , the third circuit pattern 123 , and the fourth circuit pattern 124 is less than 5 μm, the signal transmission loss is can increase For example, when the thickness of each of the first circuit pattern 121 , the second circuit pattern 122 , the third circuit pattern 123 , and the fourth circuit pattern 124 exceeds 20 μm, the circuit The line width of the patterns may increase, and thus the overall volume of the circuit board may increase.

Meanwhile, the first circuit pattern 121 of the embodiment may be a fine pattern. Also, correspondingly, the second circuit pattern 122 , the third circuit pattern 123 , and the fourth circuit pattern 124 may be fine patterns. However, in the embodiment, the first circuit pattern 121 includes a chip mounting unit on which a chip is mounted on the package substrate. In addition, the first circuit pattern 121 may include a mounting pad on which at least one application processor chip is mounted. For example, the first circuit pattern 121 may include a mounting pad on which at least two application processor chips are mounted. Accordingly, the first circuit pattern 121 may include a fine pattern. However, the characteristics of the first circuit pattern 121 described below may be equally applied to the second circuit pattern 122 , the third circuit pattern 123 , and the fourth circuit pattern 124 . For convenience, only the first circuit pattern 121 will be described.

The first circuit pattern 121 may include a trace 121T and a pad 121P.

A line width of the trace 121T of the first circuit pattern 121 may be 7 μm or less. For example, the line width of the trace 121T of the first circuit pattern 121 may be 6 μm or less. For example, the line width of the trace 121T of the first circuit pattern 121 may be 5 μm or less. For example, the line width of the trace 121T of the first circuit pattern 121 may be in a range of 1 μm to 7 μm. For example, the line width of the trace 121T of the first circuit pattern may be in a range of 1.5 μm to 6.5 μm. For example, the line width of the trace 121T of the first insulating layer 111 may be in a range of 2 μm to 6 μm.

In addition, the first circuit pattern 121 includes a plurality of traces 121T disposed on the upper surface of the first insulating layer 111 at a predetermined distance from each other. In addition, an interval between the plurality of traces 121T of the first circuit pattern 121 may be 7 μm or less. For example, an interval between the traces 121T of the first circuit pattern 121 may be 6 μm or less. For example, an interval between the traces 121T of the first circuit pattern 121 may be 5 μm or less. For example, an interval between the traces 121T of the first circuit pattern 121 may be in a range of 1 μm to 7 μm. For example, an interval between the traces 121T of the first circuit pattern 121 may be in a range of 1.5 μm to 6.5 μm. For example, an interval between the traces 121T of the first circuit pattern 121 may be in a range of 2 μm to 6 μm.

However, in the first circuit pattern 121 in the embodiment, the line width of the trace 121T may be greater than the interval between the traces 121T. For example, an interval between the traces 121T of the first circuit pattern 121 may be smaller than a line width of the trace 121T. For example, in a general circuit board, there is a limit to further reducing the line width of the trace 121T within the above-described range. Accordingly, in order to increase the density of the first circuit pattern 121 within a limited space, it is important to reduce the spacing between the traces 121T rather than the line width of the traces 121T of the first circuit pattern 121 . . In this case, in the embodiment, the interval between the traces 121T of the first circuit pattern 121 is smaller than the line width of the traces 121T. Accordingly, in the embodiment, even when the line width of the trace 121T is maintained at a certain level, the density of the first trace 121T in a limited space can be increased, and thus the overall volume of the circuit board can be reduced. .

Meanwhile, in the embodiment, at least a portion of the upper surface of the trace 121T may be positioned lower than the upper surface of the first insulating layer 111 . For example, a central portion of the upper surface of the trace 121T may be lower than an edge portion. For example, the upper surface of the trace 121T may include a curved surface concave in the downward direction.

The shape of the trace 121T as described above may be achieved by a manufacturing process of the bump 150 to be described below. For example, the shape of the trace 121T may be indicated by a process of removing a seed layer used to form the bump 150 .

At this time, in the embodiment, the upper surface of the trace 121T includes a concave curved surface as described above, so that the reliability of the trace 121T can be improved.

For example, in the circuit board in the embodiment, a protective layer (eg, solder resist) is not disposed on the first outermost side corresponding to the uppermost side. For example, in the circuit board in the embodiment, the uppermost protective layer may be removed. In this case, the trace 121T of the circuit pattern 121 is a fine pattern, and is an outermost circuit pattern disposed on the outermost side of the circuit board. Accordingly, as the passivation layer is not disposed on the trace 121T, the trace 121T may be damaged in various use environments. In this case, in the embodiment, the upper surface of the trace 121T has a curved surface concave in the downward direction. Accordingly, in the embodiment, the trace 121T has a structure buried deeper than that of the comparative example in the upper surface of the first insulating layer 111, and thus the trace 121T is stably protected in various use environments. make it possible

Meanwhile, in the embodiment, the first circuit pattern 121 includes a pad 121P. The pad 121P may refer to a mounting pad on which an application processor chip is mounted on a package substrate. For example, the pad 121P of the first circuit pattern 121 may mean a via pad connected to the first via 131 to be described below. The pad 121P of the first circuit pattern 121 may have a greater width than the trace 121T of the first circuit pattern 121 . For example, the pad 121P of the first circuit pattern 121 may be determined by the size of the first via 131 . A width of the pad 121P of the first circuit pattern 121 may be in a range of 15 μm to 100 μm. For example, the width of the pad 121P of the first circuit pattern 121 may be in a range of 18 μm to 90 μm. For example, the width of the pad 121P of the first circuit pattern 121 may be in a range of 20 μm to 80 μm.

The pad 121P of the first circuit pattern 121 may be divided into a plurality of regions. For example, the pad 121P of the first circuit pattern 121 may include a first portion 121P1 on which the bump 150 is disposed and a second portion 121P2 other than the first portion 121P1. can Also, the first portion 121P1 and the second portion 121P2 of the pad 121P of the first circuit pattern 121 may have different shapes. For example, the upper surface of the first portion 121P1 of the pad 121P of the first circuit pattern 121 may be located on a different plane from the upper surface of the second portion 121P2 . For example, a top surface of the first part 121P1 of the pad 121P of the first circuit pattern 121 may be positioned higher than a top surface of the second part 121P2 . For example, an upper surface of the first portion 121P1 of the pad 121P of the first circuit pattern 121 may be flat. For example, the upper surface of the second portion 121P2 of the pad 121P of the first circuit pattern 121 may include a curved surface. In detail, the thickness of the second portion 121P2 of the pad 121P may decrease as the distance from the first portion 121P1 increases.

Accordingly, the top surface of the first portion 121P1 of the pad 121P of the first circuit pattern 121 in the embodiment may be disposed on the same plane as the top surface of the first insulating layer 111 . That is, the first portion 121P1 and the first insulating layer 111 of the pad 121P are disposed on one and the same metal layer (a seed layer, which will be described later). Accordingly, the first portion 121P1 of the pad 121P and the top surface of the first insulating layer 111 may be positioned on the same plane. Also, in an embodiment, the upper surface of the second portion 121P2 of the pad 121P may be positioned lower than the upper surface of the first insulating layer 111 . For example, the upper surface of the second portion 121P2 of the pad 121P has a curved surface, and thus the first insulating layer 111 is further away from the first portion 121P1 of the pad 121P. The step with the upper surface of the may increase. For example, the height of the top surface of the second part 121P2 of the pad 121P may correspond to the height of the top surface of the first insulating layer 111 at a position adjacent to the first part 121P1 . In addition, the upper surface of the second portion 121P2 of the pad 121P may gradually become lower than the height of the upper surface of the first insulating layer 111 as it moves away from the first portion 121P1 .

As described above, the shape of the pad 121P of the first circuit pattern 121 may be due to the relationship between the first circuit pattern 121 and the bump 150 , which will be described below.

A bump 150 is disposed on the pad 121P of the first circuit pattern 121 . The bump 150 may have a predetermined height H1 and may protrude on the pad 121P of the first circuit pattern 121 .

The bump 150 may be composed of a plurality of layers.

For example, the bump 150 includes a first metal layer 151 disposed on the first portion 121P1 of the first circuit pattern 121 . In addition, the bump 150 in the embodiment includes a second metal layer 152 disposed on the first metal layer 151 .

The first metal layer 151 may be a seed layer for forming the second metal layer 152 . The first metal layer 151 may be a copper foil. For example, the first metal layer 151 may be a copper foil layer.

That is, in the circuit board of the embodiment, the process of forming the first circuit pattern 121 is performed by using the copper foil constituting the carrier board (to be described later) as a seed layer. That is, the first circuit pattern 121 may be an electrolytic plating layer formed by electroplating the copper foil of the carrier board as a seed layer. In this case, in the embodiment, the bump 150 can be formed using the copper foil of the carrier board used as the seed layer of the first circuit pattern 121 without removing the copper foil.

That is, the first metal layer 151 may be a metal layer constituting the carrier board. For example, the first metal layer 151 may be a copper foil constituting the carrier board. For example, the first metal layer 151 may be a copper foil layer constituting the carrier board. For example, the first metal layer 151 may be a seed layer used to form the first circuit pattern 121 . Furthermore, the first metal layer 151 may be a seed layer used to form the second metal layer 152 .

Consequently, in the embodiment, the first circuit pattern 121 and the second metal layer 152 are respectively formed on both surfaces of the seed layer using one seed layer.

Here, it is assumed that the first metal layer 151 is a component of the bump 150 , but the first metal layer 151 is not only a component of the bump 150 , but also the first circuit pattern 121 . It may be a work configuration of

As described above, in the embodiment, the first circuit pattern 121 and the second metal layer 152 may be formed by performing electrolytic plating on both sides of the single seed layer.

Accordingly, in the embodiment, in order to form the bump 150 , the process of additionally forming the seed layer of the bump 150 or the process of removing the additionally formed seed layer may be omitted, and thus the manufacturing process can be simplified.

Furthermore, in an embodiment, the bonding force between the bump 150 and the first circuit pattern 121 may be improved. That is, in the embodiment, the first circuit pattern 121 and the second metal layer 152 are respectively disposed with the first metal layer 151 interposed therebetween. Accordingly, in the embodiment, as the first circuit pattern 121 and the second metal layer 152 are formed by using the same metal layer, the first metal layer 151 and the first circuit pattern 121 are formed. It is possible to improve the bonding strength between the two metal layers, the bonding strength between the first metal layer 151 and the second metal layer 152 , and further the bonding strength between the first circuit pattern 121 and the bump 150 .

Meanwhile, in an embodiment, the width of the bump 150 may be reduced. For example, the width W1 of the bump 150 may be less than 40% of the height H1 of the bump 150 . For example, the width W1 of the bump 150 may be 35% or less of the height H1 of the bump 150 . For example, the width W1 of the bump 150 may be 30% or less of the height H1 of the bump 150 . That is, in the embodiment, the height H1 of the bump 150 may be 100 μm or more. For example, in the embodiment, the height H1 of the bump 150 may be 110 μm or more. For example, the height H1 of the bump 150 in the above embodiment may be 120 μm or more. And, in the embodiment, the width of the bump 150 may be less than 40% of the height of the bump 150 .

That is, in the comparative example, in order for the bump to have a certain height, the width of the bump had to be increased to correspond to the height of the bump. This is because a portion of the width of the bump had to include the thickness of the seed layer used to form the bump. In addition, the bump in the comparative example is formed by performing the process of forming a seed layer and an electrolytic plating layer on the pad. Accordingly, in the comparative example, as additional layers are sequentially formed on the pad, the bonding force between the pad and the bump is not secured compared to the present invention. Therefore, in the comparative example, the width of the bump had to be increased to a certain level or more in order to secure bonding force between the bump and the pad.

In contrast, in the embodiment, both the first circuit pattern 121 and the bump 150 are formed using one seed layer. Accordingly, in the embodiment, the bonding force between the first circuit pattern 121 and the bump 150 may be secured. Accordingly, in the embodiment, the width W1 of the bump 150 may be reduced compared to the comparative example. Also, in the embodiment, even if the width W1 of the bump 150 is reduced, the bonding strength between the bump 150 and the first circuit pattern 121 may be maintained.

Also, in the embodiment, as described above, both the first circuit pattern 121 and the bump 150 are formed using one seed layer.

Accordingly, the first metal layer 151 used as the seed layer does not affect the width of the bump 150 at all. For example, in the embodiment, the first metal layer 151 is disposed only on the lower surface of the second metal layer 152 . For example, the first metal layer 151 does not contact the side surface of the second metal layer 152 . For example, in the bump 150 , the width of the first metal layer 151 may be the same as the width of the second metal layer 152 . For example, the first upper surface and the first lower surface of the first metal layer 151 may have the same width. Also, the second metal layer 152 may include a second bottom surface having the same width as the first top surface of the first metal layer 151 and a second top surface having the same width as the second bottom surface.

Accordingly, in the embodiment, the thickness of the first metal layer 151 used as the seed layer does not affect the width of the bump 150 at all, and accordingly, the width of the bump 150 can be reduced.

Meanwhile, in the embodiment, the bumps 150 are respectively disposed on the plurality of pads 121P of the first circuit pattern 121 . For example, in the embodiment, a plurality of bumps 150 are provided on the pad 121P to be spaced apart from each other.

In this case, in the embodiment, the pitch P1 between the centers of the bumps 150 can be reduced compared to the comparative example. For example, the pitch P1 corresponding to the distance between the centers of the plurality of bumps 150 in the embodiment may be 60 μm or less. For example, in an embodiment, the pitch P1 corresponding to the distance between the centers of the plurality of bumps 150 may be 55 μm or less. For example, in an embodiment, the pitch P1 corresponding to the distance between the centers of the plurality of bumps 150 may be 50 μm or less.

Here, the reduction of the pitch P1 of the plurality of bumps 150 is not achieved only by reducing the width of the bumps 150 .

For example, the pitch P1 of the plurality of bumps 150 is not only the width of the bump 150 , but also the width of the pad 121P of the first circuit pattern 121 , and the first circuit pattern 121 . ) is determined by the pitch, which is the distance between the centers of the pads 121P.

In other words, the plurality of bumps 150 are disposed on the pads 121P of the first circuit pattern 121 . Accordingly, the plurality of bumps 150 is substantially determined by the pitch of the pads 121P of the first circuit pattern 121 .

In this case, in the comparative example, there was a limit in reducing the pitch of the bumps due to the width of the bumps. Furthermore, in the comparative example, there is a limit in reducing the pitch of the bumps due to the limit of not only the width of the bumps but also the pitch of the pads connected to the bumps. That is, in the comparative example, the protective layer is included on the outermost side of the circuit board. In this case, as described above, the passivation layer has a size limit of the open region SOR. Accordingly, the pad in the comparative example had to have a width greater than or equal to a certain level due to the size limit of the open area SOR. Accordingly, the pitch between the pads in the comparative example had 100 μm or more.

Meanwhile, in the embodiment, the protective layer disposed on the outermost side of the circuit board is removed as described above. That is, in the embodiment, the protective layer disposed on the upper surface of the first insulating layer 111 is removed.

For example, in the embodiment, the upper surface of the first insulating layer 111 is exposed to the outside. Accordingly, in the embodiment, the first insulating layer 111 constitutes the outermost insulating layer in the circuit board. For example, in the comparative example, the outermost insulating layer of the circuit board was constituted by the protective layer. Alternatively, in the embodiment, the outermost insulating layer of the circuit board is configured as the upper surface of the first insulating layer 111 on which the first circuit pattern 121 is disposed.

Accordingly, in the embodiment, as the protective layer disposed on the upper surface of the first insulating layer 111 is removed, the pad ( 121P) solves the problem of having to maintain the width of a certain level or more. That is, in the embodiment, since the pad 121P can be formed without considering the size of the open region SOR of the protective layer, the width of the pad 121P can be reduced.

In other words, the width of the pad was determined not only by the size of the open region SOR of the passivation layer, but also by the size of the via.

That is, the first via 131 is disposed in the first insulating layer 111 . In addition, the lower surface of the pad 121P of the first circuit pattern 121 directly contacts the upper surface of the first via 131 . In this case, the first via 131 is formed through laser processing. In addition, the pad 121P is also used as a laser stopper during the laser processing. Accordingly, the width of the pad 121P may be determined by the width of the upper surface of the first via 131 in contact with the pad 121P. In this case, the first via 131 may have a trapezoidal shape having upper and lower widths different from each other. Here, in the embodiment, the width of the upper surface of the first via 131 is smaller than the width of the lower surface. For example, the width of the upper surface of the first via 131 may be 15 μm to 35 μm. For example, the width of the upper surface of the first via 131 may be 18 μm to 32 μm. For example, the width of the upper surface of the first via 131 may be 20 μm to 30 μm. Accordingly, in an embodiment, the width of the pad 121P of the first circuit pattern 121 may be determined to correspond to the width of the relatively small upper surface among the upper surface and the lower surface of the via 131 . Accordingly, in the embodiment, the width of the pad 121P of the first circuit pattern 121 may be reduced. Furthermore, in the embodiment, as the width of the pad 121P of the first circuit pattern 121 may be reduced, the pitch of the pad 121P may be reduced. Furthermore, in an embodiment, as the pitch of the pad 121P can be reduced, the pitch of the bump 150 may be reduced to correspond to the pitch of the pad 121P.

Consequently, in the embodiment, the pitch P1 of the bumps 150 may be reduced, and accordingly, a space in which a plurality of different application processor chips may be disposed on the circuit pattern 121 may be secured. . Accordingly, in the embodiment, the volume of the circuit board and the package board including the same can be reduced.

Meanwhile, the circuit board of the embodiment includes vias.

The via passes through the insulating layer 110 included in the circuit board of the embodiment, and thus may electrically connect between circuit patterns disposed on different layers. In this case, the via may be formed to pass through only one insulating layer, or alternatively, the via may be formed to pass through at least two or more insulating layers in common.

For example, the circuit board includes a first via 131 . The first via 131 may be formed to pass through the first insulating layer 111 . The first via 131 may electrically connect between the first circuit pattern 121 and the second circuit pattern 122 . For example, an upper surface of the first via 131 may be directly connected to a lower surface of the first circuit pattern 121 . For example, a lower surface of the first via 131 may be directly connected to an upper surface of the second circuit pattern 122 . In addition, the first circuit pattern 121 and the second circuit pattern 122 may be electrically connected to each other through the first via 131 to transmit a signal.

For example, the circuit board includes a second via 132 . The second via 132 may be formed to pass through the second insulating layer 112 . The second via 132 may electrically connect between the second circuit pattern 122 and the third circuit pattern 123 . For example, an upper surface of the second via 132 may be directly connected to a lower surface of the second circuit pattern 122 . For example, a lower surface of the second via 132 may be directly connected to an upper surface of the third circuit pattern 123 . Accordingly, the second circuit pattern 122 and the third circuit pattern 123 may be directly electrically connected to each other through the second via 132 to transmit a signal.

For example, the circuit board includes a third via 133 . The third via 133 may be formed to pass through the third insulating layer 113 . The third via 133 may electrically connect the third circuit pattern 123 and the fourth circuit pattern 124 . For example, an upper surface of the third via 133 may be directly connected to a lower surface of the third circuit pattern 123 . For example, a lower surface of the third via 133 may be directly connected to an upper surface of the fourth circuit pattern 124 . Accordingly, the third circuit pattern 123 and the fourth circuit pattern 124 may be electrically connected to each other to transmit a signal.

The via of the circuit board including the first via 131 , the second via 132 , and the third via 133 as described above forms a via hole passing through the insulating layer 110 , and the formed via hole It can be formed by filling the inside with a conductive material.

The via hole may be formed by any one of mechanical, laser, and chemical processing. When the via hole is formed by machining, methods such as milling, drilling, and routing can be used, and when formed by laser processing, UV or CO ₂ laser method is used. In the case of being formed by chemical processing, at least one insulating layer among the plurality of insulating layers may be opened by using a chemical containing aminosilane, ketones, or the like.

On the other hand, the processing by the laser is a cutting method that melts and evaporates a part of the material by concentrating optical energy on the surface to take a desired shape, and complex formation by a computer program can be easily processed. Even difficult composite materials can be machined.

In addition, the processing by the laser can have a cutting diameter of at least 0.005 mm, and has a wide advantage in a range of possible thicknesses.

As the laser processing drill, it is preferable to use a YAG (Yttrium Aluminum Garnet) laser, a CO ₂ laser, or an ultraviolet (UV) laser. The YAG laser is a laser that can process both the copper foil layer and the insulating layer, and the CO ₂ laser is a laser that can process only the insulating layer.

When the via hole is formed, the via of the embodiment may be formed by filling the inside of the via hole with a conductive material. The metal material forming the via may be any one material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd), and the conductivity For material filling, any one or a combination of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjetting and dispensing may be used.

Meanwhile, the circuit board of the embodiment may include the protective layer 140 . The protective layer 140 may be disposed only on the outermost side of any one of the outermost sides of the circuit pattern 121 . For example, the protective layer 140 in the embodiment may be disposed only on the lowermost side of the circuit board. For example, the protective layer 140 in the embodiment may be disposed on the lower surface of the third insulating layer 113 . For example, a protective layer may not be disposed on the upper surface of the first insulating layer 111 in the embodiment. Specifically, in an embodiment, the upper surface of each of the trace 121T and the pad 121P of the first circuit pattern 121 may be positioned lower than the upper surface of the first insulating layer 111 . Accordingly, in the embodiment, the trace 121T and the pad 121P of the first circuit pattern 121 may be protected by the first insulating layer 111 .

Accordingly, in the embodiment, the first insulating layer 111 can stably protect the first circuit pattern 121 even in a state in which the protective layer is not disposed, and thus reliability can be improved. In other words, in the embodiment, the protective layer to be disposed on the upper surface of the first insulating layer 111 may be deleted through the structural features of the first insulating layer 111 , and accordingly It is possible to reduce the overall thickness of the circuit board by the thickness. Furthermore, in the embodiment, the process of disposing the protective layer on the upper surface of the first insulating layer 111 may be omitted, thereby simplifying the manufacturing process and reducing manufacturing cost.

The protective layer 140 may be a solder resist, but is not limited thereto.

The protective layer 140 may include at least one opening (not shown).

For example, the protective layer 140 may have an opening exposing the lower surface of the fourth circuit pattern 124 . For example, the protective layer 140 may have an opening exposing a region (eg, a terminal pad portion connected to an external substrate) in which a solder ball is later disposed on a lower surface of the fourth circuit pattern 124 . have.

In this case, although not shown in the drawing, a surface treatment layer (not shown) may be disposed on the lower surface of the fourth circuit pattern 124 exposed through the opening of the protective layer 140 . The surface treatment layer may be formed to improve soldering characteristics while preventing corrosion and corrosion of the fourth circuit pattern 124 exposed through the protective layer 140 .

The surface treatment layer may be an Organic Solderability Preservative (OSP) layer. For example, the surface treatment layer may be an organic layer formed of an organic material such as benzimidazole coated on the lower surface of the fourth circuit pattern 124 .

However, the embodiment is not limited thereto. For example, the surface treatment layer may be a plating layer. For example, the surface treatment layer may include at least one of a nickel (Ni) plating layer, a palladium (Pd) plating layer, and a gold (Au) plating layer.

Meanwhile, in an embodiment, the circuit pattern and the vias may have a plurality of layer structures. However, in an embodiment, the first circuit pattern 121 of the circuit patterns has an ETS structure, and accordingly, the first circuit pattern 121 having an ETS structure may have a layer structure different from that of other circuit patterns or vias. .

For example, the first circuit pattern 121 may have a layer structure different from that of the second circuit pattern 122 , the third circuit pattern 123 , and the fourth circuit pattern 124 . For example, the number of layers of the first circuit pattern 121 may be smaller than the number of layers of the second circuit pattern 122 , the third circuit pattern 123 , and the fourth circuit pattern 124 .

For example, the first circuit pattern 121 may include only an electrolytic plating layer.

Alternatively, the second circuit pattern 122 , the third circuit pattern 123 , and the fourth circuit pattern 124 may each include a seed layer and an electrolytic plating layer.

However, in an embodiment, the first circuit pattern 121 may also include a seed layer. However, the seed layer of the first circuit pattern 121 may be substantially the first metal layer 151 of the bump 150 .

For example, the second circuit pattern 122 may include a seed layer 122-1 and an electrolytic plating layer 122-2. For example, the third circuit pattern 123 may include a seed layer 123 - 1 and an electrolytic plating layer 123 - 2 . For example, the fourth circuit pattern 124 may include a seed layer 124 - 1 and an electrolytic plating layer 124 . Also, correspondingly, the via included in the circuit board may include a seed layer and an electrolytic plating layer. For example, the first via 131 may include a seed layer 131-1 and an electrolytic plating layer 131-2. For example, the second via 132 may include a seed layer 132-1 and an electrolytic plating layer 132-2. For example, the third via 133 may include a seed layer 133 - 1 and an electrolytic plating layer 133 - 2 .

-Package Board-

5 is a view showing a package substrate according to an embodiment.

Referring to FIG. 5, the package substrate of the embodiment includes the circuit board shown in FIG. 2, at least one chip mounted on the circuit board, a molding layer for molding the chip, and the chip or the external substrate. Includes connections for

Hereinafter, a package substrate including the circuit board of FIG. 2 will be described.

For example, the package substrate 200 includes a first connection part 210 and a second connection part 240 disposed on the first circuit pattern 121 disposed on the outermost side of the circuit board. Specifically, the package substrate according to the embodiment includes the first connection part 210 and the second connection part 240 disposed on the bump 150 disposed on the pad 121P of the first circuit pattern 121 . .

The first connection part 210 and the second connection part 240 may have the same shape or different shapes from each other.

For example, the first connection part 210 and the second connection part 240 may have a hexahedral shape. For example, the cross-sections of the first connection part 210 and the second connection part 240 may include a rectangular shape. The cross-sections of the first connection part 210 and the second connection part 240 may include a rectangle or a square. For example, the first connection part 210 and the second connection part 240 may include a spherical shape. For example, the cross-sections of the first connection part 210 and the second connection part 240 may include a circular shape or a semicircular shape. For example, the cross-sections of the first connection part 210 and the second connection part 240 may include a partially or wholly rounded shape. The cross-sectional shapes of the first connection part 210 and the second connection part 240 may be flat on one side and curved on the other side. The first connection part 210 and the second connection part 240 may be solder balls, but are not limited thereto.

In an embodiment, the first chip 220 disposed on the first connection part 210 may be included. The first chip 220 may be a first processor chip. For example, the first chip 220 may be an application processor (AP) chip among a central processor (eg, CPU), a graphic processor (eg, GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller. . The terminal 230 of the first chip 220 may be electrically connected to the pad 121P of the first circuit pattern 121 through the first connection part 210 .

In addition, in an embodiment, the second chip 250 disposed on the second connection part 240 may be included. The second chip 250 may be a second processor chip. For example, the second chip 250 may include the first chip 220 among a central processor (eg, CPU), a graphic processor (eg, GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller. may be another type of application processor (AP) chip. The terminal 260 of the second chip 250 may be electrically connected to the pad 121P of the first circuit pattern 121 through the second connection part 240 .

For example, the first chip 220 may be a central processor chip, and the second chip 250 may be a graphics processor chip, but is not limited thereto.

Meanwhile, the first chip 220 and the second chip 250 may be spaced apart from each other by a predetermined distance on the circuit board. For example, a spacing between the first chip 220 and the second chip 250 may be 150 μm or less. For example, the spacing between the first chip 220 and the second chip 250 may be 120 μm or less. For example, a spacing between the first chip 220 and the second chip 250 may be 100 μm or less.

Preferably, a spacing between the first chip 220 and the second chip 250 may be in a range of 60 μm to 150 μm. Preferably, a distance between the first chip 220 and the second chip 250 may be in a range of 70 μm to 120 μm. Preferably, the spacing between the first chip 220 and the second chip 250 may be in a range of 80 μm to 110 μm. When the distance between the first chip 220 and the second chip 250 is less than 60 μm, the first chip 220 and the second chip 250 may interfere with each other, A problem may occur in the operation reliability of the first chip 220 or the second chip 250 . When the distance between the first chip 220 and the second chip 250 is greater than 150 μm, as the distance between the first chip 220 and the second chip 250 increases, signal transmission losses may increase. When the spacing between the first chip 220 and the second chip 250 is greater than 150 μm, the volume of the package substrate 200 may increase.

The package substrate 200 may include a molding layer 270 . The molding layer 270 may be disposed to cover the first chip 220 and the second chip 250 . For example, the molding layer 270 may be an epoxy mold compound (EMC) formed to protect the mounted first chip 220 and the second chip 250 , but is not limited thereto.

The molding layer 270 may directly contact an upper surface of the first insulating layer 111 disposed on the uppermost side of the circuit board. That is, in the circuit board of the first embodiment, the protective layer is not disposed on the uppermost side, and accordingly, the upper surface of the first insulating layer 111 may be in direct contact with the molding layer 270 .

In this case, the trace 121T and the bump 150 of the first circuit pattern 121 include a curved surface.

For example, the upper surface of the trace 121T of the first circuit pattern 121 includes a curved surface. In addition, the second portion 121P2 of the pad 121P of the first circuit pattern 121 includes a curved surface. Accordingly, in the embodiment, the contact area between the circuit board and the molding layer may be increased, and the bonding force therebetween may be improved in proportion to this.

In this case, the molding layer 270 may have a low dielectric constant in order to improve heat dissipation characteristics. For example, the dielectric constant Dk of the molding layer 270 may be 0.2 to 10. For example, the dielectric constant Dk of the molding layer 270 may be 0.5 to 8. For example, the dielectric constant Dk of the molding layer 270 may be 0.8 to 5. Accordingly, in the embodiment, the molding layer 270 has a low dielectric constant, so that heat dissipation characteristics against heat generated by the first chip 220 and/or the second chip 250 can be improved.

Meanwhile, the package substrate 200 may include a third connection part 280 disposed on the lowermost side of the circuit board. The third connection part 280 may be disposed on a lower surface of the fourth circuit pattern 124 exposed through the protective layer 140 .

-Manufacturing method-

Hereinafter, a method of manufacturing a circuit board according to an embodiment will be described. Specifically, a method of manufacturing the circuit board shown in FIG. 2 will be described in the order of the steps below.

6 to 20 are views showing the manufacturing method of the circuit board shown in FIG. 2 in order of process.

Referring to FIG. 6 , in the embodiment, a basic material for manufacturing a circuit board may be prepared by the ETS method.

For example, in the embodiment, the carrier insulating layer 311 and the carrier board 310 in which the metal layer 312 is disposed on at least one surface of the carrier insulating layer 311 may be prepared. In this case, the metal layer 312 may be disposed on only one of the first and second surfaces of the carrier insulating layer 311 , or alternatively, may be disposed on both surfaces of the carrier insulating layer 311 . For example, the metal layer 312 is disposed on only one surface of the carrier insulating layer 311 , and accordingly, the ETS process for manufacturing the circuit board may be performed only on the one surface. Alternatively, the metal layer 312 may be disposed on both surfaces of the carrier insulating layer 311 , and accordingly, an ETS process for manufacturing a circuit board may be simultaneously performed on both surfaces of the carrier board 311 . In this case, two circuit boards can be manufactured at once.

The metal layer 312 may be formed by electroless plating on the carrier insulating layer 311 . Alternatively, the carrier insulating layer 311 and the metal layer 312 may be copper clad laminate (CCL). That is, the metal layer 312 may be a copper foil layer. For example, the metal layer 312 may be a copper foil. For example, the metal layer 312 may be an electroless plating layer formed on the carrier insulating layer 311 . That is, the metal layer 312 is the first metal layer formed in the manufacturing process of the circuit board. In addition, the metal layer 312 may be used as a seed layer of the first circuit pattern 121 to be formed in a subsequent process.

Next, referring to FIG. 7 , in the embodiment, a first dry film 320 is formed on the metal layer 312 . In this case, the first dry film 320 may be disposed to cover the entirety of the metal layer 312 .

Next, referring to FIG. 8 , in the embodiment, the formed first dry film 320 may be exposed and developed.

Specifically, in the embodiment, the process of forming the opening 321 exposing the surface of the metal layer 312 by exposing and developing the first dry film 320 may be performed.

The opening 321 may be formed on the surface of the metal layer 312 to correspond to a region where the first circuit pattern 121 is to be formed.

Next, referring to FIG. 9 , in the embodiment, the metal layer 312 is electrolytically plated as a seed layer to form a first circuit pattern 121 filling the opening 321 of the first dry film 320 . The forming process may proceed.

In this case, in an embodiment, a curing process of heat-treating the first dry film 320 may be additionally performed before the electrolytic plating process of the first circuit pattern 121 . For example, in an embodiment, a process of curing the first dry film 320 may be performed after the exposure and development process of the first dry film 320 . The curing of the first dry film 320 may include curing using ultraviolet rays and curing using infrared rays. For example, in an embodiment, the first dry film 320 may be cured using ultraviolet rays in a range of 5 mV to 100 mV. Alternatively, in the embodiment, the first dry film 320 may be cured by infrared heat. As described above, in the embodiment, the bonding force between the metal layer 312 and the first dry film 320 may be improved by further performing the process of curing the first dry film 320 . Accordingly, in the embodiment, the first circuit pattern 121 formed in the opening 321 can be miniaturized according to the improvement of the bonding force between the first dry film 320 and the metal layer 312 . For example, in the embodiment, the line width and spacing of the traces 121T of the first circuit pattern 121 may be reduced by further performing the process of curing the first dry film 320 .

Next, referring to FIG. 10 , in the embodiment, when the first circuit pattern 121 is formed, a process of removing the first dry film 320 may be performed. And, in an embodiment, as the first dry film 320 is removed, a process of pre-processing the first circuit pattern 121 may be performed. For example, in an embodiment, a process of imparting a surface roughness of a predetermined level or higher to the surface of the first circuit pattern 121 may be performed. For example, in the embodiment, the first circuit pattern 121 is surface-treated so that the surface of the first circuit pattern 121 has a 10-point average surface roughness Rz in the range of 0.01 μm to 0.5 μm. can make it

Next, in the embodiment, as shown in FIG. 11 , a first insulating layer 111 covering the first circuit pattern 121 may be formed on the metal layer 312 .

Next, referring to FIG. 12 , in the embodiment, a process of forming a via hole VH in the first insulating layer 111 may be performed. The via hole VH may be formed by laser processing, but is not limited thereto.

Next, referring to FIG. 13 , in the embodiment, a process of forming the first via 131 and the second circuit pattern 122 may be performed.

Specifically, in the embodiment, a seed layer is formed on the lower surface of the first insulating layer 111 and the inner wall of the via hole VH, and electrolytic plating is performed using the seed layer to conduct the second circuit pattern 122 . ) and the process of forming the first via 131 may be performed.

Next, in the embodiment, as shown in FIG. 14 , the lamination process may be performed by repeating the processes shown in FIGS. 11 to 13 .

Specifically, in the embodiment, the process of forming the second insulating layer 112 covering the second circuit pattern 122 on the lower surface of the first insulating layer 111 may be performed. Next, in the embodiment, a process of forming the second via 132 penetrating the second insulating layer 112 and the third circuit pattern 123 protruding from the lower surface of the second insulating layer 112 is performed. can

Next, in the embodiment, as shown in FIG. 15 , an additional lamination process may be performed by repeating the process shown in FIG. 14 .

Specifically, in the embodiment, the process of forming the third insulating layer 113 covering the third circuit pattern 123 on the lower surface of the second insulating layer 112 may be performed. Next, in the embodiment, a process of forming the third via 133 penetrating the third insulating layer 113 and the fourth circuit pattern 124 protruding from the lower surface of the third insulating layer 113 is performed. can

Next, as shown in FIG. 16 , in the embodiment, a process of removing the carrier board may be performed from the circuit board manufactured as described above. For example, in the embodiment, a process of separating the carrier insulating layer 311 and the metal layer 312 from each other may be performed in the carrier board 310 . Accordingly, in the circuit board of the embodiment, the metal layer 312 included in the carrier board remains on the outermost side.

Next, in the embodiment, a process of forming the second dry film 340 on the upper surface of the metal layer 312 may be performed. In this case, the second dry film 340 may be formed to have a predetermined height on the metal layer 312 . For example, the second dry film 340 may have a height corresponding to the height H1 of the bump 150 .

For example, the height of the second dry film 340 may be higher than the height H1 of the bump 150 . For example, the height of the second dry film 340 may be 100 μm or more. For example, the height of the second dry film 340 may be 110 μm or more. For example, the height of the second dry film 340 may be 150 μm or more. Accordingly, in the embodiment, the height H1 of the bump 150 may be determined to correspond to the height of the second dry film 340 . Accordingly, in the embodiment, the height H1 of the bump 150 may be 100 μm or more. For example, the height of the bump 150 in the embodiment may be 110 μm or more. For example, in the embodiment, the height of the bump 150 may be 150 μm or more.

Next, as shown in FIG. 17 , in the embodiment, a process of forming the opening 341 by exposing and developing the second dry film 340 may be performed. For example, in an embodiment, the second dry film 340 may be exposed and developed to form an opening 341 exposing the pad 121P of the first circuit pattern 121 .

Next, in the embodiment, as shown in FIG. 18 , electroplating the metal layer 312 as a seed layer to form the second metal layer 152 of the bump 150 filling the opening 341 . process can proceed.

Next, as shown in FIG. 19 , in the embodiment, when the process of forming the second metal layer 152 of the bump 150 is completed, the process of removing the second dry film 340 may be performed. .

Thereafter, as shown in FIG. 20 , in the embodiment, a process of removing the metal layer 312 by nickname may be performed. For example, in the embodiment, a process of forming the first metal layer 151 constituting the bump 150 is performed by removing a portion that does not overlap the second metal layer 152 in the metal layer 312 . can

Accordingly, in the embodiment, in the process of removing the metal layer 312 , at least a portion of the trace 121T of the first circuit pattern 121 is also removed, so that at least a portion of the upper surface of the trace 121T is It may be positioned lower than the upper surface of the first insulating layer 111 . For example, a central portion of the upper surface of the trace 121T may be lower than an edge portion. For example, the upper surface of the trace 121T may include a curved surface concave in the downward direction.

Also, like the trace 121T, a part of the pad 121P of the first circuit pattern 121 may also be partially removed in the process of removing the metal layer 312 . Accordingly, the pad 121P of the first circuit pattern 121 may include a first portion 121P1 on which the bump 150 is disposed and a second portion 121P2 other than the first portion 121P1. have. Also, the first portion 121P1 and the second portion 121P2 of the pad 121P of the first circuit pattern 121 may have different shapes. For example, the top surface of the first part 121P1 of the pad 121P of the first circuit pattern 121 may be located on a different plane from the top surface of the second part 121P2 . For example, the upper surface of the first portion 121P1 of the pad 121P of the first circuit pattern 121 may be positioned higher than the upper surface of the second portion 121P2. For example, a top surface of the first portion 121P1 of the pad 121P of the first circuit pattern 121 may be flat. For example, the upper surface of the second portion 121P2 of the pad 121P of the first circuit pattern 121 may include a curved surface. In detail, the thickness of the second portion 121P2 of the pad 121P may decrease as the distance from the first portion 121P1 increases.

Accordingly, the top surface of the first portion 121P1 of the pad 121P of the first circuit pattern 121 in the embodiment may be disposed on the same plane as the top surface of the first insulating layer 111 . That is, the first portion 121P1 and the first insulating layer 111 of the pad 121P are disposed on one and the same metal layer (a seed layer, which will be described later). Accordingly, the first portion 121P1 of the pad 121P and the upper surfaces of the first insulating layer 111 may be positioned on the same plane. Also, in an embodiment, the upper surface of the second portion 121P2 of the pad 121P may be positioned lower than the upper surface of the first insulating layer 111 . For example, the upper surface of the second portion 121P2 of the pad 121P has a curved surface, and thus the first insulating layer 111 is further away from the first portion 121P1 of the pad 121P. The step with the upper surface of the may increase. For example, the height of the top surface of the second part 121P2 of the pad 121P may correspond to the height of the top surface of the first insulating layer 111 at a position adjacent to the first part 121P1. In addition, the upper surface of the second portion 121P2 of the pad 121P may gradually become lower than the height of the upper surface of the first insulating layer 111 as the distance from the first portion 121P1 increases.

Features, structures, effects, etc. described in the above embodiments are included in at least one embodiment, and are not necessarily limited to only one embodiment. Furthermore, features, structures, effects, etc. illustrated in each embodiment can be combined or modified for other embodiments by those of ordinary skill in the art to which the embodiments belong. Accordingly, the contents related to such combinations and modifications should be interpreted as being included in the scope of the embodiments.

In the above, the embodiment has been mainly described, but this is only an example and does not limit the embodiment, and those of ordinary skill in the art to which the embodiment pertains are provided with several examples not illustrated above within a range that does not depart from the essential characteristics of the embodiment. It can be seen that variations and applications of branches are possible. For example, each component specifically shown in the embodiment can be implemented by modification. And differences related to such modifications and applications should be interpreted as being included in the scope of the embodiments set forth in the appended claims.

Claims (16)

a first insulating layer;
a first circuit pattern disposed on the first insulating layer and including a pad; and
a bump disposed on the pad of the first circuit pattern;
The bump is
a first metal layer disposed on the pad of the first circuit pattern;
a second metal layer disposed on the first metal layer;
The width of the first metal layer corresponds to the width of the second metal layer,
circuit board. According to claim 1,
The first insulating layer is a first outermost insulating layer disposed on the uppermost side,
The first circuit pattern is a first outermost circuit pattern buried in the upper surface of the first outermost insulating layer,
circuit board. 3. The method of claim 2,
The pad is
a first portion overlapping the bump in a vertical direction;
a second part other than the first part;
The height of the upper surface of the first part is different from the height of the upper surface of the second part,
circuit board. 4. The method of claim 3,
an upper surface of the first portion of the pad,
disposed on the same plane as the upper surface of the first insulating layer,
circuit board. 5. The method of claim 3 or 4,
an upper surface of the second part of the pad,
located lower than the first portion of the pad or an upper surface of the first insulating layer,
circuit board. 5. The method of claim 3 or 4,
a top surface of the second portion of the pad comprises a curved surface;
circuit board. 5. The method according to any one of claims 1 to 4,
The first metal layer,
a seed layer of the first circuit pattern and the second metal layer;
circuit board. 5. The method according to any one of claims 1 to 4,
The width of the bump is less than 40% of the height of the bump,
circuit board. 9. The method of claim 8,
The height of the bump is 100㎛ or more,
circuit board. 5. The method according to any one of claims 1 to 4,
The first circuit pattern includes a plurality of pads,
the bumps include a plurality of bumps disposed on the plurality of pads;
The distance between the centers of the plurality of bumps is 60 μm or less,
circuit board. 5. The method according to any one of claims 1 to 4,
the first circuit pattern includes a trace,
At least a portion of the upper surface of the trace is located lower than the upper surface of the first insulating layer,
circuit board. 12. The method of claim 11,
The upper surface of the trace of the first circuit pattern comprises a curved surface,
circuit board. a plurality of insulating layers;
a first circuit pattern disposed on an upper surface of a first outermost insulating layer among the plurality of insulating layers and including a trace and a pad;
a second circuit pattern and a third circuit pattern disposed between the plurality of insulating layers;
a fourth circuit pattern disposed on a lower surface of the second outermost insulating layer among the plurality of insulating layers;
a bump disposed on the pad of the first circuit pattern;
a first connection part disposed on an upper surface of the pad;
a chip disposed on the first connector; and
and a molding layer disposed on the first outermost insulating layer and molding the chip,
The bump is
a first metal layer disposed on the pad of the first circuit pattern;
a second metal layer disposed on the first metal layer;
The width of the first metal layer corresponds to the width of the second metal layer,
The pad is
a first portion overlapping the bump in a vertical direction;
a second part other than the first part;
The height of the upper surface of the first part is different from the height of the upper surface of the second part,
The first metal layer is a seed layer of the first circuit pattern and the second metal layer,
package board. 14. The method of claim 13,
The molding layer is
In direct contact with the upper surface of the insulating layer disposed on the first outermost,
package board. 14. The method of claim 13,
The second portion of the pad of the first circuit pattern includes a curved surface,
At least a portion of the lower surface of the molding layer,
Containing a curved surface corresponding to the curved surface of the second portion,
package board. 14. The method of claim 13,
The chip includes a first chip and a second chip disposed to be spaced apart from each other in the width direction,
The first chip corresponds to a central processor (CPU),
The second chip corresponds to a graphics processor (GPU),
package board.

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