KR20220138205A - Circuit board and package substrate including the same - Google Patents

Abstract

A circuit board according to an embodiment includes: a first insulating layer; multiple first vias passing through the first insulating layer; a first circuit pattern disposed on an upper surface of the first insulating layer and including multiple pads connected to upper surfaces of the multiple first vias; and a second circuit pattern positioned on a lower surface of the first insulating layer and including multiple pads connected to lower surfaces of the multiple first vias. The first insulating layer is a first outermost insulating layer disposed on a first outermost side of the circuit board, the upper surface of the first insulating layer is exposed to the first outermost side to form a first outermost side surface of the circuit board, and a pitch corresponding to a distance between the centers of the multiple pads in the first circuit pattern is 100㎛ or less. The present invention aims to provide a circuit board having a new structure capable of minimizing the pitch of mounting pads and a package substrate including the circuit board.

Description

Circuit board and package board including same {CIRCUIT BOARD AND PACKAGE SUBSTRATE INCLUDING THE SAME}

The embodiment relates to a circuit board, and more particularly, to a circuit board capable of minimizing a pitch between a plurality of adjacent pads, and a package board including the same.

As the performance of electric/electronic products progresses, techniques for attaching a larger number of packages to a substrate having a limited size are being proposed and studied. However, since a general package is based on mounting one semiconductor chip, there is a limit in obtaining desired performance.

A typical package substrate has a form in which a processor package in which a processor chip is disposed and a memory package to which a memory chip is attached are connected as one. Such a package substrate has the advantage of reducing a chip mounting area and enabling high-speed signals through a short pass by manufacturing the processor chip and the memory chip as one integrated package.

Due to these advantages, the package substrate as described above is widely applied to mobile devices and the like.

On the other hand, in recent years, due to the high specification of electronic devices such as mobile devices and the adoption of high bandwidth memory (HBM), a circuit board capable of mounting a plurality of chips on one package board is required.

However, the conventional circuit board for a package has a size limitation due to a design limitation of a pad on which a chip is mounted. For example, in a conventional circuit board for a package, the size of a minimum via, a size of a pad according to the size of the via, a size of a trace disposed between a plurality of pads, and an opening of a solder resist for opening the surface of the pad The size of the Solder resist open region (SOR) is limited. For example, in the conventional circuit board for package, the pitch of the pad for chip mounting exceeds 100 micrometers. Accordingly, when the conventional circuit board for a package is used, the number of chips that can be mounted in a limited space can be reduced. For example, in the related art, there is a problem in that the volume of the circuit board increases in order to mount all of the plurality of chips due to the limitation of the pitch of the pads.

In addition, recently, a circuit board having a fine pitch using a photosensitive material (eg, PID) has been developed. However, the circuit board made of the photosensitive material is vulnerable to warpage, and there is a problem in that the manufacturing cost is high compared to the circuit board manufactured using the prepreg.

In the embodiment, an object of the present invention is to provide a circuit board having a novel structure capable of minimizing the pitch of mounting pads and a package board including the same.

In addition, an embodiment is to provide a circuit board having a new structure such that the outermost chip mounting pad has a fine pitch of 100 μm or less in a circuit board made of a prepreg, and a package board including the same.

In addition, in the embodiment, by removing the solder resist disposed on the outermost layer of the circuit board, the circuit board of a new structure capable of solving the size restriction of the pad due to the solder resist open region (SOR), and including the same An object of the present invention is to provide a package substrate for

The technical tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks not mentioned are clear to those of ordinary skill in the art to which the proposed embodiment belongs from the description below. will be able to understand

A circuit board according to an embodiment includes a first insulating layer; a plurality of first vias passing through the first insulating layer; a first circuit pattern disposed on an upper surface of the first insulating layer and including a plurality of pads connected to upper surfaces of the plurality of first vias; and a second circuit pattern disposed on a lower surface of the first insulating layer and including a plurality of pads connected to lower surfaces of the plurality of first vias, wherein the first insulating layer is a first outermost side of the circuit board. a first outermost insulating layer disposed on The pitch corresponding to the distance between the centers of the plurality of pads is 100 µm or less.

In addition, the plurality of pads of the first circuit pattern are disposed to protrude above the upper surface of the first insulating layer.

In addition, the width of the upper surface of the first via is greater than the width of the lower surface, and the pad of the first circuit pattern has a width in the range of 101% to 130% of the width of the upper surface of the first via.

In addition, the width of the upper surface of the first via is greater than the width of the lower surface, and the pad of the first circuit pattern has a width smaller than the width of the upper surface of the first via.

In addition, the pad of the first circuit pattern is smaller than the width of the pad of the second circuit pattern and is larger than the width of the lower surface of the first via.

In addition, the first circuit pattern includes a trace connected to a pad of the first circuit pattern, and the trace includes a portion in direct contact with the pad of the first circuit pattern and an upper surface of the first via.

In addition, the first circuit pattern may include a trace disposed on an upper surface of the first insulating layer and disposed between the plurality of pads of the first circuit pattern.

In addition, the plurality of pads of the first circuit pattern are disposed to be embedded in the upper surface of the first insulating layer.

In addition, the width of the upper surface of the first via is smaller than the width of the lower surface, and the pad of the first circuit pattern has a width in the range of 101% to 130% of the width of the upper surface of the first via.

In addition, the width of the upper surface of the first via is smaller than the width of the lower surface, the pad of the first circuit pattern has a width smaller than the width of the upper surface of the first via, and the first via has a width of the first circuit pattern is placed around the side of the pad.

In addition, the first circuit pattern includes a trace, and the trace is in direct contact with a side surface of the first via.

In addition, the circuit board may include a first surface treatment layer disposed on an upper surface of the pad of the first circuit pattern.

In addition, a pitch corresponding to a distance between the centers of the plurality of pads of the first circuit pattern is 90 μm or less.

In addition, a second insulating layer disposed under the first insulating layer; and a protective layer disposed on a lower surface of the second insulating layer, wherein the second insulating layer is a second outermost insulating layer disposed on a second outermost side opposite to the first outermost side of the circuit board, A lower surface of the protective layer is exposed as the second outermost surface to constitute a second outermost surface of the circuit board.

On the other hand, the package substrate according to the embodiment includes a first insulating layer; a first via passing through the first insulating layer and including 1-1 vias and 1-2 vias spaced apart from each other in a width direction; A first pad disposed on an upper surface of the 1-1 via, a second pad disposed on an upper surface of the first-2 via, and an upper surface of the first insulating layer between the first pad and the second pad a first circuit pattern including a first trace to be formed; a second circuit pattern disposed on a lower surface of the first insulating layer and connected to a lower surface of the second via; a first surface treatment layer disposed on the first pad and the second pad; a first adhesive portion disposed on the first surface treatment layer; a chip attached to the first adhesive part; and a molding layer disposed on an upper surface of the first insulating layer and molding the chip, wherein the molding layer is in direct contact with the upper surface of the first insulating layer and is disposed to cover the first circuit pattern, A pitch corresponding to a distance from a center of the first pad of the first circuit pattern to a center of the second pad of the first circuit pattern is 100 μm or less.

In addition, a width of the first adhesive portion is smaller than a width of the first pad and a width of the second pad.

In addition, the chip includes a first chip and a second chip disposed to be spaced apart from each other in a width direction, the first chip corresponding to a central processor (CPU), the second chip to the graphic processor (GPU) respond

A circuit board according to an embodiment includes a mounting pad disposed in an area on which a chip is mounted. In this case, the mounting pad in the comparative example has a larger width than a solder resist open region (SOR) disposed on the outermost side of the circuit board, and thus the mounting pad has a pitch larger than 110 μm. do. On the contrary, in the circuit board according to the embodiment, the solder resist disposed on the outermost side of the circuit board is removed. Accordingly, the width of the mounting pad in the embodiment is not affected by the size of the solder resist open region (SOR), and thus the width of the mounting pad may be reduced compared to the comparative example. Accordingly, in the embodiment, since the pitch of the mounting pad can be reduced compared to the comparative example, more chips can be mounted in a limited space, and thus the volume of the circuit board and further the volume of the package board can be reduced.

In addition, in the embodiment, as the pitch decreases as described above, the length of the transmission line connecting between the terminals of the chip mounted on the circuit board can be reduced, and thus the communication performance can be improved by minimizing the signal transmission loss. have.

1A is a diagram illustrating a circuit board according to a comparative example.
1B is an enlarged view of area A in the circuit board of FIG. 1A.
1C is a view for explaining a pitch of mounting pads in a circuit board according to a comparative example.
2 is a view showing a circuit board according to the first embodiment.
FIG. 3A is an enlarged view of a region T1 of FIG. 2 .
FIG. 3B is an enlarged view of area B1 of FIG. 2 .
4 is a view for explaining a pitch of a mounting pad according to the first embodiment.
5A is a diagram illustrating a circuit board according to a first modified example.
5B is a diagram illustrating a circuit board according to a second modified example.
5C is a diagram illustrating a circuit board according to a third modified example.
5D is a diagram illustrating a circuit board according to a fourth modified example.
5E is a diagram illustrating a circuit board according to a fifth modified example.
6 is a diagram illustrating a circuit board according to a second embodiment.
FIG. 7 is an enlarged view of the outermost side of FIG. 6 .
8A is a diagram illustrating a circuit board according to a first modified example.
8B is a diagram illustrating a circuit board according to a second modified example.
8C is a diagram illustrating a circuit board according to a third modified example.
9A to 9F are views for explaining the manufacturing method of the circuit board shown in FIG. 2 in order of process.
10A to 10H are views for explaining the manufacturing method of the circuit board shown in FIG. 6 in order of process.
11 is a view showing a package substrate according to the first embodiment.
12 is a view showing a package substrate according to a second embodiment.

Hereinafter, the embodiments disclosed in the present specification will be described in detail with reference to the accompanying drawings, but the same or similar components are assigned the same reference numerals regardless of reference numerals, and redundant description thereof will be omitted. The suffixes "module" and "part" for components used in the following description are given or mixed in consideration of only the ease of writing the specification, and do not have distinct meanings or roles by themselves. In addition, in describing the embodiments disclosed in the present specification, if it is determined that detailed descriptions of related known technologies may obscure the gist of the embodiments disclosed in the present specification, the detailed description thereof will be omitted. In addition, the accompanying drawings are only for easy understanding of the embodiments disclosed in this specification, and the technical idea disclosed herein is not limited by the accompanying drawings, and all changes included in the spirit and scope of the present invention , should be understood to include equivalents or substitutes.

Terms including ordinal numbers such as first, second, etc. may be used to describe various elements, but the elements are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another.

When a component is referred to as being “connected” or “connected” to another component, it may be directly connected or connected to the other component, but it is understood that other components may exist in between. it should be On the other hand, when it is said that a certain element is "directly connected" or "directly connected" to another element, it should be understood that the other element does not exist in the middle.

The singular expression includes the plural expression unless the context clearly dictates otherwise.

In the present application, terms such as “comprises” or “have” are intended to designate that a feature, number, step, operation, component, part, or combination thereof described in the specification exists, but one or more other features It is to be understood that this does not preclude the possibility of the presence or addition of numbers, steps, operations, components, parts, or combinations thereof.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

- Comparative Example -

Prior to the description of the embodiment, a comparative example compared with the circuit board of the embodiment of the present application will be described.

1A is a view showing a circuit board according to a comparative example, FIG. 1B is an enlarged view of area A in the circuit board of FIG. 1A, and FIG. 1C is a view for explaining the pitch of mounting pads in the circuit board according to the comparative example .

Referring to FIG. 1A , in a circuit board according to a comparative example, a pitch between adjacent pads (specifically, a mounting pad on which a chip is mounted) exceeds 110 μm due to design limitations of vias and pads. The circuit board in the comparative example has a core type structure.

The circuit board according to the comparative example includes an insulating layer, a circuit pattern, a via, and a protective layer.

The insulating layer includes a core layer 1 , a first insulating layer 5 and a second insulating layer 8 . In the circuit board of the comparative example, the first insulating layer 5 and the second insulating layer 8 are disposed on the core layer 1 as the center, and the first insulating layer 5 and the second insulating layer 8 have a symmetrical structure thereon. The core layer 1 is CCL (Clad Copper Laminate) including a prepreg, or includes a material such as silicon, glass, and ceramic used in an interposer.

The first insulating layer 5 and the second insulating layer 8 are respectively disposed on the upper and lower surfaces of the core layer 1 . The first insulating layer 5 and the second insulating layer 8 include prepregs. For example, the first insulating layer 5 and the second insulating layer 8 include a resin and reinforcing fibers in the resin.

The first circuit pattern 2 is disposed on the lower surface of the first insulating layer 5 . In addition, the first circuit pattern 2 is disposed on the upper surface of the core layer 1 .

The second circuit pattern 7 is disposed on the upper surface of the first insulating layer 5 . The second circuit pattern 7 is disposed to protrude above the upper surface of the first insulating layer 5 .

The third circuit pattern 3 is disposed on the upper surface of the second insulating layer 8 . In addition, the third circuit pattern 3 is disposed on the lower surface of the second insulating layer 8 .

The fourth circuit pattern 10 is disposed on the lower surface of the second insulating layer 8 . The fourth circuit pattern 10 is disposed to protrude below the lower surface of the second insulating layer 8 .

At this time, in the circuit board of the comparative example, the first insulating layer 5 is an insulating layer disposed on the first outermost or uppermost side in the multilayer structure, and the second insulating layer 8 is on the second outermost or lowermost side of the circuit board. placed insulating layer.

The first circuit pattern 2 , the second circuit pattern 7 , the third circuit pattern 3 , and the fourth circuit pattern 10 include pads and traces, respectively. The pad is a portion in which an adhesive portion (not shown) connected to a via, a chip is mounted, or a main board of an external substrate is disposed. The trace is a signal line extending long from the pad.

A via is disposed through each insulating layer. For example, the first via 6 is disposed through the first insulating layer 5 . One end of the first via 6 is connected to the first circuit pattern 2 , and the other end is connected to the second circuit pattern 7 . For example, the second via 4 is disposed through the core layer 1 . For example, the third via 9 is disposed passing through the second insulating layer 8 . For example, one end of the third via 9 is connected to the third circuit pattern 3 and the other end is connected to the fourth circuit pattern 10 .

The first protective layer 11 and the second protective layer 12 are respectively disposed on the upper surface of the first insulating layer 5 and the lower surface of the second insulating layer 8 . The first protective layer 11 and the second protective layer 12 have openings exposing the surfaces of the second circuit pattern 7 and the fourth circuit pattern 10 , respectively.

In this case, in the circuit board of the comparative example, one of the first and second outermost circuit patterns includes a mounting part on which a chip is mounted, and the other includes a terminal part connected to the main board of the external board.

For example, in the comparative example, the second circuit pattern 7 disposed on the first outermost side includes a mounting pad on which a chip is mounted, and the fourth circuit pattern 10 disposed on the second outermost side is an external substrate. It includes a terminal pad to which the main board is connected.

Specifically, in the circuit board of the comparative example of FIG. 1A , the second circuit pattern 7 includes a mounting pad, and the fourth circuit pattern 10 includes a terminal pad.

In this case, the circuit board in the comparative example has limitations in the size according to the design of the via and the size according to the design of the mounting pad, so that the pitch, which is the distance between the centers of the neighboring mounting pads, exceeds 110 μm.

That is, the first insulating layer 5 in the comparative example includes a prepreg. At this time, in order to form a via hole in the first insulating layer 5, laser processing should be performed. At this time, due to the characteristics of general laser processing, the first via 6 has a size greater than or equal to a certain level.

For example, the width of the first surface and the width of the second surface are different from the width of the first via 6 by filling the inside of the via hole formed by laser processing. For example, the width w1 of the first surface or the upper surface of the first via 6 is greater than the width w2 of the second surface or the lower surface of the first via 6 . In addition, in the circuit board including the core layer, the first outermost mounting pad is connected to the first surface or the upper surface that is the wide portion of the first via 6 .

In this case, the width w1 of the first surface of the first via 6 has a minimum of 45 μm or more due to the limitation of the laser process. In addition, the width w2 of the second surface of the first via 6 has a width of 40 µm or more, which is 80% of the width w1 of the first surface.

In addition, in the comparative example, the width w3 of the mounting pads 7-2a and 7-2b of the second circuit pattern 7 in direct contact with the first surface of the first via 6 is at least 70 μm or more. have That is, in the comparative example, the mounting pads 7 - 2a and 7 - 2b of the second circuit pattern 7 connected to the upper surface of the first via 6 are formed on the first surface of the first via 6 . It has a width more than a certain level than the width w1. In addition, the width w4 of the pad of the first circuit pattern 2 in direct contact with the second surface or the lower surface of the first insulating layer 5 is at least 67 μm. That is, the pad of the first circuit pattern 2 has a width greater than or equal to the width w2 of the second surface of the first via 6 .

Accordingly, the width (w5=(w3-w1)/2) of the portion affecting the pitch of the mounting pads 7-2a and 7-2b of the second circuit pattern 7 and the neighboring pads is the minimum. It is about 12.5 μm. That is, the horizontal straight line distance w5 in the width direction from one end of the first surface of the via 40 to one end of the mounting pads 7-2a and 7-2b of the second circuit pattern 7 is It is at least 12.5 μm. In addition, in the pad of the first circuit pattern 2 , the width (w6=(w4-w2)/2) of the portion affecting the pitch with respect to the neighboring pad is at least 13.5 μm. That is, the horizontal straight line distance w5 in the width direction from one end of the second surface of the first insulating layer 5 to one end of the pad of the first circuit pattern 2 is at least 12.5 μm. In addition, the horizontal straight line distance (w7=(w4-w1)/2) in the width direction from one end of the first surface of the first via 6 to the one end of the pad of the first circuit pattern 2 is It is at least 11 μm.

Accordingly, in the comparative example, when the chip is mounted using the mounting pads 7-2a and 7-2b of the second circuit pattern 7 having the design and size as described above, the first pad 7- The pitch, which is the distance between the center of 2a) and the center of the second pad 7-2b, has a minimum of 78 μm or more. That is, the first pad 7-2a and the second pad 7-2b in the comparative example have a spacing of 8 μm or more. Accordingly, when only the design and size of the first pad 7-2a and the second pad 7-2b are considered, the center of the first pad 7-2a and the second pad 7-2b The pitch, which is the distance between the centers of , is about 78 μm.

However, with the recent high-spec electronic products, the number of terminals of the chip increases, and accordingly, the number of traces connecting the terminals of the chip and the terminals also increases. Accordingly, as shown in (a) of FIG. 1C, in the circuit board on which the chip is mounted, at least between the first pad 7-2a and the second pad 7-2b on which the chip is to be mounted. One trace should be placed. For example, when at least one trace is not disposed between the first pad 7-2a and the second pad 7-2b, the overall volume of the circuit board may increase. In addition, when at least one trace is not disposed between the first pad 7-2a and the second pad 7-2b, the length of the trace connecting the terminal and the terminal of the chip increases, There is a problem in that signal transmission loss increases as the length of the trace increases.

Accordingly, in the circuit board on which the chip can be mounted, at least one trace 7-2 should exist between the first pad 7-2a and the second pad 7-2b. The trace 7-2 may be a signal line connecting the first pad 7-2a and the second pad 7-2b. Alternatively, the first pad 7-2a and the second pad 7-2b It may be a signal line connecting any one of the two pads 7 - 2b or other pads except the same.

In this case, the trace 7-2 has a line width w8 of 7 μm or more, and a spacing w9 of at least 8 μm. The spacing w9 may mean a spacing between a plurality of traces, and a spacing between the trace 7-2 and the first pad 7-2a or the second pad 7-2b. It could mean an interval.

In addition, the width w10 of the opening of the first passivation layer 11 in the comparative example has a minimum width of 45 μm or more. In this case, the opening of the first passivation layer 11 is formed through an exposure and development process, and has a width of at least 45 μm depending on a process capability limit during the exposure and development.

In this case, as described above, the width w3 of the mounting pads 7-2a and 7-2b in the embodiment should be greater than the width w10 of the opening of the first protective layer 11 . This is because the entire surface of the mounting pads 7 - 2a and 7 - 2b must be exposed through the opening of the first protective layer 11 . In this case, there is a limit in forming the opening of the first protective layer 11 at an accurate position. Accordingly, in the comparative example, the mounting pads 7-2a and 7-2b have a width w3 of about 70 μm larger than the opening in consideration of the deviation of the position where the opening is formed.

Accordingly, as shown in (b) of FIG. 1C , in the circuit board of the comparative example, when the second circuit pattern 7 is used as a mounting pad, the first pad 7-2a and the second pad 7- The pitch, which is the distance between the centers of 2b), is the width of the first pad 7-2a, the width of the second pad 7-2b, the width of the trace 7-2, and the width of the trace 7-2. ) is determined by the spacing of the For example, as described above, in the comparative example, the width of the first pad 7-2a, the width of the second pad 7-2b, the width of the trace 7-2, and the width of the trace 7-2 ) is determined, so that the pitch p1 between the first pad 7-2a and the second pad 7-2b exceeds 110 μm. That is, in the comparative example, the widths of the first pad 7-2a and the second pad 7-2b are limited by the size of the via 6 and the size of the SOR of the first protective layer 11 . increases, and thus the pitch p1 between them exceeds 110 μm.

As described above, in the comparative example, the pitch between the centers of the first pad 7-2a and the second pad 7-2b exceeds at least 110 μm, and accordingly, it is difficult to mount a plurality of chips within a limited space. can be difficult For example, as the pitch increases, there is a problem in that the width in the width direction of the circuit board required to mount the chip increases. In addition, an increase in the pitch means an increase in signal transmission lines between adjacent pads, and there is a problem in that a signal transmission loss increases as the signal transmission lines increase.

In addition, as the performance of electric/electronic products is progressing recently, techniques for attaching a larger number of packages to a substrate having a limited size are being studied, and accordingly, miniaturization of circuit patterns is required. However, in the case of the package substrate using the circuit board of the comparative example, there is a limit to the miniaturization of the pad pitch. In addition, as functions processed by an application processor (AP) increase in recent years, it is becoming difficult to implement them in a single chip. However, it is difficult to mount two application processors (APs) having different functions in a limited space using the circuit board provided in the comparative example.

The embodiment is to solve the problems of the comparative example, and by removing the solder resist of the outermost side of the circuit board on which the mounting pad is disposed, the pitch of the mounting pad is 100 μm or less, preferably 90 μm or less, more preferably It should be reduced to less than 80㎛. Furthermore, in the embodiment, it is possible to mount a plurality of chips on one circuit board according to the reduction of the pitch. For example, in the embodiment, it is possible to provide a circuit board having a new structure on which a plurality of processor chips or memory chips having different functions can be mounted on a single circuit board, and a package board including the same.

-Electronic device-

Prior to the description of the embodiment, an electronic device including the package substrate of the embodiment will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and/or electrically connected to various components. For example, the main board may be connected to the package substrate of the embodiment. Various chips may be mounted on the package substrate. Broadly, the package substrate includes a volatile memory (eg, DRAM), a non-volatile memory (eg, ROM), a memory chip such as a flash memory, a central processor (eg, CPU), a graphics processor (eg, GPU), An application processor chip such as a digital signal processor, an encryption processor, a microprocessor, and a microcontroller, and a logic chip such as an analog-to-digital converter and an ASIC (application-specific IC) may be mounted.

In addition, the embodiment provides a circuit board and a package board capable of refining the pitch of the pads and capable of mounting at least two different types of chips on a single board according to the miniaturization of the pitch. Furthermore, the embodiment provides a circuit board and a package substrate in which more traces than in the comparative example can be disposed between mounting pads having a smaller pitch than in the comparative example.

In this case, the electronic device includes a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, and a computer. ), a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, and the like. However, the present invention is not limited thereto, and may be any other electronic device that processes data in addition to these.

-First embodiment-

Hereinafter, a circuit board according to an embodiment and a package board including the same will be described.

2 is a view showing a circuit board according to the first embodiment, FIG. 3A is an enlarged view of area T1 of FIG. 2 , FIG. 3B is an enlarged view of area B1 of FIG. 2 , and FIG. 4 is an enlarged view of area B1 of FIG. It is a diagram for explaining the pitch of the mounting pad according to the present invention. A circuit board according to the first embodiment will be described with reference to FIGS. 2 to 4 .

Referring to FIG. 2 , the circuit board 100 provides a mounting space in which at least one chip can be mounted. The number of chips mounted on the circuit board 100 may be one, alternatively, two, or alternatively, three or more. For example, one processor chip may be mounted on the circuit board 100 , and at least two processor chips having different functions may be mounted differently. Alternatively, one processor chip and one memory chip may be mounted on the circuit board 100 . This may be mounted, otherwise, at least two processor chips and at least one memory chip having different functions may be mounted.

The circuit board 100 includes an insulating layer 110 .

In this case, the circuit board 100 of the embodiment may be a core board. For example, the circuit board 100 may include a core layer 111 . For example, the circuit board 100 may have a structure in which a plurality of insulating layers are stacked symmetrically on top and bottom of the core layer 111 . At this time, in the embodiment, it has been described that the circuit board 100 is a core substrate, but is not limited thereto. For example, in another embodiment, the circuit board may be a core rig board from which the core layer is removed. At this time, in the embodiment, the mounting pad for mounting the chip has its characteristics. Accordingly, in the embodiment, it is not very important whether the circuit board 100 includes the core layer, and in the multilayer structure of the circuit board, the outermost insulating layer, the via, and the circuit pattern are characterized. . In addition, features of the outermost insulating layer, via, and circuit pattern described below may be equally applied to not only the core substrate but also the coreless substrate. However, in the embodiment, in order to maximize the bending characteristics of the circuit board, the circuit board 100 will be described as a core board including a core layer.

Accordingly, the insulating layer 110 of the circuit board 100 may include a core layer 111 , a first insulating layer 112 , and a second insulating layer 113 .

The core layer 111 is CCL (clad copper laminate) including a prepreg, or includes a material such as silicon, glass, and ceramic used in an interposer.

The first insulating layer 112 may be stacked on the first surface of the core layer 111 . For example, the first insulating layer 112 may be stacked on the upper surface of the core layer 111 . At this time, although it has been described that the first insulating layer 112 is composed of one layer in FIG. 2 , the present invention is not limited thereto. For example, the first insulating layer 112 may have a multilayer structure of two or more layers. And, when the first insulating layer 112 has a multilayer structure, the second insulating layer 113 may also have a multilayer structure corresponding thereto. In addition, when at least two or more first insulating layers are stacked on the first surface or upper surface of the core layer 111 in the circuit board 100 , the first insulating layer 112 shown in FIG. 2 includes the two Among the above first insulating layers, the first insulating layer disposed on the first outermost (or uppermost) side may be shown. In this case, the first outermost side may correspond to a chip mounting area in which a chip is mounted.

In addition, the second insulating layer 113 may be stacked on the second surface of the core layer 111 . For example, the second insulating layer 113 may be stacked on a lower surface of the core layer 111 . At this time, although it has been described that the second insulating layer 113 is composed of one layer in FIG. 2 , the present invention is not limited thereto. For example, the second insulating layer 113 may have a multilayer structure of two or more layers. In addition, when the second insulating layer 113 has a multilayer structure, the first insulating layer 112 may have a multilayer structure with the same number of layers corresponding thereto. In addition, when at least two or more second insulating layers are stacked on the second surface or lower surface of the core layer 111 in the circuit board 100 of the embodiment, the second insulating layer 113 shown in FIG. 2 is The second insulating layer disposed on the second outermost (or lowermost) side of the two or more second insulating layers may be shown.

The first insulating layer 112 and the second insulating layer 113 may include a prepreg (PPG). The prepreg may be formed by impregnating a fiber layer in the form of a fabric sheet, such as a glass fabric woven with glass yarn, with an epoxy resin, and then performing thermocompression. However, the embodiment is not limited thereto, and the prepreg constituting the first insulating layer 112 and the second insulating layer 113 may include a fiber layer in the form of a fabric sheet woven with carbon fiber threads.

The first insulating layer 112 and the second insulating layer 113 may include a resin and a reinforcing fiber disposed in the resin. The resin may be an epoxy resin, but is not limited thereto. The resin is not particularly limited to the epoxy resin, for example, one or more epoxy groups may be included in the molecule, and alternatively, two or more epoxy groups may be included. Alternatively, four or more epoxy groups may be included. In addition, the resin of the first insulating layer 112 and the second insulating layer 113 may include a naphthalene group, for example, may be an aromatic amine type, but is not limited thereto. For example, the resin is a bisphenol A type epoxy resin, a bisphenol F type epoxy resin, a bisphenol S type epoxy resin, a phenol novolak type epoxy resin, an alkylphenol novolak type epoxy resin, a biphenyl type epoxy resin, an aralkyl type epoxy resin Resin, dicyclopentadiene type epoxy resin, naphthalene type epoxy resin, naphthol type epoxy resin, epoxy resin of condensate of phenol and aromatic aldehyde having phenolic hydroxyl group, biphenyl aralkyl type epoxy resin, fluorene type epoxy resin resins, xanthene-type epoxy resins, triglycidyl isocyanurate, rubber-modified epoxy resins, phosphorous-based epoxy resins, and the like, and naphthalene-based epoxy resins, bisphenol A-type epoxy resins, and phenol novolac epoxy resins , cresol novolac epoxy resins, rubber-modified epoxy resins, and phosphorous-based epoxy resins. In addition, the reinforcing fiber is glass fiber, carbon fiber, aramid fiber (eg, aramid-based organic material), nylon (nylon), silica (silica)-based inorganic material or titania-based inorganic material is used. can The reinforcing fibers may be arranged in the resin to cross each other in a planar direction.

Meanwhile, the glass fiber, carbon fiber, aramid fiber (eg, aramid-based organic material), nylon, silica-based inorganic material or titania-based inorganic material may be used.

The first insulating layer 112 and the second insulating layer 113 may have a thickness (T1 in FIG. 3A and T3 in FIG. 3B ) in the range of 10 μm to 60 μm. For example, the first insulating layer 112 and the second insulating layer 113 may have thicknesses T1 and T3 in the range of 15 μm to 55 μm. For example, the first insulating layer 112 and the second insulating layer 113 may have thicknesses T1 and T3 in the range of 20 μm to 50 μm. The thicknesses T1 and T3 of the first insulating layer 112 and the second insulating layer 113 may mean a distance between circuit patterns respectively disposed on the surface thereof. For example, the thickness T1 of the first insulating layer 112 may be between the second surface or the lower surface of the first circuit pattern 140 and the first surface or the upper surface of the second circuit pattern 120 to be described below. can mean the distance of Also, the thickness T2 of the second insulating layer 113 may mean a distance between the lower surface of the third circuit pattern 125 and the upper surface of the fourth circuit pattern 160 , which will be described below.

Circuit patterns may be respectively disposed on the surface of the insulating layer 110 of the embodiment. For example, the first circuit pattern 140 may be disposed on the first surface or the upper surface of the first insulating layer 112 . For example, the second circuit pattern 120 may be disposed on the second surface or the lower surface of the first insulating layer 112 . For example, the third circuit pattern 125 may be disposed on the first surface or the upper surface of the second insulating layer 113 . For example, the fourth circuit pattern 160 may be disposed on the second surface or the lower surface of the second insulating layer 113 .

The first circuit pattern 140 , the second circuit pattern 120 , the third circuit pattern 125 , and the fourth circuit pattern 160 are a conventional printed circuit board manufacturing process using an additive process, Subtractive process (Subtractive Process), MSAP (Modified Semi Additive Process), SAP (Semi Additive Process), etc. are possible, and a detailed description will be omitted here.

Each of the first circuit pattern 140 , the second circuit pattern 120 , the third circuit pattern 125 , and the fourth circuit pattern 160 is a surface of each insulating layer with the core layer 111 as the center. It may be formed to protrude upward.

The first circuit pattern 140 is disposed on the first surface of the first insulating layer 112 . For example, the first surface of the first insulating layer 112 may be a top surface of the first insulating layer 112 . For example, the first circuit pattern 140 may have a structure protruding above the first surface or the top surface of the first insulating layer 112 .

The first circuit pattern 140 may include a trace 141 and a pad 142 . The pads 142 of the first circuit pattern 140 may be disposed on the circuit board 100 in a chip mounting region (not shown) in which a chip is to be mounted. For example, the pad 142 of the first circuit pattern 140 may mean a chip mounting pad.

The traces 141 of the first circuit pattern 140 may be disposed on a first surface or an upper surface of the first insulating layer 112 . For example, the lower surface of the trace 141 of the first circuit pattern 140 may directly contact the upper surface of the first insulating layer 112 . For example, the first circuit pattern 140 may include a seed layer (not shown) and an electrolytic plating layer on the seed layer, and a lower surface of the seed layer of the first circuit pattern 140 is the first insulating layer. It may be in direct contact with the top surface of layer 112 . However, the embodiment is not limited thereto. For example, the first insulating layer 112 may include a primer layer (not shown) for improving adhesion to the traces 141 of the first circuit pattern 140 , and in this case, the first The lower surface of the circuit pattern 140 may directly contact the upper surface of the primer layer.

The pad 142 of the first circuit pattern 140 is disposed on the first surface or the top surface of the first via 150 penetrating the first insulating layer 112 . For example, the pad 142 of the first circuit pattern 140 may be disposed on the first surface of the first via 150 and may be electrically connected to the trace 141 . In this case, the traces 141 and the pads 142 of the first circuit pattern 140 are only for functional distinction, and in reality, they may be a single pattern integrally formed with each other.

A lower surface of the trace 141 of the first circuit pattern 140 may be positioned on the same plane as a lower surface of the pad 142 of the first circuit pattern 140 . For example, an upper surface of the trace 141 of the first circuit pattern 140 may be positioned on the same plane as an upper surface of the pad 142 of the first circuit pattern 140 . In this case, at least a portion of the trace 141 of the first circuit pattern 140 is disposed on the upper surface of the first insulating layer 112 . Also, at least a portion of the pad 142 of the first circuit pattern 140 may be disposed on the upper surface of the first insulating layer 112 .

The first circuit pattern 140 is at least one selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). It may be formed of a metal material of In addition, the first circuit pattern 140 is selected from among gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding strength. It may be formed of a paste or solder paste including at least one metal material. Preferably, the first circuit pattern 140 may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

The first circuit pattern 140 may have a thickness in a range of 5 μm to 20 μm. For example, the first circuit pattern 140 may have a thickness in a range of 6 μm to 17 μm. The first circuit pattern 140 may have a thickness in a range of 7 μm to 13 μm. When the thickness of the first circuit pattern 140 is less than 5 μm, the resistance of the first circuit pattern 140 may increase. When the thickness of the first circuit pattern 140 exceeds 20 μm, the line width of the trace 141 constituting the first circuit pattern 140 increases, and thus the overall volume of the circuit board 100 decreases. can increase

The trace 141 of the first circuit pattern 140 may have a specific line width W5 and a specific interval W6 . For example, the line width W5 of the trace 141 of the first circuit pattern 140 may be in a range of 6 μm to 20 μm. For example, the line width W5 of the trace 141 of the first circuit pattern 140 may be in a range of 7 μm to 15 μm. For example, the line width W5 of the trace 141 of the first circuit pattern 140 may be in a range of 8 μm to 12 μm. Also, the interval W6 between the traces of the first circuit pattern 140 may be in a range of 6 μm to 20 μm. For example, the interval W6 between the traces of the first circuit pattern 140 may be in a range of 7 μm to 15 μm. For example, the interval W6 between the traces of the first circuit pattern 140 may be in a range of 8 μm to 12 μm. Here, the spacing W6 may mean a spacing between a plurality of traces constituting the first circuit pattern 140 . In addition, the gap W6 may mean a gap between the trace 141 constituting the first circuit pattern 140 and the pad 142 .

In an embodiment, at least one trace 141 of the first circuit pattern 140 may be positioned between the plurality of pads 142 of the first circuit pattern 140 , which are used as mounting pads. For example, the pad 142 of the first circuit pattern 140 may include a first pad 142-1 and a second pad 142-2 spaced apart from each other in the width direction. In addition, on the upper surface of the first insulating layer 112 , the first circuit pattern 140 is disposed between the first pad 142-1 and the second pad 142-2 of the first circuit pattern 140 . ) of at least one trace 141 may be disposed. The trace 141 disposed between the pads is directly connected to at least one of the first pad 142-1 and the second pad 142-2, or the other of the first insulating layer 112 except for this. It can be directly connected to the pad.

That is, in the embodiment, the first pad 142-1 and the second pad 142-2 are mounting pads on which chips are mounted. In this case, the mounting pads may be electrically connected to each other. For example, as shown in FIG. 1B , at least one trace may be disposed between neighboring pads. And, in the embodiment, while being disposed on at least one trace 141 between the first pad 142-1 and the second pad 142-2, the first pad 142-1 and the second pad 142 -2) so that the pitch between the centers is 100 μm or less.

Meanwhile, in general, the width of the mounting pad is determined by the width of the via and the size of the open area of the solder resist, and the pitch between the plurality of mounting pads is determined by the width of the mounting pad. In addition, at least one trace should be disposed between the mounting pads. Accordingly, in the comparative example, the pitch of the mounting pads exceeds 110 μm due to the width of the mounting pad and the width of the trace. Alternatively, in the embodiment, the solder resist is removed, and accordingly, the width of the mounting pad can be formed without considering the size of the open area of the solder resist. Accordingly, in the embodiment, the width of the mounting pad may be reduced compared to that of the comparative example. Also, in an embodiment, the spacing between the vias may be reduced as much as the width of the mounting pad is reduced. That is, the pitch of the mounting pad in the embodiment only needs to consider the width of the via and the distance therebetween, and accordingly, the pitch of the mounting pad may be reduced compared to the comparative example.

Specifically, in the first embodiment, the width W3 of the pad 142 of the first circuit pattern 140 may be greater than the width W1 of the first surface or the top surface of the first via 150 . .

For example, the width W3 of the pad 142 may be 26 μm to 65 μm. For example, the width W3 of the pad 142 may be 30 μm to 60 μm. The width W3 of the pad 142 may be 35 μm to 50 μm. When the width W3 of the pad 142 is greater than 65 μm, a pitch between the plurality of pads may increase according to an increase in the width of the pad 142 .

In the first embodiment, the width W3 of the pad 142 may be similar to the width W1 of the first surface or the top surface of the first via 150 . For example, in the first embodiment, the width W3 of the pad 142 may have a value between 101% and 130% of the width W1 of the first surface or the top surface of the first via 150 . have. For example, in the first embodiment, the width W3 of the pad 142 may have a value between 102% and 125% of the width W1 of the first surface or the top surface of the first via 150 . have. For example, in the first embodiment, the width W3 of the pad 142 may have a value between 105% and 120% of the width W1 of the first surface or the top surface of the first via 150 . have. That is, in the comparative example, the width of the pad was determined by the width of the first surface of the first via and the width of the opening of the first passivation layer. In contrast, in the circuit board according to the embodiment, the solder resist, which is a protective layer disposed on the first outermost side of the circuit board, is removed. Accordingly, in the embodiment, in determining the width W3 of the pad 142 , it is not necessary to consider the size of the open area SOR of the solder resist. Accordingly, in the embodiment, the width W3 of the pad 142 may be reduced compared to the comparative example, and further, the pitch between neighboring pads may be reduced to 100 μm or less.

Also, in an embodiment, the width W3 of the pad 142 of the first circuit pattern 140 may be smaller than the width W4 of the pad 142 of the second circuit pattern 120 . That is, in the comparative example, the width of the pad of the first circuit pattern is greater than the width of the pad of the second circuit pattern because the size of the open area of the solder resist should be considered. Unlike this, since the size of the open region of the solder resist does not need to be considered in the first embodiment, the width W3 of the pad 142 of the first circuit pattern 140 is equal to that of the second circuit pattern 120 . It may be formed to be smaller than the width W4 of the pads 121 and 122 .

The second circuit pattern 120 may be disposed on the second surface or the lower surface of the first insulating layer 112 . For example, the second circuit pattern 120 may be disposed on the surface of the first insulating layer 112 , opposite to the surface on which the first circuit pattern 140 is disposed. The second circuit pattern 140 may be buried in the second surface or the lower surface of the first insulating layer 112 . For example, an upper surface and a side surface of the second circuit pattern 120 may be covered by the first insulating layer 112 . Specifically, the second circuit pattern 120 may be disposed to protrude from the upper surface of the insulating layer disposed under the first insulating layer 112 . For example, as shown in FIG. 2 , when the core layer 111 is disposed under the first insulating layer 112 , the second circuit pattern 120 is formed on the upper surface of the core layer 111 or the first It may be disposed to protrude from the surface. However, as described above, the first insulating layer 112 may be disposed on the core layer 111 to have a plurality of layer structures. In this case, the second circuit pattern 120 may be disposed on the upper surface of the insulating layer disposed under the outermost first insulating layer.

The second circuit pattern 120 may be connected to the first via 150 . Specifically, the second circuit pattern 120 may include pads 121 and 122 and traces. Also, the pads 121 and 122 of the second circuit pattern 120 may be connected to the first via 150 . In addition, the second circuit pattern 120 may include traces (not shown) connected to the pads 121 and 122 .

The pads 121 and 122 of the second circuit pattern 120 may be connected to a second surface or a lower surface of the first via 150 . Specifically, the first surface or upper surface of the pads 121 and 122 of the second circuit pattern 120 may directly contact the second surface or the lower surface of the first via 150 . The traces of the second circuit pattern 120 may not be disposed between the pads 121 and 122 of the second circuit pattern 120 . That is, in the embodiment, although the second circuit pattern 120 includes the pads 121 and 122 and the trace, the trace of the second circuit pattern 120 is the second circuit pattern of the first insulating layer 112 . On two or lower surfaces, the pad 121 and 122 may be disposed avoiding the area between the pads. Accordingly, in the embodiment, the gap between the pads 121 and 122 of the second circuit pattern 120 can be minimized, and further, the gap between the plurality of first vias can be minimized, and furthermore, the first The pitch between the plurality of pads 142 of the circuit pattern 140 may be minimized. For example, due to the structural features as described above, in the embodiment, the pitch between the pads 142 of the first circuit pattern 140 may be 100 μm or less, further 90 μm or less, and further 80 μm or less. .

The interval W7 between the pads 121 and 122 of the second circuit pattern 120 may be 30 μm or less. For example, the gap W7 between the pads 121 and 122 of the second circuit pattern 120 may be 20 μm or less. For example, the gap W7 between the pads 121 and 122 of the second circuit pattern 120 may be 10 μm or less. For example, the gap W7 between the pads 121 and 122 of the second circuit pattern 120 may be 7 μm or less. For example, the gap W7 between the pads 121 and 122 of the second circuit pattern 120 may be 5 μm or less. For example, the gap W7 between the pads 121 and 122 of the second circuit pattern 120 may be 2 μm or more.

Specifically, the interval W7 between the pads 121 and 122 of the second circuit pattern 120 may be in a range of 2 μm to 30 μm. For example, the distance W7 between the pads 121 and 122 of the second circuit pattern 120 may be in a range of 2.5 μm to 20 μm. For example, the interval W7 between the pads 121 and 122 of the second circuit pattern 120 may be in a range of 2.5 μm to 7 μm. Preferably, the interval W7 between the pads 121 and 122 of the second circuit pattern 120 is the line width of the trace 141 of the first circuit pattern 140 or the trace of the second circuit pattern 120 or may be smaller than the interval.

If the interval W7 between the pads 121 and 122 of the second circuit pattern 120 is less than 2 μm, a reliability problem in which the pads 121 and 122 are connected to each other may occur. If the interval W7 between the pads 121 and 132 of the second circuit pattern 120 is less than 2 μm, a problem in communication performance may occur due to signal interference between the pads 121 and 122 . When the interval W7 of the second circuit pattern 120 is greater than 30 μm, the pads 121 and 122 of the second circuit pattern 120 are formed between the pads 142 of the first circuit pattern 140 . It may be difficult to set the pitch of 100 μm or less. That is, when the interval W7 between the second circuit patterns 120 is greater than 30 μm, the overall volume of the circuit board 100 may increase according to the increase in the pitch.

The pads 121 and 122 of the second circuit pattern 120 may overlap the traces 141 of the first circuit pattern 140 in a thickness direction (or a vertical direction or a z-axis direction in a three-dimensional coordinate system). .

That is, the second circuit pattern 120 includes the first pad 121 and the second pad 122 spaced apart in the width direction (or the x-axis, the y-axis, and a diagonal direction therebetween in a horizontal direction or a three-dimensional coordinate system). ) is included.

And, in an embodiment, the trace of the second circuit pattern 120 is not disposed between the first pad 121 and the second pad 122 of the second circuit pattern 120 . And, in an embodiment, the gap between the first pad 121 and the second pad 122 of the second circuit pattern 120 is minimized, thereby providing a space between the plurality of first vias spaced apart in the width direction. The pitch is set to be 100 μm or less, and correspondingly, the pitch of the pads 142 of the first circuit pattern 140 is set to be 100 μm or less.

At this time, as described above, the interval between the first pad 121 and the second pad 122 of the second circuit pattern 120 is smaller than the line width or interval of the trace 141 of the first circuit pattern 140 . Accordingly, at least a portion of the trace 141 of the first circuit pattern 140 may overlap the first pad 121 or the second pad 122 of the second circuit pattern 120 in the thickness direction. have. For example, at least a portion of the trace 141 of the first circuit pattern 140 may overlap the first pad 121 of the second circuit pattern 120 in the thickness direction. For example, at least a portion of the trace 141 of the first circuit pattern 140 may overlap the second pad 142 of the second circuit pattern 120 in the thickness direction. For example, at least a portion of the trace 141 of the first circuit pattern 140 overlaps the first pad 121 of the second circuit pattern 120 in the thickness direction, and another portion of the trace 141 of the second circuit pattern 120 overlaps with the second circuit. The second pad 122 of the pattern 120 may overlap in the thickness direction.

The width W4 of the first pad 121 and the second pad 122 of the second circuit pattern 120 may correspond to each other. For example, the width W4 of the first pad 121 and the second pad 122 of the second circuit pattern 120 may be 30 μm to 70 μm. For example, the width W4 of the first pad 121 and the second pad 122 of the second circuit pattern 120 may be 32 μm to 65 μm. For example, the width W4 of the first pad 121 and the second pad 122 of the second circuit pattern 120 may be 35 μm to 60 μm.

The circuit board 100 in the embodiment includes a first via 150 passing through the first insulating layer 112 . A first surface or an upper surface of the first via 150 may contact the first circuit pattern 140 . For example, a first surface or an upper surface of the first via 150 may contact a lower surface of the pad 142 of the first circuit pattern 140 . Also, a second surface or a lower surface of the first via 150 may contact the second circuit pattern 120 . For example, the second surface or lower surface of the first via 150 may contact the pads 121 and 122 of the second circuit pattern 120 .

The first via 150 may be formed by forming a via hole (not shown) penetrating the first insulating layer 112 and filling the formed via hole with a conductive material.

The via hole may be formed by any one of mechanical, laser, and chemical processing. When the via hole is formed by machining, methods such as milling, drilling, and routing can be used, and when formed by laser processing, UV or CO ₂ laser method is used. In the case of being formed by chemical processing, at least one insulating layer among the plurality of insulating layers may be opened by using a chemical containing aminosilane, ketones, or the like.

On the other hand, the processing by the laser is a cutting method that melts and evaporates a part of the material by concentrating optical energy on the surface to take a desired shape, and complex formation by a computer program can be easily processed. Even difficult composite materials can be machined.

In addition, the processing by the laser can have a cutting diameter of at least 0.005 mm, and has a wide advantage in a range of possible thicknesses.

As the laser processing drill, it is preferable to use a YAG (Yttrium Aluminum Garnet) laser, a CO ₂ laser, or an ultraviolet (UV) laser. The YAG laser is a laser that can process both the copper foil layer and the insulating layer, and the CO ₂ laser is a laser that can process only the insulating layer.

When the via hole is formed, the first via 150 may be formed by filling an inside of the via hole with a conductive material. The metal material forming the first via 150 may be one selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). For the conductive material filling, any one or a combination of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjetting and dispensing may be used. have.

The thickness of the first via 150 may be the same as the thickness of the first insulating layer 112 . For example, T1 in FIG. 2 may mean the thickness of the first via 150 , or alternatively, the thickness of the first insulating layer 112 .

The first via 150 may include a first surface and a second surface. For example, a first surface of the first via 150 may be an upper surface, and a second surface of the first via 150 may be a lower surface.

The width W1 of the first surface or the upper surface of the first via 150 may be greater than the width W2 of the second surface or the lower surface of the first via 150 . For example, the first via 150 may have a trapezoidal shape in which the width of the first surface and the second surface are different from each other. In addition, in the embodiment, the first via 150 may be connected to the pad 142 of the first circuit pattern 140 having a relatively large first surface or upper surface disposed on the first outermost side of the circuit board. have.

Specifically, the first via 150 may include a 1-1 via 151 and a 1-2 via 152 that are spaced apart from each other in the width direction.

In addition, the width W1 of the first surface of the 1-1 via 151 and the 1-2 via 152 may be 25 μm to 55 μm. For example, the width W1 of the first surface of the 1-1 via 151 and the 1-2 via 152 may be 27 μm to 50 μm. For example, the width W1 of the first surfaces of the 1-1 via 151 and the 1-2 via 152 may be 30 μm to 47 μm. For example, when the width W1 of the first surface of the 1-1 via 151 and the 1-2 via 152 is less than 25 μm, the first insulation including the prepreg is performed by a laser process. It may be difficult to easily form a via hole through the layer 112 . Specifically, it may be difficult to form a via hole having a size smaller than 25 μm in the first insulating layer 112 due to a limitation of the laser process. For example, when the width W1 of the first surfaces of the 1-1 via 151 and the 1-2 via 152 is greater than 50 μm, the 1-1 via 151 and the 1-th via 151 are The pitch between the two vias 152 may increase, and accordingly, the volume of a circuit board for mounting a chip may increase. For example, if the width W1 of the first surface of the 1-1 via 151 and the 1-2 via 152 is greater than 50 μm, the pad 142 of the first circuit pattern 140 . As the pitch between them increases, the signal transmission loss may increase as the signal transmission distance of the chip disposed on the pad 142 increases.

A width W2 of the second surface of the 1-1 via 151 and the 1-2 via 152 may be 20 μm to 40 μm. For example, the width W2 of the second surface of the 1-1 via 151 and the 1-2 via 152 may be 22 μm to 37 μm. For example, the width W2 of the second surface of the 1-1 via 151 and the 1-2 via 152 may be 25 μm to 35 μm.

In other words, the first outermost structure of the circuit board of the first embodiment will be described as follows. A first insulating layer 112 is disposed on the first outermost side of the circuit board. A first circuit pattern 140 is disposed on an upper surface of the first insulating layer 112 , and a second circuit pattern 120 is disposed on a lower surface of the first insulating layer 112 . In addition, a first via 150 connected to the first circuit pattern 140 and the second circuit pattern 120 is included in the first insulating layer 112 .

In this case, the first circuit pattern 140 includes a pad 142 connected to the first via 150 and a trace 141 connected to the pad 142 . And, in the first embodiment, the width W3 of the pad 142 of the first circuit pattern 140 is similar to the width W1 of the first surface of the first via 150 . That is, in the embodiment, the width W3 of the pad 142 may be determined without considering the size of the open area of the solder resist, and the width W3 of the pad 142 is equal to the width W3 of the first via 150 . ) to be as similar as possible to the width W1 of the first surface. Accordingly, in the embodiment, as the width of the pad 142 may be reduced, the pitch between the plurality of pads of the first circuit pattern 140 may be reduced.

Meanwhile, the circuit board 100 includes a third circuit pattern 125 disposed on the first or upper surface of the second insulating layer 113 , and the second or lower surface of the second insulating layer 113 . A fourth circuit pattern 160 is included. In addition, the circuit pattern 140 passes through the second insulating layer 113 and includes a second via 170 connecting the third circuit pattern 125 and the fourth circuit pattern 160 .

The second via 170 may have a trapezoidal shape in which the width W11 of the first surface or the upper surface is smaller than the width W12 of the second surface or the lower surface. For example, the second via 170 may have a symmetrical shape with the first via 150 .

The width W11 of the first surface or the upper surface of the second via 170 may correspond to the width W2 of the second surface or the lower surface of the first via 150 . The width W11 of the first surface or the upper surface of the second via 170 may be 20 μm to 40 μm. For example, the width W11 of the first surface or the upper surface of the second via 170 may be 22 μm to 37 μm. For example, the width W11 of the first surface or the upper surface of the second via 170 may be 25 μm to 35 μm.

The width W12 of the second surface or the lower surface of the second via 170 may correspond to the width W1 of the first surface or the upper surface of the first via 150 . The width W12 of the second surface or the lower surface of the second via 170 may be 25 μm to 55 μm. For example, the width W12 of the second surface or the lower surface of the second via 170 may be 27 μm to 50 μm. For example, the width W12 of the second surface or the lower surface of the second via 170 may be 30 μm to 47 μm.

The third circuit pattern 125 includes a pad connected to the second via 170 . The width W13 of the pad of the third circuit pattern 125 may correspond to the width W4 of the pads 121 and 122 of the second circuit pattern 120 . For example, the width W13 of the pad of the third circuit pattern 125 may be 20 μm to 50 μm. For example, the width W13 of the pad of the third circuit pattern 125 may be 22 μm to 47 μm. For example, the width W13 of the pad of the third circuit pattern 125 may be 25 μm to 40 μm.

The fourth circuit pattern 160 includes a pad connected to the second via 170 . In this case, the pad of the fourth circuit pattern 160 may be a terminal pad. For example, the pad of the fourth circuit pattern 160 may function as a terminal connected to the main board of the electronic device. For example, the pad of the fourth circuit pattern 160 may be a pad on which solder balls are disposed to be connected to the main board of the electronic device.

In this case, the pitch of the pads of the fourth circuit pattern 160 may have a pitch corresponding to the pads of the main board. In this case, the pitch of the pads of the main board relatively exceeds 100 μm, and accordingly, the pitch of the pads of the fourth circuit pattern 160 is greater than the pitch of the pads 142 of the first circuit pattern 140 . free of charge Accordingly, the width W14 of the pad of the fourth circuit pattern 160 is the width W3 of the pad 142 of the first circuit pattern 140 and the second surface of the second via 170 or It may be larger than the width W12 of the lower surface.

For example, the width W14 of the pad of the fourth circuit pattern 160 may be 30 μm to 80 μm. For example, the width W14 of the pad of the fourth circuit pattern 160 may be 35 μm to 70 μm. For example, the width W14 of the pad of the fourth circuit pattern 160 may be 40 μm to 60 μm.

Meanwhile, in an embodiment, the spacing W16 between the pads of the fourth circuit pattern 160 may be greater than the spacing W7 between the pads 121 and 122 of the second circuit pattern 120 . .

Accordingly, in the embodiment, the pitch that is the distance between the centers of the pads of the fourth circuit pattern 160 may be greater than the pitch that is the distance between the centers of the pads 142 of the first circuit pattern 140 . .

The circuit board 100 of the embodiment includes a protective layer 185 . The protective layer 185 is disposed on the second surface or the lower surface of the second insulating layer 113 .

In this case, in the circuit board 100 of the embodiment, the first and second outermost layer structures may be different from each other. For example, the first insulating layer 112 is disposed on the first outermost side of the circuit board 100 in the embodiment, and the second insulating layer 113 is disposed on the second outermost side. At this time, in the embodiment, a solder resist, which is a protective layer, is not disposed on the first surface of the first insulating layer 112 disposed on the first outermost side. Accordingly, in an embodiment, the first outermost surface of the circuit board may be configured as the first surface or the upper surface of the first insulating layer 112 . Alternatively, in the embodiment, the protective layer 185 is disposed on the second surface of the second insulating layer 113 disposed on the second outermost side. Accordingly, in the embodiment, the second outermost surface of the circuit board may be configured as the second surface or the lower surface of the protective layer 185 .

The protective layer 185 may include at least one opening (not shown).

The width W15 of the opening of the passivation layer 185 may be smaller than the width W14 of the pad of the fourth circuit pattern 160 . Accordingly, the second passivation layer 185 may cover at least a portion of the pad of the fourth circuit pattern 160 . For example, the second passivation layer 185 exposes the center of the lower surface of the pad of the fourth circuit pattern 160 through the opening, and covers the edge area of the lower surface of the pad of the fourth circuit pattern 160 . It can be covered and placed.

Meanwhile, the protective layer 185 may have a predetermined thickness T4. Preferably, the thickness T4 of the second passivation layer 185 may mean a thickness from the lower surface of the pad of the fourth circuit pattern 160 to the lower surface of the second passivation layer 185 . A thickness T4 of the passivation layer 185 may be in a range of 2 μm to 20 μm. A thickness T4 of the passivation layer 185 may be in a range of 4 μm to 15 μm. A thickness T4 of the passivation layer 185 may be in a range of 7 μm to 12 μm.

In an embodiment, the circuit board 100 includes a surface treatment layer. The surface treatment layer may be formed to increase solderability while preventing corrosion and oxidation of the pad. In this case, the surface treatment layer may be disposed on the surface of the pad disposed on the outermost side of the circuit board.

For example, the circuit board 100 may include the first surface treatment layer 190 disposed on the pad 142 of the first circuit pattern 140 .

The first surface treatment layer 190 may be an Organic Solderability Preservative (OSP) layer. Preferably, the first surface treatment layer 190 may be an organic layer formed of an organic material such as benzimidazole coated on the pad 142 of the first circuit pattern 140 .

Alternatively, the first surface treatment layer 190 may be a plating layer. For example, the first surface treatment layer 190 may include a gold (Au) plating layer electrolessly plated on the first surface of the pad 142 of the first circuit pattern 140 . For example, the first surface treatment layer 190 may include a nickel (Ni) plating layer electrolessly plated on the first surface of the pad 142 of the first circuit pattern 140 and an electroless plating layer on the nickel plating layer. and a gold (Au) plating layer. For example, the first surface treatment layer 190 may include a nickel (Ni) plating layer electrolessly plated on the first surface of the pad 142 of the first circuit pattern 140 and an electroless plating layer on the nickel plating layer. The palladium (Pd) plating layer may include a gold (Au) plating layer electrolessly plated on the palladium plating layer.

In an embodiment, the first surface treatment layer 190 may have a width corresponding to the width W3 of the pad 142 of the first circuit pattern 140 .

Correspondingly, the second surface treatment layer 195 is disposed on the second surface or the lower surface of the pad of the fourth circuit pattern 160 . The second surface treatment layer 195 may be an Organic Solderability Preservative (OSP) layer. Preferably, the second surface treatment layer 195 may be an organic layer corresponding to the first surface treatment layer 190 , and alternatively a nickel (Ni) plating layer, a palladium (Pd) plating layer, and a gold (Au) plating layer. It may be a gold plating layer including at least one of the plating layers.

A width of the second surface treatment layer 195 may correspond to a width W15 of the opening of the passivation layer 185 .

Referring to FIG. 4 , the embodiment includes a 1-1 via 151 and a 1-2 via 152 that are spaced apart from each other in the width direction. In addition, on the 1-1 via 151 and the 1-2 via 152 , the first pad 142-1 and the second pad 142- of the first circuit pattern 140 having a greater width 2) are placed respectively. Also, a trace 141 of at least one first circuit pattern 140 may be disposed across the first pad 142-1 and the second pad 142-2. In this case, in the embodiment, as described above, the pad 142 of the first circuit pattern 140 has a width greater than the width of the first surface of the first via 150 . Also, in an embodiment, a protective layer, which is a solder resist, is not disposed on the first insulating layer 112 on which the pads 142 of the first circuit pattern 140 are disposed. Accordingly, in the embodiment, the pad 142 of the first circuit pattern 140 can be formed without considering the size of the open region of the solder resist, so that the width of the pad 142 can be reduced. have.

Accordingly, in the embodiment, the gap between the 1-1 via 151 and the 1-2 via 152 may be minimized. Accordingly, in the embodiment, the pitch P1 corresponding to the distance between the centers of the first pad 142-1 and the second pad 142-2 may be 100 μm or less. Furthermore, in the embodiment, the pitch P1 corresponding to the distance between the centers of the first pad 142-1 and the second pad 142-2 may be set to 90 μm or less. Furthermore, in the embodiment, the pitch P1 corresponding to the distance between the centers of the first pad 142-1 and the second pad 142-2 may be 80 μm or less.

For example, in the embodiment, even if one trace 141 and further at least two or more traces are disposed between the first pad 142-1 and the second pad 142-2, the pitch ( P1) can be reduced.

That is, in the embodiment, the width of the pad 142 of the first circuit pattern 140 , which is a mounting pad disposed on the first via 150 , is similar to the width of the first surface of the first via 150 . Accordingly, in the embodiment, the spacing between the plurality of first vias is minimized. At this time, even in the comparative example as in FIG. 1B , as the spacing between the mounting pads 7-2a and 7-2b of the second circuit pattern 7 is minimized, the mounting pads 7-2a and 7-2b Although it seems that the pitch can be reduced, it is practically difficult to reduce the pitch of the mounting pad to 100 μm or less in the comparative example. This allows the mounting pads 7-2a and 7-2b to have a width in consideration of the size of the open area of the solder resist, and at least one trace 7 between the mounting pads 7-2a and 7-2b. -1) should be placed. Accordingly, in the comparative example, the distance between the mounting pads 7-2a and 7-2b is determined by the width of the mounting pads composed of the second circuit pattern 7 and the line width and spacing of the traces disposed therebetween. The gap cannot be reduced to less than 30 μm. That is, in the comparative example, the distance between the mounting pads 7-2a and 7-2b could not be reduced to 30 μm or less, and accordingly, the pitch between the mounting pads 7-2a and 7-2b exceeded 100 μm. did.

On the other hand, in the embodiment, the width of the pad of the first circuit pattern 140 may be reduced compared to the comparative example, and thereby, in the embodiment, the gap between the pads 121 and 122 of the second circuit pattern 120 Even if is reduced to 30 μm or less (and further reduced to 2 μm), a space for arranging at least one trace 141 is sufficiently provided in the space between the pads 142 of the first circuit pattern 140 . Accordingly, in the embodiment, the distance between the pads 121 and 122 of the second circuit pattern 120 is reduced to 30 μm or less, and accordingly, the distance between the centers of the first vias 150 or the first circuit pattern ( 140), the pitch P1, which is an interval between the centers of the pads 142, may be lowered to 100 μm or less, further to 90 μm or less, and further to 80 μm or less.

Hereinafter, a modified example of the circuit board according to the first embodiment shown in FIG. 2 will be described.

-Variation example-

5A is a diagram illustrating a circuit board according to a first modified example.

In FIG. 5A , the arrangement position of the first surface treatment layer 190a may be different from that of FIG. 2 .

The circuit board 100a according to the first modification has a first insulating layer 112 , a core layer 111 , a second insulating layer 113 , and a first circuit pattern 140 corresponding to the circuit board of FIG. 2 . , second circuit pattern 120 , third circuit pattern 125 , fourth circuit pattern 160 , first via 150 , second via 170 , second surface treatment layer 195 , and a protective layer (185).

The circuit board in the first modified example includes the first surface treatment layer 190a. In this case, the first surface treatment layer 190 according to the first embodiment is disposed only on the upper surface of the pad 142 of the first circuit pattern 140 . Alternatively, the first surface treatment layer 190a in the first modified example may be disposed on the upper surface and the side surface of the pad 142 of the first circuit pattern 140 . Accordingly, at least a portion of the first surface treatment layer 190a may directly contact the upper surface of the first insulating layer 112 .

5B is a diagram illustrating a circuit board according to a second modified example.

5B , there is a difference in the width of the pad of the first circuit pattern compared to FIG. 2 .

The circuit board according to the second modified example corresponds to the circuit board of FIG. 2 , the first insulating layer 112 , the core layer 111 , the second insulating layer 113 , the first circuit pattern 140 , and the second Circuit pattern 120 , third circuit pattern 125 , fourth circuit pattern 160 , first via 150 , second via 170 , first surface treatment layer 190 , and second surface treatment layer 195 and a second passivation layer 185 .

The circuit board 100b in the second modified example includes the pads of the first circuit pattern 140 .

The pad of the first circuit pattern 140 includes a first pad 142-1b and a second pad 142-2b. In this case, the width of the first pad 142-1b and the second pad 142-2b may be the same as the width of the first surface or the upper surface of the first via 150 .

For example, the width W1b of the first surface of the first via 150 may be 25 μm to 55 μm. For example, the width W1b of the first surface of the first via 150 may be 27 μm to 50 μm. For example, the width W1b of the first surface of the first via 150 may be 30 μm to 47 μm.

In addition, the first pad 142-1b and the second pad 142-2b of the first circuit pattern may be the same as the width W1b of the first surface of the first via 150 . Accordingly, according to the second modification, the pitch between the first pad 142-1b and the second pad 142-2b may be further reduced compared to the embodiment illustrated in FIG. 2 .

5C is a diagram illustrating a circuit board according to a third modified example.

5C , there is a difference in the width of the pad of the first circuit pattern compared to FIG. 2 .

The circuit board 100c according to the third modified example corresponds to the circuit board of FIG. 2 , the first insulating layer 112 , the core layer 111 , the second insulating layer 113 , and the first circuit pattern 140 . , second circuit pattern 120 , third circuit pattern 125 , fourth circuit pattern 160 , first via 150 , second via 170 , first surface treatment layer 190 , second It includes a surface treatment layer 195 and a protective layer 185 .

The circuit board 100c in the third modified example includes the pads of the first circuit pattern 140 .

The pad of the first circuit pattern 140 includes a first pad 142-1c and a second pad 142-2c. In this case, the width of the first pad 142-1c and the second pad 142-2c may be smaller than the width of the first surface or the upper surface of the first via 150 .

For example, the width W1 of the first surface of the first via 150 may be 25 μm to 55 μm. For example, the width W1 of the first surface of the first via 150 may be 27 μm to 50 μm. For example, the width W1 of the first surface of the first via 150 may be 30 μm to 47 μm.

In addition, the first pad 142-1c and the second pad 142-2c of the first circuit pattern may have a width W3c smaller than the width W1 of the first surface of the first via 150 . can

For example, the width W3c of the first pad 142-1c and the second pad 142-2c of the first circuit pattern may be 5 μm to 50 μm. For example, the width W3c of the first pad 142-1c and the second pad 142-2c of the first circuit pattern may be 10 μm to 40 μm. For example, the width W3c of the first pad 142-1c and the second pad 142-2c of the first circuit pattern may be 15 μm to 35 μm.

When the width W3c of the first pad 142-1c and the second pad 142-2c of the first circuit pattern is less than 5 μm, the first pad 142-1c of the first circuit pattern and The resistance of the second pad 142 - 2c may increase, and thus signal transmission loss may increase. When the width W3c of the first pad 142-1c and the second pad 142-2c of the first circuit pattern is greater than 50 μm, the first pad 142-1c of the first circuit pattern and A pitch between the centers of the second pads 142 - 2c may increase.

In this case, in the embodiment, the width W3c of the first pad 142-1c and the second pad 142-2c of the first circuit pattern is greater than the width W1 of the first surface of the via 150 . It is small and larger than the width W2 of the second surface. Accordingly, in the embodiment, the difference between the widths of the first pad 142-1c and the second pad 142-2c of the first circuit pattern and the width between the first via 150 may be minimized. , it is possible to minimize the signal transmission loss caused by the width difference.

Also, the first surface treatment layer 190c may be disposed only on upper surfaces of the first pad 142-1c and the second pad 142-2c of the first circuit pattern.

Meanwhile, as the width W3c of the first pad 142-1c and the second pad 142-2c of the first circuit pattern is smaller than the width of the first surface of the first vias 151 and 152, , among the traces of the first circuit pattern, the traces connected to the first pad 142-1c and the second pad 142-2c of the first circuit pattern may be in direct contact with the first vias 151 and 152. can

For example, when the first pad 142-1c and the second pad 142-2c of the first circuit pattern are larger than the widths of the first surfaces of the first vias 151 and 152, the first The traces of the circuit pattern may not directly contact the first vias 151 and 152 . Alternatively, in the embodiment, as described above, the first pad 142-1c and the second pad 142-2c of the first circuit pattern are smaller than the widths of the first surfaces of the first vias 151 and 152. As it is formed, at least one of the traces of the first circuit pattern extends from the first pad 142-1c and the second pad 142-2c of the first circuit pattern, so that the first via 151; 152) may be in direct contact with the upper surface.

5D is a diagram illustrating a circuit board according to a fourth modified example.

5D and 5C, there is a difference in the arrangement position of the first surface treatment layer.

The circuit board 100d according to the fourth modified example corresponds to the circuit board of FIG. 5C *, the first insulating layer 112 , the core layer 111 , the second insulating layer 113 , and the first circuit pattern 140 . , second circuit pattern 120 , third circuit pattern 125 , fourth circuit pattern 160 , first via 150 , second via 170 , second surface treatment layer 195 , and a protective layer (185).

In this case, the first surface treatment layer 190d of the circuit board 100d may also be disposed on the side surfaces of the pads 142-1d and 142-2d of the first circuit pattern, unlike the third modified example. .

Also, unlike the third modified example, the first surface treatment layer 190d of the circuit board 100d may be disposed on the upper surface of the first via 150 .

That is, the first surface treatment layer 190d of the circuit board 100d includes a first portion disposed on an upper surface of a pad, a second portion disposed on a side surface of the pad, and a first surface treatment layer 190d disposed on an upper surface of the first via. It can contain 3 parts.

5E is a diagram illustrating a circuit board according to a fifth modified example.

Referring to FIG. 5E , the circuit board has a difference in the number of insulating layers compared to FIG. 2 .

For example, in FIG. 2 , a first insulating layer 112 and a second insulating layer 113 of one layer are respectively disposed above and below the core layer 111 , respectively.

Alternatively, as shown in FIG. 5E , in the circuit board according to the fifth modified example, multi-layered insulating layers may be respectively disposed above and below the core layer 111 . For example, the insulating layer may have a number of layers of 7 or more based on the number of insulating layers.

The circuit board may include a first inner insulating layer 114 disposed between the core layer 111 and the first insulating layer 112 . For example, the first inner insulating layer 114 may include a 1-1 inner insulating layer 114a disposed on the core layer 111 and a 1-1 first inner insulating layer 114a disposed on the 1-1 inner insulating layer 114a. Two inner insulating layers 114b may be included.

Also, the circuit board may include a second inner insulating layer 115 disposed between the core layer 111 and the second insulating layer 113 . For example, the second inner insulating layer 115 may include a 2-1 th inner insulating layer 115a disposed under the core layer 111 and a second inner insulating layer 115a disposed under the 2-1 th inner insulating layer 115a. -2 may include an inner insulating layer 115b.

In addition, the first insulating layer 112 is an insulating layer disposed on the first outermost side of the circuit board, and the second insulating layer 113 is an insulating layer disposed on the second outermost side of the circuit board.

In addition, the embodiment may include circuit patterns and vias disposed on the core layer 111 , the first inner insulating layer 114 , and the second inner insulating layer 115 .

A circuit board according to an embodiment includes a mounting pad disposed in an area on which a chip is mounted. In this case, the mounting pad in the comparative example has a larger width than a solder resist open region (SOR) disposed on the outermost side of the circuit board, and thus the mounting pad has a pitch larger than 110 μm. do. On the contrary, in the circuit board according to the embodiment, the solder resist disposed on the outermost side of the circuit board is removed. Accordingly, the width of the mounting pad in the embodiment is not affected by the size of the solder resist open region (SOR), and thus the width of the mounting pad may be reduced compared to the comparative example. Accordingly, in the embodiment, since the pitch of the mounting pad can be reduced compared to the comparative example, more chips can be mounted in a limited space, and thus the volume of the circuit board and further the volume of the package board can be reduced.

In addition, in the embodiment, as the pitch decreases as described above, the length of the transmission line connecting between the terminals of the chip mounted on the circuit board can be reduced, and thus the communication performance can be improved by minimizing the signal transmission loss. have.

-Second embodiment-

6 is a view showing a circuit board according to the second embodiment, and FIG. 7 is an enlarged view of the outermost side of FIG. 6 .

6 and 7 , the circuit board according to the second embodiment may have an ETS structure. That is, the circuit board according to the first embodiment in FIG. 2 has an SAP structure. Alternatively, the circuit board according to the second embodiment of FIGS. 6 and 7 may have an ETS structure.

Referring to FIG. 6 , the circuit board 200 provides a mounting space in which at least one chip can be mounted.

The circuit board 200 includes an insulating layer 210 , a first circuit pattern 240 , a second circuit pattern 220 , a third circuit pattern 225 , a fourth circuit pattern 260 , and a first via 250 . , a second via 230 , a third via 270 , a first surface treatment layer 290 , a second surface treatment layer 295 , and a protective layer 285 . In this case, a detailed description of the components of the second embodiment that are substantially the same as those of the first embodiment will be omitted.

The circuit board 200 of the second embodiment includes an insulating layer 210 . The insulating layer 210 has a structure of at least one layer. At this time, although FIG. 6 illustrates that the circuit board 200 has a three-layer structure based on the number of insulating layers 210 , the present invention is not limited thereto. For example, the circuit board 200 may have a structure of one or two layers based on the number of layers of the insulating layer 210 , or alternatively may have a structure of four or more layers. However, hereinafter, the circuit board 200 will be described as having a one-layer structure based on the number of layers of the insulating layer 210 .

The insulating layer 210 may include a prepreg (PPG). The prepreg may be formed by impregnating a fiber layer in the form of a fabric sheet, such as a glass fabric woven with glass yarn, with an epoxy resin, and then performing thermocompression. However, the embodiment is not limited thereto, and the prepreg constituting the insulating layer 210 may include a fiber layer in the form of a fabric sheet woven with carbon fiber yarn.

The insulating layer 210 may include an inner insulating layer 211 , a first insulating layer 212 , and a second insulating layer 213 .

Each of the inner insulating layer 211 , the first insulating layer 212 , and the second insulating layer 213 may have a thickness in a range of 10 μm to 60 μm. For example, each of the inner insulating layer 211 , the first insulating layer 212 , and the second insulating layer 213 may have a thickness in the range of 15 μm to 55 μm. For example, each of the inner insulating layer 211 , the first insulating layer 212 , and the second insulating layer 213 may have a thickness in a range of 20 μm to 50 μm. Each thickness of the inner insulating layer 211 , the first insulating layer 212 , and the second insulating layer 213 may mean a distance between circuit patterns respectively disposed on the surface thereof.

For example, the thickness of the first insulating layer 212 may mean a distance between the lower surface of the first circuit pattern 240 and the upper surface of the second circuit pattern 220 . The thickness of the inner insulating layer 211 may mean a distance between the lower surface of the second circuit pattern 220 and the upper surface of the third circuit pattern 225 . The thickness of the second insulating layer 213 may mean a thickness between the lower surface of the third circuit pattern 225 and the upper surface of the fourth circuit pattern 260 .

Circuit patterns are respectively disposed on the surfaces of the inner insulating layer 211 , the first insulating layer 212 , and the second insulating layer 213 .

For example, the first circuit pattern 240 is disposed on the first surface or the upper surface of the first insulating layer 212 . In addition, a second circuit pattern 220 is disposed on the second surface or the lower surface of the first insulating layer 212 . In addition, a third circuit pattern 225 is disposed on the second or lower surface of the inner insulating layer 211 . In addition, a fourth circuit pattern 260 is disposed on the second or lower surface of the second insulating layer 213 . The circuit board 200 of the second embodiment may be manufactured using an Embedded Trace Substrate (ETS) method. Accordingly, at least one of the circuit patterns included in the circuit board 200 may have an ETS structure. For example, the first circuit pattern 240 disposed on the first outermost side of the circuit patterns included in the circuit board 200 has an ETS structure, and thus the first surface of the first insulating layer 212 . Alternatively, it may have a structure buried in the upper surface.

The first circuit pattern 240 of the embodiment may include a trace 241 and a pad 242 . The pad 2142 of the first circuit pattern 240 may be disposed in a chip mounting area (not shown) in which a chip is to be mounted on the circuit board 200 . For example, the pad 242 of the first circuit pattern 240 may mean a chip mounting pad.

The pad 242 of the first circuit pattern 240 is disposed on the first surface or the top surface of the first via 250 passing through the first insulating layer 212 . For example, the pad 242 of the first circuit pattern 240 may be disposed on the first surface of the first via 250 and may be electrically connected to the trace 241 .

The first circuit pattern 240 may have a thickness in a range of 5 μm to 20 μm. For example, the first circuit pattern 240 may have a thickness in a range of 6 μm to 17 μm. The first circuit pattern 240 may have a thickness in a range of 7 μm to 13 μm. When the thickness of the first circuit pattern 240 is less than 5 μm, the resistance of the first circuit pattern 240 may increase. When the thickness of the first circuit pattern 240 exceeds 20 μm, the line width of the trace 241 constituting the first circuit pattern 240 increases, and thus the overall volume of the circuit board 200 decreases. can increase

The trace 241 of the first circuit pattern 240 may have a specific line width W5' and a specific interval W6'. For example, the line width W5 ′ of the trace 241 of the first circuit pattern 240 may be in a range of 6 μm to 20 μm. For example, the line width W5 ′ of the trace 241 of the first circuit pattern 240 may be in a range of 7 μm to 15 μm. For example, the line width W5 ′ of the trace 241 of the first circuit pattern 240 may range from 8 μm to 12 μm. Also, the interval W6 ′ between the traces of the first circuit pattern 240 may be in a range of 6 μm to 20 μm. For example, the interval W6 ′ between the traces of the first circuit pattern 240 may be in a range of 7 μm to 15 μm. For example, the interval W6 ′ between the traces of the first circuit pattern 240 may be in a range of 8 μm to 12 μm.

In an embodiment, at least one trace 241 of the first circuit pattern 240 may be positioned between a plurality of pads 242 of the first circuit pattern 240 used as mounting pads. For example, the pad 242 of the first circuit pattern 240 may include a first pad 242-1 and a second pad 242-2 spaced apart from each other in the width direction. In addition, on the upper surface of the first insulating layer 212 , the first circuit pattern 240 is between the first pad 242-1 and the second pad 242-2 of the first circuit pattern 240 . ) of at least one trace 241 may be disposed. The trace 241 disposed between the pads is directly connected to at least one of the first pad 242-1 and the second pad 242-2, or the other of the first insulating layer 212 except this. It can be directly connected to the pad.

Meanwhile, in general, the width of the mounting pad is determined by the width of the via and the size of the open area of the solder resist, and the pitch between the plurality of mounting pads is determined by the width of the mounting pad. In addition, at least one trace should be disposed between the mounting pads. Accordingly, in the comparative example, the pitch of the mounting pads exceeds 110 μm due to the width of the mounting pad and the width of the trace. Alternatively, in the embodiment, the solder resist is removed, and accordingly, the width of the mounting pad can be formed without considering the size of the open area of the solder resist. Accordingly, in the embodiment, the width of the mounting pad may be reduced compared to that of the comparative example. Also, in an embodiment, the spacing between the vias may be reduced as much as the width of the mounting pad is reduced. That is, the pitch of the mounting pad in the embodiment only needs to consider the width of the via and the distance therebetween, and accordingly, the pitch of the mounting pad may be reduced compared to the comparative example.

Specifically, in the first embodiment, the width W3 ′ of the pad 242 of the first circuit pattern 240 is greater than the width W1 ′ of the first surface or the top surface of the first via 250 . can

For example, the width W3 ′ of the pad 242 of the first circuit pattern 240 may be 22 μm to 42 μm. For example, the width W3 ′ of the pad 242 of the first circuit pattern 240 may be 25 μm to 40 μm. For example, the width W3 ′ of the pad 242 of the first circuit pattern 240 may be 27 μm to 37 μm. That is, in the comparative example, the width W3 ′ of the pad 242 of the first circuit pattern 240 was formed to be 70 μm or more to correspond to the size of the open region of the solder resist. Unlike this, the pad 242 of the first circuit pattern 240 is formed without considering the size of the open region of the solder resist, so that the width W1 ′ of the first surface of the first via 250 . It may have a width W3' similar to . For example, a width of the pad 242 of the first circuit pattern 240 may satisfy a range of 101% to 130% of a width of the first surface of the first via. For example, a width of the pad 242 of the first circuit pattern 240 may satisfy a range of 102% to 125% of a width of the first surface of the first via. For example, a width of the pad 242 of the first circuit pattern 240 may satisfy a range of 105% to 120% of a width of the first surface of the first via.

As described above, in the circuit board in the embodiment, the solder resist, which is a protective layer disposed on the first outermost side of the circuit board, is removed. Accordingly, in the embodiment, when determining the width W3 ′ of the pad 242 , it is not necessary to consider the size of the open area SOR of the solder resistor. Accordingly, in the embodiment, the width W3 ′ of the pad 242 may be reduced compared to the comparative example, and further, the pitch between neighboring pads may be reduced to 100 μm or less.

Also, in an embodiment, the width W3 ′ of the pad 242 of the first circuit pattern 240 may be smaller than the width W4 ′ of the pad 24 of the second circuit pattern 220 .

The second circuit pattern 220 may be disposed on the second surface or the lower surface of the first insulating layer 212 . For example, the second circuit pattern 220 may be disposed on a surface of the first insulating layer 212 opposite to a surface on which the first circuit pattern 240 is disposed.

The second circuit pattern 220 may be connected to the first via 250 . Specifically, the second circuit pattern 220 may include pads 221 and 222 and traces. In addition, the pads 221 and 222 of the second circuit pattern 220 may be connected to the first via 250 .

The pads 221 and 222 of the second circuit pattern 220 may be connected to a second surface or a lower surface of the first via 250 . Specifically, the first surface or upper surface of the pads 221 and 222 of the second circuit pattern 220 may directly contact the second surface or lower surface of the first via 250 . Traces of the second circuit pattern 220 may not be disposed between the pads 221 and 222 of the second circuit pattern 220 .

The gap W7 ′ between the pads 221 and 222 of the second circuit pattern 220 may be 30 μm or less. For example, the gap W7 ′ between the pads 221 and 222 of the second circuit pattern 220 may be 20 μm or less. For example, the interval W7 ′ between the pads 221 and 222 of the second circuit pattern 220 may be 10 μm or less. For example, the gap W7 ′ between the pads 221 and 222 of the second circuit pattern 220 may be 7 μm or less. For example, the gap W7 ′ between the pads 221 and 222 of the second circuit pattern 220 may be 5 μm or less. For example, the gap W7 ′ between the pads 221 and 222 of the second circuit pattern 220 may be 2 μm or more.

Specifically, the interval W7 ′ between the pads 221 and 222 of the second circuit pattern 220 may be in a range of 2 μm to 30 μm. For example, the interval W7 ′ between the pads 221 and 222 of the second circuit pattern 220 may be in a range of 2.5 μm to 20 μm. For example, the gap W7 ′ between the pads 221 and 222 of the second circuit pattern 220 may be in a range of 2.5 μm to 7 μm. Preferably, the interval W7 ′ between the pads 221 and 222 of the second circuit pattern 220 is that of the trace 241 of the first circuit pattern 240 or the trace of the second circuit pattern 220 . It may be smaller than the line width or spacing.

The width W4' of the pads 221 and 222 of the second circuit pattern 220 may be 30 μm to 75 μm. For example, the width W4 ′ of the pads 221 and 222 of the second circuit pattern 220 may be 32 μm to 70 μm. For example, the width W4 ′ of the pads 221 and 222 of the second circuit pattern 220 may be 35 μm to 65 μm.

In an embodiment, vias may be formed in each of the inner insulating layer 211 , the first insulating layer 212 , and the second insulating layer 213 .

For example, a first via 250 may be formed in the first insulating layer 212 . Also, a second via 230 may be formed in the inner insulating layer 211 . Also, a third via 270 may be formed in the second insulating layer 213 . In this case, the first via 250 , the second via 230 , and the third via 270 may have the same shape. That is, each of the first via 250 , the second via 230 , and the third via 270 may have a trapezoidal shape in which the width of the first surface is smaller than the width of the second surface. For example, the width of the upper surface of each of the first via 250 , the second via 230 , and the third via 270 may be smaller than the width of the lower surface.

A first surface or an upper surface of the first via 250 may contact a lower surface of the pad 242 of the first circuit pattern 240 . Also, a second surface or a lower surface of the first via 250 may contact the second circuit pattern 220 . For example, the second surface or lower surface of the first via 250 may contact the pads 221 and 122 of the second circuit pattern 220 .

The first via 250 may include a 1-1 via 251 and a 1-2 via 252 .

A width W1 ′ of the first surface of the 1-1 via 251 and the 1-2 via 252 may be 20 μm to 40 μm. For example, the width W1 ′ of the first surface of the 1-1 via 251 and the 1-2 via 252 may be 22 μm to 37 μm. For example, the width W1 ′ of the first surface of the 1-1 via 251 and the 1-2 via 252 may be 25 μm to 35 μm.

In addition, the width W2 ′ of the second surface of the 1-1 via 251 and the 1-2 via 252 may be 25 μm to 55 μm. For example, the width W2 ′ of the second surface of the 1-1 via 251 and the 1-2 via 252 may be 27 μm to 50 μm. For example, the width W2 ′ of the second surface of the 1-1 via 251 and the 1-2 via 252 may be 30 μm to 47 μm.

As described above, in the second embodiment, there is a difference in that the circuit board 200 has an ETS structure compared to the first embodiment, and accordingly, the pads and traces of the circuit pattern disposed on the outermost side are the first ones of the outermost insulating layer. There is a difference in having a structure embedded in a surface or an upper surface.

In the second embodiment, the width of the pad of the first circuit pattern 240 can be reduced compared to the comparative example by removing the solder resist, and thereby, in the embodiment, the pads 221 of the second circuit pattern 220, 222), a space for arranging at least one trace 241 in the space between the pads 242 of the first circuit pattern 240 even if the interval between them is reduced to 30 μm or less (and further reduced to 2 μm). This will come out enough. Accordingly, in the embodiment, the distance between the pads 221 and 222 of the second circuit pattern 220 is reduced to 30 μm or less, and accordingly, the distance between the centers of the first vias 250 or the first circuit pattern ( The pitch, which is an interval between the centers of the pads 242 of 240 , may be lowered to 100 μm or less, further to 90 μm or less, and further to 80 μm or less.

Furthermore, in the second embodiment, the pad 242 of the first circuit pattern 240 used as a mounting pad is disposed on the first surface of the first via 250 . In this case, the width of the first surface of the first via 250 is narrower than the width of the second surface. Accordingly, in the embodiment, compared to the first embodiment, the space between the pads 242 of the first circuit pattern 240 can be secured more widely, and thus more traces can be arranged in the corresponding space.

Hereinafter, a modified example of the circuit board according to the second embodiment shown in FIG. 6 will be described.

-Variation example-

8A is a diagram illustrating a circuit board according to a first modified example.

The circuit board 200a of the first modified example of FIG. 8A has a difference in the width of the pad of the first circuit pattern compared to the circuit board of FIG. 6 .

For example, the pad 242 of the first circuit pattern 240 of FIG. 6 has a width greater than the width of the first surface of the first via 250 .

On the other hand, as in the first modified example, the pads 242-1a and 242-2a of the first circuit pattern 240 are equal to the width W1'a of the first surfaces of the first vias 251 and 252. can have a width. Accordingly, according to the first modified example, a space between the pads 242-1a and 242-2a of the first circuit pattern 240 can be secured more widely compared to the circuit board of the second embodiment.

8B is a diagram illustrating a circuit board according to a second modified example.

The circuit board 200b of the second modified example of FIG. 8B has a difference in the width of the pad of the first circuit pattern compared to the circuit board of FIG. 6 .

For example, the pad 242 of the first circuit pattern 240 of FIG. 6 has a width greater than the width of the first surface of the first via 250 .

On the contrary, as in the first modified example, the pads 242-1b and 242-2b of the first circuit pattern 240 are smaller than the width W1'b of the first surface of the first vias 251b and 252b. It may have a width W3'b.

Accordingly, according to the second modification, the first surface of the first vias 251b and 252b may be positioned on the same plane as the first surface of the first insulating layer 212 .

Furthermore, the first vias 251b and 252b may be formed to surround the pads 242-1b and 242-2b of the first circuit pattern 240 . Accordingly, the trace 241b of the first circuit pattern 240 may not be directly connected to the pads 242-1b and 242-2b of the first circuit pattern 240 . For example, the trace 241b of the first circuit pattern 240 is not directly connected to the pads 242-1b and 242-2b of the first circuit pattern 240, but the first via 251b, 252b) can be directly connected.

Accordingly, the mounting pad in the second modified example is formed of the first portion formed of the pads 242-1b and 242-2b of the first circuit pattern 240 and the first vias 251b and 252b. It may include a second part that becomes

8C is a diagram illustrating a circuit board according to a third modified example.

The circuit board 200c of the third modified example of FIG. 8C is different from the circuit board of FIG. 6 in the configuration of the pad of the first circuit pattern.

In the circuit board 200c according to the third modification, the pad of the first circuit pattern disposed on the first surface of the first vias 251c and 252c may be removed.

That is, according to the third modified example, the first circuit pattern may include the trace 241b. The trace 241b may be directly connected to side surfaces of the first vias 251c and 252c used as mounting pads.

The first via includes a 1-1 via 251c and a second via 252c that are spaced apart from each other in the width direction. In this case, each of the 1-1 via 251c and the second via 252c has a thickness greater than that of the first insulating layer 212 . For example, each of the 1-1 via 251c and the second via 252c may have a thickness obtained by adding the thickness of the first insulating layer 212 to the thickness of the trace 241b of the first circuit pattern. . The first surface or top surface of the 1-1 via 251c and the second via 252c may be located on the same plane as the first surface or top surface of the first circuit pattern. The 1-1 via 251c and the second via 252c may be directly connected to the first circuit pattern through side surfaces. That is, side surfaces of the 1-1 via 251c and the second via 252c may be connected to the side surface of the first circuit pattern.

As described above, according to the third modification, the first surfaces of the 1-1 via 251c and the second via 252c are used as the mounting pad, and thus the width of the mounting pad can be further reduced.

A circuit board according to an embodiment includes a mounting pad disposed in an area on which a chip is mounted. In this case, the mounting pad in the comparative example has a larger width than a solder resist open region (SOR) disposed on the outermost side of the circuit board, and thus the mounting pad has a pitch larger than 110 μm. do. On the contrary, in the circuit board according to the embodiment, the solder resist disposed on the outermost side of the circuit board is removed. Accordingly, the width of the mounting pad in the embodiment is not affected by the size of the solder resist open region (SOR), and thus the width of the mounting pad may be reduced compared to the comparative example. Accordingly, in the embodiment, since the pitch of the mounting pad can be reduced compared to the comparative example, more chips can be mounted in a limited space, and thus the volume of the circuit board and further the volume of the package board can be reduced.

In addition, in the embodiment, as the pitch decreases as described above, the length of the transmission line connecting between the terminals of the chip mounted on the circuit board can be reduced, and thus the communication performance can be improved by minimizing the signal transmission loss. have.

-Manufacturing method of the first embodiment-

9A to 9F are views for explaining the manufacturing method of the circuit board shown in FIG. 2 in order of process.

Referring to FIG. 9A , in the embodiment, a basic material for manufacturing a circuit board may be prepared. For example, the circuit board of the embodiment may be a core board. To this end, in the embodiment, a base material for the central core layer may be prepared. As an example, CCL (Copper Clad Laminate) may be prepared, but is not limited thereto.

In an embodiment, when the core layer 111 is prepared, a process of forming the via hole VH by processing the core layer 111 may be performed. The via hole VH may be formed by laser processing the core layer 111 . In this case, the core layer 111 has a predetermined thickness or more, and it may be difficult to easily form a via hole completely penetrating it through one laser processing. Accordingly, in the embodiment, a process of processing the via holes VH on the first and second surfaces of the core layer 111 may be performed, respectively. In addition, as the via hole processing process is performed on both surfaces of the core layer 111 as described above, an hourglass-shaped via hole VH may be formed in the core layer 111 .

Next, referring to FIG. 9B , in the embodiment, a process of forming a dry film on each of the first and second surfaces of the core layer 111 may be performed.

Specifically, in the embodiment, the process of forming the first dry film DF1 on the first surface of the core layer 111 and forming the second dry film DF2 on the second surface of the core layer 111 is performed. can

In this case, the first dry film DF1 and the second dry film DF2 may be disposed to cover the entire first surface and the second surface of the core layer 111 . Thereafter, in an embodiment, the first dry film DF1 and the second dry film DF2 may be exposed and developed, respectively, to form an opening (not shown).

For example, in the embodiment, an opening (not shown) exposing a region in which the via hole VH and the second circuit pattern 120 are to be formed may be formed in the first dry film DF1 .

For example, in an embodiment, an opening (not shown) exposing a region in which the via hole VH and the third circuit pattern 125 are to be formed may be formed in the second dry film DF2 .

Next, as shown in FIG. 9C , in the embodiment, a plating process for filling the openings of the first dry film DF1 and the second dry film DF2 may be performed. To this end, in the embodiment, before the first dry film DF1 and the second dry film DF2 are formed, a seed layer (not shown) on the first and second surfaces of the core layer 111, respectively. The process of forming can be carried out. Thereafter, in the embodiment, electrolytic plating is performed using the formed seed layer to fill the via hole VH, the opening of the first dry film DF1, and the opening of the second dry film DF2. can proceed. In addition, in an embodiment, when the electrolytic plating process is completed, a process of removing the first dry film DF1 and the second dry film DF2 may be performed.

Next, as shown in FIG. 9D , in the embodiment, a process of laminating the first insulating layer 112 and the second insulating layer 113 on the first and second surfaces of the core layer 111 is performed, respectively. can proceed. Each of the first insulating layer 112 and the second insulating layer 113 may include a prepreg.

Next, as shown in FIG. 9E , in the embodiment, a process of forming the first via 150 and the first circuit pattern 140 in the first insulating layer 112 may be performed. In this case, as described above, the first circuit pattern 140 includes the trace 141 and the pad 142 . In addition, the pad 142 of the first circuit pattern 140 may have a width greater than the width of the first via 150 penetrating the first insulating layer 112 . However, in an embodiment, the width of the pad 142 may be determined without considering the size of the open area of the solder resist. Accordingly, in an embodiment, the pad 142 may be formed to have a width substantially similar to or equal to the width of the first surface of the first via 150 . However, as shown in FIGS. 5A to 5C , the width of the pad 142 of the first circuit pattern may be the same as the width of the first surface of the first via 150 , and Alternatively, the width of the first via 150 may be smaller than the width of the first surface.

Also, in an embodiment, a process of forming the second via 170 and the fourth circuit pattern 160 in the second insulating layer 113 may be performed. The fourth circuit pattern 160 includes a pad and a trace, and in this case, the pad of the fourth circuit pattern 160 may have a greater width than the second via 170 .

Next, as shown in FIG. 9F , in the embodiment, a process of forming the protective layer 185 on the second surface or the lower surface of the second insulating layer 113 may be performed. The protective layer 185 may include an opening (not shown) exposing the pad of the fourth circuit pattern 160 disposed on the second surface of the second insulating layer 113 . In this case, the opening of the protective layer 185 may have a width smaller than the width of the pad of the fourth circuit pattern 160 . However, the embodiment is not limited thereto, and the opening of the protective layer 185 may be formed to be greater than or equal to the width of the pad of the fourth circuit pattern 160 . The protective layer 185 is formed only on the lower surface of the second insulating layer 113 and is not formed on the upper surface of the first insulating layer 112 .

However, the embodiment is not limited thereto, and the protective layer 185 disposed on the lower surface of the second insulating layer 113 may also be removed. Accordingly, in the circuit board of the embodiment, the outermost surface may be composed of an upper surface of the first insulating layer 112 and a lower surface of the second insulating layer 113 . That is, in another embodiment, the solder resist may not be disposed on the first and second outermost sides of the circuit board.

Next, in the embodiment, a process of forming the first surface treatment layer 190 on the pad 142 of the first circuit pattern 140 may be performed. Also, in an embodiment, a process of forming the second surface treatment layer 195 on the pad of the fourth circuit pattern 160 exposed through the opening of the protective layer 185 may be performed.

- Manufacturing method of the second embodiment -

10A to 10H are views for explaining the manufacturing method of the circuit board shown in FIG. 6 in order of process.

Referring to FIG. 10A , in the embodiment, a basic material for manufacturing a circuit board may be prepared by the ETS method.

For example, in the embodiment, the carrier board CB in which the carrier insulating layer CB1 and the metal layer CB2 are disposed on at least one surface of the carrier insulating layer CB1 may be prepared. In this case, the metal layer CB2 may be disposed on only one of the first and second surfaces of the carrier insulating layer CB1 , or alternatively, it may be disposed on both surfaces of the carrier insulating layer CB1 . For example, the metal layer CB2 is disposed on only one surface of the carrier insulating layer CB1 , and accordingly, the ETS process for manufacturing the circuit board may be performed only on the one surface. Alternatively, the metal layer CB2 may be disposed on both surfaces of the carrier insulating layer CB1, and accordingly, the ETS process for manufacturing the circuit board may be simultaneously performed on both surfaces of the carrier board CB. In this case, two circuit boards can be manufactured at once.

The metal layer CB2 may be formed by electroless plating on the carrier insulating layer CB1 . Alternatively, the carrier insulating layer CB1 and the metal layer CB2 may be copper clad laminate (CCL).

Next, in the embodiment, a dry film DF3 is formed on the metal layer CB2 . In this case, the dry film DF3 may be disposed to cover the entirety of the metal layer CB2 . Thereafter, in an embodiment, the dry film DF3 may be exposed and developed to form an opening (not shown). In this case, the opening of the dry film DF3 may expose a region where the first circuit pattern 240 is to be formed.

In this case, as shown in FIG. 10A , the first circuit pattern 240 may include a trace 241 and a pad 242 . In addition, the width of the pad 242 may be greater than the width of the first via 250 formed in a subsequent process. Accordingly, in the opening of the dry film DF3 , a region corresponding to the pad 242 may have a width greater than a width of the first via 250 .

Thereafter, in the embodiment, the process of forming the first circuit pattern 240 filling the opening of the dry film DF3 may be performed by electroplating the metal layer CB2 as a seed layer.

Next, referring to FIG. 10B , in the embodiment, a process of forming the first insulating layer 212 on the metal layer CB2 may be performed. The first insulating layer 212 may include a prepreg as described above.

Next, in the embodiment, a laser mask (not shown) may be formed on the first insulating layer 212 , and a via hole VH may be formed using the laser mask (not shown). In this case, the laser mask (not shown) may include an opening exposing a region where the via hole VH is to be formed. Thereafter, in an embodiment, a via hole VH passing through the first insulating layer 212 may be formed by irradiating a laser beam into the opening of the laser mask.

At this time, as described above, the width of the pad 242 of the first circuit pattern 240 formed on the metal layer CB2 is greater than the width of the via hole VH, and thus, through the via hole VH A portion of the upper surface of the pad 242 of the first circuit pattern 240 may be exposed.

Alternatively, referring to FIG. 10C , the pad 242a of the first circuit pattern may have the same width as the via hole VHa. Accordingly, as the via hole VHa is formed, the entire surface of the pad 242a may be exposed through the via hole VHa. This may be a method for manufacturing the circuit board shown in FIG. 8A .

Alternatively, referring to FIG. 10D , the pad 242b of the first circuit pattern may be smaller than the width of the via hole VHb. Accordingly, the via hole VHb may be formed to surround the pad 242b. Accordingly, the via hole VHb may expose a portion of the surface of the metal layer CB2 . This may be a method for manufacturing the circuit board shown in FIG. 8B .

Alternatively, referring to FIG. 10E , the first circuit pattern may include only the trace 241c. That is, the first circuit pattern may not include a pad disposed in a region where the via hole VHc is to be formed. Accordingly, the via hole VHc may be formed using the metal layer CB2 as a stopper. Accordingly, as the via hole VHc is formed, the metal layer CB2 may be exposed through the via hole VHc. This may be a method for manufacturing the circuit board shown in FIG. 8C .

Next, as in FIG. 10F , the following process may be performed using any one of the circuit boards of FIGS. 10B, 10C, 10D, and 10E.

For example, in an embodiment, the first via 250 filling the via hole VH may be formed. Thereafter, in an embodiment, a process of forming the second circuit pattern 220 connected to the first via 250 on the second surface of the first insulating layer 212 may be performed.

Next, in the embodiment, as shown in FIG. 10G , a multilayer circuit board may be manufactured by sequentially performing an insulating layer lamination process, a via hole forming process, and a via and circuit pattern forming process.

Thereafter, in the embodiment, as the multilayer circuit board is manufactured, the two circuit boards formed on the upper and lower portions of the carrier insulating layer CB1 may be separated from each other.

Next, in the embodiment, as shown in FIG. 10H , a process of removing the metal layer CB2 by etching may be performed. Thereafter, in the embodiment, a process of forming the first surface treatment layer 290 on the pad 242 of the first circuit pattern 240 may be performed.

In addition, in the embodiment, the protective layer 285 is formed on the second surface or the lower surface of the second insulating layer 213 , and the fourth circuit pattern 260 exposed through the opening of the protective layer 285 is formed. A process of forming the second surface treatment layer 295 on the two surfaces or the lower surface may be performed.

- Package board -

11 is a view showing a package substrate according to the first embodiment.

Referring to FIG. 11 , the package substrate may include the circuit board shown in any one of FIGS. 2, 5A, 5B, 5C, 5D, and 5E. However, as the package substrate, a chip is mounted using a multilayer substrate, and accordingly, the package substrate including the circuit substrate shown in FIG. 5E will be described. However, the embodiment is not limited thereto, and the circuit board may include a circuit board included in other drawings.

The package substrate 300 includes a circuit board 100 .

In addition, the package substrate 300 includes the first adhesive portion 310 disposed on the mounting pad of the circuit board. Preferably, in an embodiment, the circuit board may form the first adhesive part 310 on the pad 142 of the first circuit pattern 140 . In this case, a first surface treatment layer 190 may be formed on the pad 142 of the first circuit pattern 140 , and accordingly, the first adhesive part 310 is formed on the first surface treatment layer 190 . may be formed in

The first adhesive part 310 may have a hexahedral shape, for example. For example, the cross-section of the first adhesive part 310 may include a rectangular shape. For example, a cross-section of the first adhesive part 310 may have a rectangular or square shape. As another example, the first adhesive part 310 may have a spherical shape. For example, the cross-section of the first adhesive part 310 may include a circular shape or a semicircular shape. For example, the cross-section of the first adhesive part 310 may include a partially or entirely rounded shape. For example, the cross-sectional shape of the first adhesive part 310 may include a flat surface on one side and a curved surface on the other side opposite to the one side. Meanwhile, the first adhesive part 310 may be a micro ball, but is not limited thereto.

A chip 320 may be mounted on the first adhesive part 310 . The chip 320 to which the terminal 330 is connected may be mounted on the first adhesive part 310 .

Meanwhile, the width of the first adhesive part 310 may be smaller than the width of the pad 142 of the first circuit pattern 140 disposed on the uppermost side of the circuit board. For example, in the embodiment, the width of the first adhesive part 310 may be 15 μm to 50 μm. For example, the width of the first adhesive part 310 may be 17 μm to 40 μm. The width of the first adhesive part 310 may be 20 μm to 30 μm.

Accordingly, in the embodiment, the width of the first adhesive part 310 is smaller than the width of the pad of the first circuit pattern, so that the first adhesive part 310 affects the pitch of the pad of the first circuit pattern. do not give Accordingly, in an embodiment, a pitch between the plurality of first adhesive portions may correspond to a pitch of the pads of the first circuit pattern.

For example, the chip 320 may include a drive IC chip. For example, the chip 320 may refer to various chips including sockets or devices other than a drive IC chip. For example, the chip 320 may include at least one of a diode chip, a power IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, and a chip capacitor. For example, the chip 320 may be a power management integrated circuit (PMIC). For example, the chip 320 may be a memory chip such as a volatile memory (eg, DRAM), a non-volatile memory (eg, ROM), a flash memory, or the like. For example, the chip 320 is an application processor (AP) chip such as a central processor (eg, CPU), a graphic processor (eg, GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, or an analog It may be a logic chip such as a digital converter or an application-specific IC (ASIC). Here, although it is illustrated that only one chip is mounted on the package substrate in the drawings, the present invention is not limited thereto. For example, a plurality of chips may be mounted on the circuit board spaced apart from each other. The plurality of chips may include a first AP chip corresponding to a central processor (CPU) and a second AP chip corresponding to a graphics processor (GPU).

A molding layer 330 may be formed on the circuit board. The molding layer 330 may be disposed to cover the mounted chip 320 . For example, the molding layer 330 may be an epoxy mold compound (EMC) formed to protect the mounted chip 320 , but is not limited thereto.

At this time, in the embodiment, the solder resist is not disposed on the first outermost side of the circuit board. Accordingly, the molding layer 330 may be disposed to cover the circuit pattern disposed on the outermost side of the circuit board. For example, the molding layer 330 may be disposed to cover the traces 141 and the pads 142 of the first circuit pattern 140 disposed on the outermost side of the circuit board.

Meanwhile, when the circuit board has a multilayer structure, the line widths or intervals of circuit patterns disposed on each insulating layer may be different from each other. For example, a circuit pattern disposed closest to the chip may have the smallest line width and spacing, and a circuit pattern disposed furthest from the chip may have the largest line width and spacing.

Accordingly, the respective vias disposed on different layers of the circuit board in the embodiment may have different widths.

For example, the via disposed in the insulating layer disposed adjacent to the chip may have a width corresponding to the first via 150 described above. In addition, the width of the via disposed in another insulating layer may gradually increase as the distance from the first via 150 increases. For example, a via disposed on the lowermost side of the circuit board may have the largest width.

Meanwhile, in an embodiment, the second adhesive part 350 may be disposed on the lowermost side of the circuit board and on the circuit pattern exposed through the opening of the protective layer 185 . Preferably, the second adhesive part 350 may be disposed on the pad of the fourth circuit pattern 160 exposed through the opening of the protective layer 185 . In this case, a second surface treatment layer 195 may be formed on the pad of the fourth circuit pattern 160 . Accordingly, the second adhesive part 350 may be disposed on the second surface treatment layer 195 which is the surface treatment layer of the fourth circuit pattern 160 .

The second adhesive part 350 may be a solder ball. The second adhesive part 350 may be connected to the main board of the external substrate.

12 is a view showing a package substrate according to a second embodiment.

Referring to FIG. 12 , the package substrate may include the circuit boards illustrated in FIGS. 6 , 8A, and 8B .

The package substrate 400 includes a circuit board 200 .

In addition, the package substrate 400 may be substantially the same as that of the package substrate of FIG. 11 , except that only the structure of the circuit board is different from that of the package substrate of FIG. 11 .

For example, the package substrate 400 may include a first adhesive part 410 , a chip 420 including a terminal 430 , a molding layer 440 , and a second adhesive part 450 .

A circuit board according to an embodiment includes a mounting pad disposed in an area on which a chip is mounted. In this case, the mounting pad in the comparative example has a width greater than a solder resist open region (SOR) disposed on the outermost side of the circuit board, and thus the mounting pad has a pitch greater than 110 μm. do. On the contrary, in the circuit board according to the embodiment, the solder resist disposed on the outermost side of the circuit board is removed. Accordingly, the width of the mounting pad in the embodiment is not affected by the size of the solder resist open region (SOR), and thus the width of the mounting pad may be reduced compared to the comparative example. Accordingly, in the embodiment, since the pitch of the mounting pads can be reduced compared to the comparative example, more chips can be mounted in a limited space, and thus the volume of the circuit board and thus the volume of the package board can be reduced.

In addition, in the embodiment, as the pitch decreases as described above, the length of the transmission line connecting between the terminals of the chip mounted on the circuit board can be reduced, and thus the communication performance can be improved by minimizing the signal transmission loss. have.

Features, structures, effects, etc. described in the above embodiments are included in at least one embodiment, and are not necessarily limited to only one embodiment. Furthermore, features, structures, effects, etc. illustrated in each embodiment can be combined or modified for other embodiments by those of ordinary skill in the art to which the embodiments belong. Accordingly, the contents related to such combinations and modifications should be interpreted as being included in the scope of the embodiments.

In the above, the embodiment has been mainly described, but this is only an example and does not limit the embodiment, and those of ordinary skill in the art to which the embodiment pertains are provided with several examples not illustrated above within a range that does not depart from the essential characteristics of the embodiment. It can be seen that variations and applications of branches are possible. For example, each component specifically shown in the embodiment can be implemented by modification. And differences related to such modifications and applications should be construed as being included in the scope of the embodiments set forth in the appended claims.

Claims (17)

a first insulating layer;
a plurality of first vias passing through the first insulating layer;
a first circuit pattern disposed on an upper surface of the first insulating layer and including a plurality of pads connected to upper surfaces of the plurality of first vias; and
a second circuit pattern disposed on a lower surface of the first insulating layer and including a plurality of pads connected to lower surfaces of the plurality of first vias;
The first insulating layer is a first outermost insulating layer disposed on the first outermost side of the circuit board,
The upper surface of the first insulating layer is exposed to the first outermost side to constitute a first outermost surface of the circuit board,
A pitch corresponding to a distance between the centers of the plurality of pads of the first circuit pattern is 100 μm or less,
circuit board. The method of claim 1,
The plurality of pads of the first circuit pattern,
disposed to protrude above the upper surface of the first insulating layer,
circuit board. 3. The method of claim 2,
The width of the upper surface of the first via is greater than the width of the lower surface,
The pad of the first circuit pattern has a width in the range of 101% to 130% of the width of the upper surface of the first via,
circuit board. 3. The method of claim 2,
The width of the upper surface of the first via is greater than the width of the lower surface,
The pad of the first circuit pattern has a width smaller than a width of an upper surface of the first via,
circuit board. 5. The method of claim 4,
The pad of the first circuit pattern,
smaller than the width of the pad of the second circuit pattern,
greater than the width of the lower surface of the first via;
circuit board. 6. The method of claim 5,
The first circuit pattern includes a trace connected to a pad of the first circuit pattern,
The trace includes a portion in direct contact with the pad of the first circuit pattern and the upper surface of the first via,
circuit board. 6. The method according to any one of claims 1 to 5,
The first circuit pattern is
and a trace disposed on an upper surface of the first insulating layer and disposed between the plurality of pads of the first circuit pattern,
circuit board. According to claim 1,
The plurality of pads of the first circuit pattern,
disposed to be buried in the upper surface of the first insulating layer,
circuit board. 9. The method of claim 8,
The width of the upper surface of the first via is smaller than the width of the lower surface,
The pad of the first circuit pattern has a width in the range of 101% to 130% of the width of the upper surface of the first via,
circuit board. 9. The method of claim 8,
The width of the upper surface of the first via is smaller than the width of the lower surface,
The pad of the first circuit pattern has a width smaller than a width of an upper surface of the first via,
The first via is disposed to surround a side surface of the pad of the first circuit pattern,
circuit board. 11. The method of claim 10,
the first circuit pattern includes a trace,
wherein the trace is in direct contact with a side of the first via;
circuit board. According to claim 1,
including a first surface treatment layer disposed on an upper surface of the pad of the first circuit pattern;
circuit board. According to claim 1,
A pitch corresponding to a distance between the centers of the plurality of pads of the first circuit pattern is 90 μm or less,
circuit board. According to claim 1,
a second insulating layer disposed under the first insulating layer; and
a protective layer disposed on a lower surface of the second insulating layer;
The second insulating layer is a second outermost insulating layer disposed on the second outermost side opposite to the first outermost side of the circuit board,
A lower surface of the protective layer is exposed to the second outermost side, constituting a second outermost surface of the circuit board,
circuit board. a first insulating layer;
a first via passing through the first insulating layer and including 1-1 vias and 1-2 vias spaced apart from each other in a width direction;
A first pad disposed on an upper surface of the 1-1 via, a second pad disposed on an upper surface of the first-2 via, and an upper surface of the first insulating layer between the first pad and the second pad a first circuit pattern including a first trace to be formed;
a second circuit pattern disposed on a lower surface of the first insulating layer and connected to a lower surface of the second via;
a first surface treatment layer disposed on the first pad and the second pad;
a first adhesive portion disposed on the first surface treatment layer;
a chip attached to the first adhesive part; and
a molding layer disposed on the upper surface of the first insulating layer and molding the chip;
The molding layer is disposed to cover the first circuit pattern while in direct contact with the upper surface of the first insulating layer,
A pitch corresponding to a distance from the center of the first pad of the first circuit pattern to the center of the second pad of the first circuit pattern is 100 μm or less,
package board. 16. The method of claim 15,
a width of the first adhesive portion is smaller than a width of the first pad and a width of the second pad;
package board. 16. The method of claim 15,
The chip includes a first chip and a second chip disposed to be spaced apart from each other in the width direction,
The first chip corresponds to a central processor (CPU),
The second chip corresponds to a graphics processor (GPU),
package board.

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