KR20220013675A - The method for manufacturing the printed circuit board - Google Patents

Abstract

A printed circuit board of an embodiment of the present invention comprises: an insulating substrate which includes a plurality of insulating layers and has a cavity formed in at least one insulating layer of the plurality of insulating layers; a first electronic device which is disposed in the cavity of the insulating substrate; and a plating layer which is disposed on a side surface of the insulating substrate. The side surface of the insulating substrate includes: a first portion on which the plating layer is disposed; and a second portion which excludes the first portion on which the plating layer is not disposed. A distance between the first electronic device and the first portion is shorter than a distance between the first electronic device and the second portion.

Description

Printed circuit board and manufacturing method thereof

The embodiment relates to a printed circuit board, and more particularly, to an electronic device embedded printed circuit board and a method of manufacturing the same.

A printed circuit board (PCB) is a printed circuit board (line pattern) formed by printing a circuit line with a conductive material such as copper on an electrically insulating board, and refers to a board immediately before mounting electronic components. In other words, it refers to a circuit board in which the mounting position of each component is determined and circuit lines connecting the components are printed and fixed on the surface of the flat panel in order to densely mount many types of electronic components on a flat plate.

In addition, recent trends in the miniaturization, simplification, and high performance of various products and components in the field of electrical and electronic industries have been remarkably shown. A method of accurately mounting is absolutely required.

As the substrate material of the printed circuit board, polyamide, polyester, polyetheramide films, etc. are mainly used because these films have very excellent thermal, electrical and mechanical properties.

An adhesive is applied to such a substrate, a metal film such as copper or aluminum is adhered, a circuit is drawn using screen printing or dry film photoresist, and a conductive metal film is etched, followed by insulation and A printed circuit board is manufactured by applying a coverlay film to protect the circuit.

SMD (Surface Mounting Devices) parts that can be surface mounted by automated equipment such as multilayer ceramic chip capacitors (MLCC), chip registers, chip tantalum capacitors, etc., in which capacitors and resistors are light and thin on such a printed circuit board. and lead parts will be installed.

On the other hand, components included in the conventional printed circuit board generate electromagnetic waves, which are not only harmful to the human body, but also cause problems in the operational reliability of other components disposed in the printed circuit board.

Accordingly, in recent years, a technology for forming an electromagnetic wave shielding layer by coating a metal such as copper or nickel on the outside of a printed circuit board has been provided. Here, the electromagnetic wave blocking layer may have a thickness of about 1.5 μm and be formed to surround the outer surface of the printed circuit board. In this case, conventionally, the electromagnetic wave blocking layer as described above is formed using a coating method such as sputtering.

However, the method for forming the electromagnetic wave shielding layer using sputtering as described above has a problem in that the deposition rate is very slow, and thus the deposition time is long.

Accordingly, there is a need for a method capable of forming a more efficient electromagnetic wave blocking layer.

The embodiment provides a printed circuit board and a method of manufacturing the same to form a plating layer for shielding electromagnetic waves by applying a plating method.

In addition, the embodiment provides a printed circuit board capable of efficiently dissipating heat generated from an electronic device mounted in the printed circuit board using a plating layer, and a method of manufacturing the same.

In addition, in the embodiment, a printed circuit board capable of preventing oxidation of the plating layer that may occur in an environment in which the printed circuit board is used by additionally forming a surface treatment layer on the plating layer, and a method for manufacturing the same.

Technical tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks not mentioned are clear to those of ordinary skill in the art to which the proposed embodiment belongs from the description below. can be understood clearly.

The printed circuit board of the embodiment includes: an insulating substrate including a plurality of insulating layers, a cavity formed in at least one insulating layer of the plurality of insulating layers; a first electronic device disposed in the cavity of the insulating substrate; and a plating layer disposed on a side surface of the insulating substrate, wherein the side surface of the insulating substrate comprises a first portion on which the plating layer is disposed, and a second portion excluding the first portion on which the plating layer is not disposed, A distance between the first electronic device and the first portion is shorter than a distance between the first electronic device and the second portion.

The plating layer may include a first portion of the side surface of the insulating substrate and a first plating layer disposed on the upper surface of the insulating substrate; and a second plating layer disposed on the first plating layer.

In addition, the first plating layer includes a first region formed on the first portion of a side surface of the insulating substrate and a second region formed on an upper surface of the insulating substrate, wherein the second plating layer includes the first region It is disposed on the first region of the plating layer.

In addition, a marking layer disposed on the second region of the first plating layer is included.

In addition, the side surface of the insulating substrate includes a plurality of corner regions, and the second portion of the side surface of the insulating substrate is a corner region having the longest distance from the electronic device among the plurality of corner regions.

In addition, the insulating substrate, a second electronic device disposed on the uppermost insulating layer of the plurality of insulating layers; and a molding layer disposed on the uppermost insulating layer and molding the second electronic device, wherein the plating layer is disposed on the plurality of insulating layers and a first portion of side surfaces of the molding layer.

On the other hand, the method of manufacturing a printed circuit board includes manufacturing an insulating substrate including a plurality of insulating layers, in which a first electronic device is embedded in a cavity formed in at least one insulating layer of the plurality of insulating layers, and passing through the insulating substrate. forming a slot and performing plating in the slot to form a plating layer, wherein the slot has an open loop shape on the insulating substrate and includes at least one bridge region, the side surface of the insulating substrate, a first portion in which the slot is formed and the plating layer is disposed; and a second portion corresponding to the bridge region and excluding the first portion in which the plating layer is not disposed, wherein the first electronic device and the first electronic device are provided. The distance between the first portions is closer than the distance between the first electronic device and the second portion, and the plating layer may include a first portion of the side surface of the insulating substrate and a first plating layer disposed on the upper surface of the insulating substrate; and a second plating layer disposed on the first plating layer.

In addition, manufacturing the insulating substrate includes manufacturing a plurality of units corresponding to the insulating substrate as a panel base, and forming the slot in each of the plurality of units, wherein the bridge region is formed from the panel base. , so that the plurality of units are not separated from each other.

In addition, the first plating layer includes a first region formed on the first portion of a side surface of the insulating substrate and a second region formed on an upper surface of the insulating substrate, wherein the second plating layer includes the first region and forming a marking layer disposed on the first area of the plating layer and disposed on the second area of the first plating layer.

In addition, the side surface of the insulating substrate includes a plurality of corner regions, and the second portion of the side surface of the insulating substrate is a corner region having the longest distance from the electronic device among the plurality of corner regions.

In an embodiment, the electromagnetic wave shielding layer formed on the outer side of the insulating substrate is formed using plating, thereby improving the reliability of the formed first plating layer. In addition, in the embodiment, by forming the first plating layer 210 formed on the outside of the insulating substrate through a plating process, it is possible to shorten the time required to form the first plating layer, thereby reducing the manufacturing cost. can In addition, in the embodiment, as the shielding layer for shielding electromagnetic waves is formed by plating, it is easy to control the thickness of the first plating layer 210 formed thereby.

In addition, in the embodiment, a bridge region in which a plating layer is not formed is formed in any one of the plurality of edge regions of the insulating substrate. That is, the side surface of the printed circuit board includes a plurality of corner regions. In addition, the slot may be formed in a region other than a corner region having the longest distance from an electronic device buried in the insulating substrate among the plurality of corner regions. According to this, in the embodiment, it is possible to minimize the bridge area as described above, and accordingly, the electromagnetic wave shielding performance can be improved. In addition, since the bridge region is formed in a region furthest from an electronic device among the corner regions, it is possible to minimize the problems of electromagnetic wave shielding performance degradation and heat dissipation performance degradation caused by the bridge region.

1 is a view showing a printed circuit board according to an embodiment.
FIG. 2 is a plan view in which a part of the printed circuit board of FIG. 1 is removed.
3 to 21 are views for explaining the manufacturing method of the printed circuit board of FIG. 1 in order of process.
22 is a view showing a printed circuit board according to another embodiment.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

However, the technical spirit of the present invention is not limited to some of the described embodiments, but may be implemented in various different forms, and within the scope of the technical spirit of the present invention, one or more of the components may be selected between the embodiments. It can be used by combining or substituted with .

In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be generally understood by those of ordinary skill in the art to which the present invention pertains, unless specifically defined and described. It may be interpreted as a meaning, and generally used terms such as terms defined in advance may be interpreted in consideration of the contextual meaning of the related art. In addition, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention.

In this specification, the singular form may also include the plural form unless otherwise specified in the phrase, and when it is described as "at least one (or one or more) of A and (and) B, C", it is combined with A, B, C It can contain one or more of all possible combinations. In addition, in describing the components of the embodiment of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

These terms are only for distinguishing the component from other components, and are not limited to the essence, order, or order of the component by the term. And, when it is described that a component is 'connected', 'coupled' or 'connected' to another component, the component is not only directly connected, coupled or connected to the other component, but also with the component It may also include a case of 'connected', 'coupled' or 'connected' due to another element between the other elements.

In addition, when it is described as being formed or disposed on "above (above) or under (below)" of each component, top (above) or under (below) is one as well as when two components are in direct contact with each other. Also includes a case in which another component as described above is formed or disposed between two components. In addition, when expressed as "upper (upper) or lower (lower)", the meaning of not only an upper direction but also a lower direction based on one component may be included.

1 is a view showing a printed circuit board according to an embodiment.

Referring to FIG. 1 , a printed circuit board may include a first insulating part, a second insulating part, and a third insulating part. The first insulating part may include a central insulating layer, the second insulating part may include an upper insulating layer disposed over the first insulating part, and the third insulating part may include a lower insulating layer disposed below the first insulating part. can do.

In addition, in an embodiment, the first insulating part constituting the central insulating layer may be composed of a single layer, or alternatively, may be composed of a plurality of layers. Also, similarly, the second insulating part disposed above the first insulating part and the second insulating part disposed below the first insulating part may also be configured as a single layer, or alternatively, may be configured as a plurality of layers.

The first insulating part includes an insulating layer in which the electronic devices 300a and 300b are buried. To this end, the first insulating part may include a first insulating layer 110 and a second insulating layer 125 . In addition, a cavity C in which the electronic device 300 is disposed may be formed in the first insulating layer 110 and the second insulating layer 125 . In this case, the first insulating part may be referred to as a core insulating part, and accordingly, the first insulating layer 110 and the second insulating layer 125 may be referred to as a core insulating layer. However, the embodiment is not limited thereto, and the first insulating layer 110 and the second insulating layer 125 may be a coreless insulating layer. In addition, although it is illustrated that the first insulating layer part in which the electronic devices 300a and 300b are buried is disposed in the first insulating layer 110 and the second insulating layer 125 , the present invention is not limited thereto, and the first insulating part has a single layer. may be composed of

The first insulating layer 110 and the second insulating layer 125 are substrates on which electric circuits capable of changing wiring are formed, and printed, wiring boards, and printed circuit boards made of an insulating material capable of forming at least one circuit pattern on the surface; All insulating substrates may be included.

The first insulating layer 110 and the second insulating layer 125 may include glass or plastic. In detail, the first insulating layer 110 and the second insulating layer 125 may include chemically strengthened/semi-tempered glass such as soda lime glass or aluminosilicate glass, or polyimide (PI). ), polyethylene terephthalate (PET), propylene glycol (PPG), reinforced or soft plastic such as polycarbonate (PC), or may include sapphire.

In this case, a plurality of circuit patterns may be disposed on the surfaces of the first insulating layer 110 and the second insulating layer 125 .

A first circuit pattern 105 may be buried under the first insulating layer 110 . A second circuit pattern 120 may be disposed on the upper surface of the first insulating layer 110 . In addition, a third circuit pattern 135 may be disposed on the upper surface of the second insulating layer 125 . At this time, when the first insulating layer 110 and the second insulating layer 125 are viewed as one insulating layer, the lower circuit pattern is buried in the insulating layer, and the upper circuit pattern is the insulating layer. It protrudes and is placed on the top. That is, in the embodiment, the first circuit pattern 105 may be buried under the first insulating layer 110 . Accordingly, in the embodiment, the thickness of the insulating layer (to be described later, 150) disposed under the first insulating layer 110 can be reduced by the thickness of the first circuit pattern 105. That is, the insulating layer is Since the circuit pattern is basically disposed while covering the circuit pattern, the thickness of the circuit pattern is determined as the basic offset thickness. On the other hand, in the embodiment, as the first circuit pattern 105 is buried under the first insulating layer 110 , the thickness of the insulating layer to be subsequently laminated under the first insulating layer 110 is 12 compared to the conventional one. It can be reduced by ~18㎛.

In addition, the first circuit pattern 105 , the second circuit pattern 120 , and the third circuit pattern 135 are wirings that transmit electrical signals, and may be formed of a metal material having high electrical conductivity. To this end, the first circuit pattern 105, the second circuit pattern 120, and the third circuit pattern 135 are gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin ( Sn), copper (Cu), and zinc (Zn) may be formed of at least one metal material. In addition, the first circuit pattern 105 , the second circuit pattern 120 , and the third circuit pattern 135 have excellent bonding strength of gold (Au), silver (Ag), platinum (Pt), titanium (Ti), and tin. It may be formed of a paste or solder paste including at least one metal material selected from (Sn), copper (Cu), and zinc (Zn). Preferably, the first circuit pattern 105 , the second circuit pattern 120 , and the third circuit pattern 135 may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

The first circuit pattern 105 , the second circuit pattern 120 , and the third circuit pattern 135 may include an additive process, a subtractive process, and a conventional printed circuit board manufacturing process. Modified Semi Additive Process (MSAP) and Semi Additive Process (SAP) methods can be used, and detailed descriptions are omitted here.

A first via 115 is formed in the first insulating layer 110 . In addition, a second via 130 is formed in the second insulating layer 125 . The first via 115 and the second via 130 electrically connect circuit patterns disposed on different layers to each other. The first via 115 may electrically connect the first circuit pattern 105 and the second circuit pattern 120 . Also, the second via 130 may electrically connect the second circuit pattern 120 and the third circuit pattern 135 .

The first via 115 and the second via 130 may penetrate only one insulating layer of the first insulating layer 110 and the second insulating layer 125 , and differently, at least one of the plurality of insulating layers. It may be formed while passing through the two insulating layers in common. Accordingly, the first via 115 and the second via 130 electrically connect circuit patterns disposed on surfaces of different insulating layers to each other.

The first via 115 and the second via 130 are formed of a conductive material inside a through hole (not shown) penetrating at least one of the first insulating layer 110 and the second insulating layer 125 . It can be formed by filling.

The through hole may be formed by any one of machining methods, including mechanical, laser, and chemical machining. When the through hole is formed by machining, methods such as milling, drilling, and routing can be used, and when formed by laser processing, UV or CO ₂ laser method is used. In the case of being formed by chemical processing, at least one insulating layer among the plurality of insulating layers may be opened by using a chemical containing aminosilane, ketones, or the like.

On the other hand, the processing by the laser is a cutting method that takes a desired shape by concentrating optical energy on the surface to melt and evaporate a part of the material. Complex formation by a computer program can be easily processed. Even difficult composite materials can be machined.

In addition, the processing by the laser can have a cutting diameter of at least 0.005 mm, and has a wide advantage in a range of possible thicknesses.

As the laser processing drill, it is preferable to use a YAG (Yttrium Aluminum Garnet) laser, a CO ₂ laser, or an ultraviolet (UV) laser. The YAG laser is a laser that can process both the copper foil layer and the insulating layer, and the CO ₂ laser is a laser that can process only the insulating layer.

When the through hole is formed, the first via 115 and the second via 130 may be formed by filling the inside of the through hole with a conductive material. The metal material forming the first via 115 and the second via 130 is selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). The conductive material filling may be any one of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjetting, and dispensing, or any one of them. Combination methods may be used.

Electronic devices 300a and 300b may be embedded in the cavity C formed in common in the first insulating layer 110 and the second insulating layer 125 . That is, the first electronic device 300a and the second electronic device 300b may be embedded within the cavity C at a predetermined distance from each other. At this time, although it is illustrated that the two first electronic elements 300a and the second electronic elements 300b are built in the cavity C in the drawing, the present invention is not limited thereto. For example, the number of electronic devices embedded in the cavity C may decrease or increase differently compared to FIG. 1 .

The electronic devices 300a and 300b may be electronic components such as chips, which may be divided into active devices and passive devices. In addition, the active element is an element that actively uses a non-linear portion, and the passive element refers to an element that does not use the non-linear characteristic even though both linear and non-linear characteristics exist. In addition, the passive element may include a transistor, an IC semiconductor chip, and the like, and the passive element may include a capacitor, a resistor, an inductor, and the like. The passive element is mounted on a general printed circuit board to increase a signal processing speed of a semiconductor chip, which is an active element, or to perform a filtering function.

The electronic devices 300a and 300b may vary depending on the application to which the printed circuit board is applied. For example, when applied to a NAND flash memory product applied to a smart phone, the electronic devices 300a and 300b) may be a control element component.

Terminals 310a and 310b may be formed on lower surfaces of the electronic devices 300a and 300b, respectively. In this case, the lower surfaces of the terminals 310a and 310b may be disposed on the same plane as the lower surface of the first insulating layer 110 . A lower surface of the terminals 310a and 310b may be disposed on the same plane as a lower surface of the first circuit pattern 105 . Meanwhile, top surfaces of the electronic devices 300a and 300b may be disposed on the same plane as the top surface of the second insulating layer 125 . Preferably, upper surfaces of the electronic devices 300a and 300b may be disposed lower than the upper surfaces of the second insulating layer 125 . That is, the cavity C may be the same as the thickness of the electronic devices 300a and 300b, and may have a thickness greater than the thickness of the electronic devices 300a and 300b to improve reliability. Preferably, the cavity C may have a thickness greater than the thickness of the electronic devices 300a and 300b by about 10 μm. Accordingly, upper surfaces of the electronic devices 300a and 300b may be positioned lower than the upper surfaces of the second insulating layer 125 . In addition, the width of the cavity C may be greater than the total width of the electronic devices 300a and 300b for stable arrangement of the electronic devices 300a and 300b.

Here, the first insulating part is not a structure in which the first circuit pattern 105 protrudes to the lower surface of the first insulating layer 110, but the first insulating layer ( 110) to have a buried structure in the lower part. This may be achieved by a differentiated manufacturing process in the embodiment rather than a general printed circuit board manufacturing process. This will be described in more detail below.

According to an embodiment, the printed circuit board includes a first insulating part in which a cavity in which an electronic device is disposed is formed. Then, the circuit pattern or the pad is buried in the first insulating portion to be disposed. Accordingly, as the circuit pattern or pad is buried in the first insulating part and disposed, the thickness of the printed circuit board can be reduced by the thickness of the circuit pattern compared to the related art, and design freedom can be improved. In addition, since the first insulating part uses a prepreg including glass fiber, it is possible to minimize the occurrence of panel cracking or warping that occurs when a thin substrate is manufactured.

A second insulating part may be disposed on the first insulating part, and a third insulating part may be disposed below the first insulating part. In this case, in an embodiment, the second insulating part may be composed of a single insulating layer, and the third insulating part may be composed of a plurality of insulating layers.

In this case, the insulating layer constituting the second insulating part, the partial insulating layer constituting the third insulating part, and the insulating layer constituting the first insulating part may all be made of different insulating materials. That is, as described above, the first insulating layer 110 and the second insulating layer 125 of the first insulating part may be formed of a prepreg including glass fibers.

Alternatively, the third insulating layer 140 constituting the second insulating part may be made of resin coated Cu (RCC). In this case, the third insulating layer 140 is disposed on the second insulating layer 125 and also in the cavity C formed in the second insulating layer 125 and the first insulating layer 110 . That is, the third insulating layer 140 may be disposed on the second insulating layer 125 to have a predetermined thickness while filling the cavity (C).

Here, the meaning that the third insulating layer 140 is disposed on the second insulating layer 125 while filling the cavity C means that the third insulating layer is disposed below the first insulating part as the center. It means that the second insulating part is laminated before the part.

In other words, the stacking of the insulating material in the cavity C means that the second insulating part is positioned in a direction.

A fourth circuit pattern 145 may be disposed on the upper surface of the third insulating layer 140 . Also, a third via may be disposed on the third insulating layer 140 while passing through the third insulating layer 140 . The third via may electrically connect the third circuit pattern 135 disposed on the second insulating layer 125 and the fourth circuit pattern 145 disposed on the third insulating layer 140 .

In addition, a first external insulating layer 170 may be disposed on the third insulating layer 140 .

Meanwhile, a third insulating part is disposed under the first insulating part. The third insulating part has a structure of a plurality of insulating layers differently from the second insulating part. Accordingly, in the embodiment, the electronic device 300a, 300b may have a symmetrical structure with respect to the first insulating portion disposed thereon, or may have an asymmetrical structure differently.

The third insulating part may include a fourth insulating layer 150 disposed under the first insulating layer 110 and a second external insulating layer 170 disposed under the fourth insulating layer 150 .

In this case, the fourth insulating layer 150 and the second external insulating layer 170 may be formed of the same insulating material, or may be formed of different insulating materials.

Preferably, the fourth insulating layer 150 may be formed of an insulating material different from that of the second external insulating layer 170 .

The second external insulating layer 170 may be formed of the same insulating material as the first insulating layer 110 and the second insulating layer 125 .

The second outer insulating layer 170 may include glass fiber or plastic. In detail, the second external insulating layer 170 includes chemically strengthened/semi-tempered glass such as soda lime glass or aluminosilicate glass, or includes polyimide (PI), polyethylene terephthalate (polyethylene), etc. Reinforced or soft plastic such as terephthalate, PET), propylene glycol (PPG), polycarbonate (PC), or the like, or sapphire may be included.

In addition, the fourth insulating layer 150 may be formed of a film-type resin. Preferably, the fourth insulating layer 150 may be formed of a film-type prepreg. Preferably, the fourth insulating layer 150 may be formed of Aginomoto Build-up Film (ABF) or Photo Imagable Dielectric (PID), which is a photosensitive insulating material.

The fourth insulating layer 150 has a predetermined thickness and is disposed under the first insulating layer 110 . In this case, the circuit pattern protruding through the lower surface does not exist in the first insulating layer 110 . That is, the first circuit pattern 105 is formed to be buried under the first insulating layer 110 . Accordingly, the fourth insulating layer 150 may be formed without considering the thickness of the circuit pattern. That is, the general insulating layer is disposed for stable interlayer insulation while covering the circuit pattern, and for this, the final thickness may be determined based on the thickness of the circuit pattern. For example, in the case of the third insulating layer 140 , the thickness should be determined in consideration of the thickness of the third circuit pattern 135 disposed on the second insulating layer 125 . That is, when the thickness of the third circuit pattern 135 is 12 μm, the thickness of the third insulating layer 140 may be 20 μm. Also, when the thickness of the third insulating layer 140 is 10 μm, the thickness of the third insulating layer 140 may be 15 μm. On the other hand, the fourth insulating layer 150 may be formed without considering the thickness of the circuit pattern, and accordingly, it may be formed even with a thin thickness of about 10 μm.

That is, the thickness of the fourth insulating layer 150 is the first insulating layer 110 , the second insulating layer 125 , the third insulating layer 140 , the first external insulating layer 170 , and the second external insulating layer. Each of the branches of 170 is smaller than the thickness.

A fifth circuit pattern 160 may be disposed on a lower surface of the fourth insulating layer 150 . In addition, a fourth via 155a and a fifth via 155b may be included in the fourth insulating layer 150 .

In this case, the fifth circuit pattern 160 formed on the lower surface of the fourth insulating layer 150 may have a line width different from that of other circuit patterns. Preferably, the fifth circuit pattern 160 may have a line width smaller than that of circuit patterns disposed on other layers. Also, the fifth circuit pattern 160 may have a smaller pitch than circuit patterns disposed on other layers. This may be achieved by the physical properties of the fifth insulating layer 165 .

Meanwhile, a fourth via 155a and a fifth via 155b are formed in the fourth insulating layer 150 . The fourth via 155a is a via directly connected to the terminals 310a and 310b of the electronic devices 300a and 300b , and the fifth insulating layer 165 is a via connected to the first circuit pattern 105 . Preferably, the fourth via 155a may overlap the electronic devices 300a and 300b in the vertical direction, and the fifth via 155b may not overlap the electronic device 300 in the vertical direction. In addition, the fourth via 155a and the fifth via 155b may have different widths. That is, the width of the via formed in the fourth insulating layer 150 may be smaller than that of the via formed in other layers. In this case, when all vias disposed in the fourth insulating layer 150 are formed as small vias, a problem may occur in alignment with vias disposed in other layers. On the other hand, when all the vias disposed on the fourth insulating layer 150 are formed to have the same width as the vias disposed on other layers, reliability of the vias connected to the terminals 310a and 310b of the electronic device 300 . This can fall. Accordingly, in the embodiment, the fourth via 155a and the fifth via 155b disposed in the same layer are formed to have different widths according to their respective functions. That is, as the fifth via 155b is connected to the vias of another layer, the fifth via 155b may have the same width as the vias of the other layer. Accordingly, the fifth via 155b may have a minimum width of 40 μm. Preferably, the fifth via 155b may have a width between 40 μm and 100 μm.

Meanwhile, as the fourth via 155a is directly connected to the terminals 310a and 310b of the electronic devices 300a and 300b, it is formed as a small via. Preferably, the fourth via 155a has a smaller width than the fifth via 155b. For example, the fourth via 155a may have a width of 10 μm to 35 μm. For example, the fourth via 155a may have a width of 20 μm to 25 μm.

Meanwhile, a protective layer 190 may be disposed on the second external insulating layer 170 constituting the third insulating part.

The protective layer 190 may be formed of at least one layer using any one or more of Solder Resist (SR), oxide, and Au.

The protective layer 190 may have an opening exposing the circuit pattern disposed on the lower surface of the second external insulating layer 170 while protecting the lower surface of the second external insulating layer 170 . In addition, an adhesive member (not shown) such as a solder ball may be disposed in the opening, and thus may be attached to an electronic product (eg, a portable terminal) in the form of a package.

Meanwhile, a protective layer may not be disposed on the first external insulating layer 170 constituting the second insulating part in the embodiment. However, a shielding layer for electromagnetic wave shielding may be disposed on the first external insulating layer 170 in the embodiment.

In an embodiment, the shielding layer may include a plating layer and a coating layer. The printed layer may be a solder resist coating layer.

Hereinafter, the entire insulating layer stacked structure including the first insulating part, the second insulating part, and the third insulating part as described above will be described as one insulating substrate.

That is, the insulating substrate in the embodiment has a stacked structure of a plurality of insulating layers, a cavity is formed in at least one insulating layer of the plurality of insulating layers, and the electronic devices 300a and 300b are formed in the cavity. can be placed.

And, the printed circuit board in the embodiment includes a plating layer disposed on the upper surface and the outer surface of the insulating substrate.

Specifically, the printed circuit board includes the first plating layer 210 disposed on the upper surface and the outer surface of the insulating substrate. The first plating layer 210 may include copper, but is not limited thereto. The first plating layer 210 may be a plating layer formed by performing electrolytic plating or electroless plating on the upper and outer surfaces of the insulating substrate. The first plating layer 210 may have a thickness in the range of 1 μm to 12 μm, and may be respectively disposed on the side surface and the top surface of the insulating substrate. Accordingly, the first plating layer 210 may be formed on outer surfaces of all insulating layers constituting the insulating substrate. In addition, the first plating layer 210 may also be disposed on the upper surface of the uppermost insulating layer (the first external insulating layer 170 in FIG. 1 ) among the insulating layers constituting the insulating substrate.

The first plating layer 210 may be a shielding layer that shields electromagnetic waves generated from the electronic devices 300a and 300b disposed in the insulating substrate.

In an embodiment, the electromagnetic wave shielding layer formed on the outer side of the insulating substrate is formed using plating, and thus, reliability of the formed first plating layer 210 can be improved. In addition, in the embodiment, by forming the first plating layer 210 formed on the outside of the insulating substrate through a plating process, the time required to form the first plating layer 210 can be shortened, and thus the manufacturing cost can save In addition, in the embodiment, as the shielding layer for shielding electromagnetic waves is formed by plating, it is easy to control the thickness of the first plating layer 210 formed thereby.

Meanwhile, in the embodiment, a second plating layer 220 disposed on the first plating layer 210 is included. The second plating layer 220 may be a surface treatment layer for preventing reliability problems such as oxidation of the first plating layer 210 . The second plating layer 220 may be formed as a single layer, or alternatively, may be formed as a plurality of layers. Preferably, the second plating layer 220 may have a layer structure of two or more layers.

In an embodiment, the second plating layer 220 is disposed on the first plating layer 210 and includes a 2-1 plating layer including nickel (Ni), and disposed on the 2-1 plating layer and including gold and a second 2-2 plating layer.

In another embodiment, the second plating layer 220 is disposed on the first plating layer 210 and includes a 2-1 plating layer including nickel (Ni), and palladium (Pd) disposed on the 2-1 plating layer. ) may include a 2-2 second plating layer containing.

In another embodiment, the second plating layer 220 is disposed on the first plating layer 210 and includes a 2-1 plating layer including nickel (Ni), and palladium ( It may include a 2-2 plating layer including Pd) and a 2-3 plating layer disposed on the 2-2 plating layer and including gold (Au).

The second plating layer 220 may be formed through an electrolytic plating or an electroless plating method in the same manner as the first plating layer 210 .

The second plating layer 220 may be formed on only a portion of the surface of the first plating layer 210 .

For example, the first plating layer 210 may include a first region disposed on a side surface of the insulating substrate and a second region disposed on an upper surface of the insulating substrate.

In addition, the second plating layer 220 may be formed on the first region of the first plating layer 210 .

Meanwhile, the printed circuit board of the embodiment may further include a marking layer 230 . The marking layer 230 may be formed on the first plating layer 210 . Preferably, the marking layer 230 may be formed on the second region of the first plating layer 210 . The marking layer 230 may be a marking layer for mutually distinguishing a plurality of units corresponding to the printed circuit board. The marking layer 230 may include solder resist.

That is, in the embodiment, when manufacturing a printed circuit board, not only one printed circuit board is manufactured, but a panel base including a plurality of units is manufactured. In addition, the marking layer 230 may be a marking layer formed of solder resist ink to distinguish each unit in the panel base.

In other words, the printed circuit board according to the embodiment includes an insulating substrate having a stacked structure of a plurality of insulating layers and having electronic devices 300a and 300b built therein.

And, in the printed circuit board in the embodiment, the first plating layer 210 is formed on the outer surface, preferably the outer surface and the upper surface of the insulating substrate. The first plating layer 210 may be formed by plating the outer and upper surfaces of the insulating substrate. That is, the first plating layer 210 may include a first region formed on the side surface of the insulating substrate and a second region formed on the upper surface of the insulating substrate.

In addition, the printed circuit board according to the embodiment may include the second plating layer 220 disposed on the first region of the first plating layer 210 . The second plating layer 220 may be a surface treatment layer for preventing oxidation of the first plating layer 210 . The second plating layer 220 may be formed to have a layer structure of any one of nickel/gold, nickel/palladium, and nickel/palladium/gold.

In addition, the printed circuit board of the embodiment may include a marking layer 230 disposed on the second region of the first plating layer 210 . The marking layer 230 may be a marking layer for distinguishing a plurality of units from the panel base, and may be formed of, for example, solder resist ink.

FIG. 2 is a plan view in which a part of the printed circuit board of FIG. 1 is removed.

Referring to FIG. 2 , the printed circuit board includes a first plating layer 210 disposed on a side surface of the insulating substrate. The first plating layer 210 is not disposed on the entire area of the side surface of the insulating substrate, but includes an exposed portion exposing a partial area.

The exposed portion may be a bridge region B that prevents the unit from being separated from the panel base in the process of forming the first plating layer 210 on each unit on a panel base basis. That is, in the embodiment, in order to increase productivity, the first plating layer 210 is formed by simultaneously performing a plating process for a plurality of units on a panel base basis.

At this time, if the bridge region B does not exist, each unit will be separated from each other in the panel base, and accordingly, the process of forming the first plating layer 210 for each unit must be performed separately. , there is a difficulty in the manufacturing process accordingly. Accordingly, in the embodiment, each unit is not separated from each other in the panel base unit based on the bridge region B, and accordingly, the forming process of the first plating layer 210 is performed for all units included in the panel base. allow them to proceed simultaneously.

Meanwhile, the first plating layer 210 may be a shielding layer for shielding electromagnetic waves. Furthermore, the first plating layer 210 may be used as a heat dissipation layer that radiates heat generated in the electronic devices 300a and 300b to the outside.

In addition, the closer the distance of the first plating layer 210 to the electronic devices 300a and 300b embedded in the insulating substrate, the better the shielding performance or heat dissipation performance.

Accordingly, in the embodiment, when determining the bridge region B, a region of the side surface of the insulating substrate that is the farthest from the electronic devices 300a and 300b disposed in the insulating substrate is determined as the bridge region B. do it For example, the electronic devices 300a and 300b are disposed in the insulating substrate. In this case, the electronic devices 300a and 300b may not be precisely disposed in the central region of the insulating substrate, but may be disposed to be biased in a specific direction.

For example, in FIG. 2 , it may have a structure in which three electronic devices 300 are disposed in an insulating substrate. That is, the device arrangement region 320 in which the three electronic devices 300 are disposed is included in the insulating substrate.

In this case, the device arrangement region 320 may be formed to be biased toward the upper right, lower left, and lower right sides of the insulating substrate, respectively. Accordingly, a side area corresponding to the upper left side of the side surfaces of the insulating substrate may be farthest apart from the device arrangement area 320 compared to other side areas.

Accordingly, in the embodiment, a side area corresponding to the upper left side farthest from the device arrangement area 320 among the side surfaces of the insulating substrate is determined as the bridge area B, and accordingly the determined bridge area B) In this case, the first plating layer 210 may not be formed.

At this time, in the embodiment, when determining the bridge region B, any one of the corner regions among the side surfaces of the insulating substrate is formed as the bridge region B. That is, due to characteristics of the plating process, the plating process may not be smoothly performed in the corner region. In addition, it may take more time to form the first plating layer 210 in the corner region than to form the first plating layer 210 in the other side regions.

In other words, the side area of the insulating substrate may include four corner areas. The corner area may be an area where different side surfaces meet each other. For example, the insulating substrate may have a quadrangular planar shape, and thus may include four side surfaces. In addition, the side area of the insulating substrate may include four corner areas where the four side surfaces meet each other.

In this case, referring to FIG. 2 , a corner region disposed on the lower left side of the four corner regions may be spaced apart from the device arrangement region 320 by a first distance L1 . Also, among the four corner areas, the lower right corner area may be spaced apart from the device arrangement area 320 by a second distance L2 . In addition, among the four corner regions, an upper right corner region may be spaced apart from the device arrangement region 320 by a third distance L3 . Also, among the four corner areas, the upper left corner area may be spaced apart from the device arrangement area 320 by a fourth distance. For example, the corner region disposed on the left layer may be spaced apart from a portion of the device arrangement region 320 by a 4-1 th distance L4-1, and may be spaced apart from another portion of the device arrangement region 320 by a fourth-th portion. It may be spaced apart by 2 distances (L4-2). In this case, each of the 4-1 th distance L4-1 and the 4-2 th distance L4-2 may be greater than the first distance L1, the second distance L2, and the third distance L3. . Accordingly, in the embodiment, in the structure shown in FIG. 2 , the upper-left corner region farthest from the device arrangement region 320 is determined as the bridge region B in the structure shown in FIG. 2 . Accordingly, in the embodiment, it is possible to solve the problem of deterioration of electromagnetic wave shielding performance occurring in forming the bridge region B, and furthermore, it is possible to improve the heat dissipation performance.

Meanwhile, in the embodiment, the first plating layer 210 is not disposed in at least a portion corresponding to the bridge region B on the side surface of the insulating substrate. However, the first plating layer 210 disposed on the upper surface of the insulating substrate may be formed over the entire area of the upper surface of the insulating substrate.

Hereinafter, a manufacturing process of the printed circuit board shown in FIG. 1 will be described. The method of manufacturing a printed circuit board in the embodiment includes a first process for having a structure such that a first circuit pattern is buried in the first insulating layer 110, and the electronic devices 300a and 300b in the first insulating part. It may include a second process of arranging, a third process of stacking the second and third insulating parts on top and bottom of the first insulating part, respectively, and a fourth process of forming a plating layer.

3 to 21 are views for explaining the manufacturing method of the printed circuit board of FIG. 1 in order of process.

Referring to FIG. 3 , first, a carrier board CB for manufacturing the first insulating part is prepared. The carrier board CB may be a substrate that is a basis for manufacturing a printed circuit board. The carrier board CB may have a structure in which the metal layers 20 are formed on both surfaces around the support substrate 10 .

The carrier board CB is a general support substrate and may use a copper clad laminate (CCL).

Meanwhile, a surface treatment may be performed on the surface of the metal layer 20 of the carrier board CB to facilitate separation from the first insulating part later.

Next, referring to FIG. 4 , a first circuit pattern 105 is formed on the carrier board CB. The first circuit patterns 105 may be respectively formed on both surfaces of the carrier board CB.

The first circuit pattern 105 may be formed by plating a metal material on the metal layer 20 using the metal layer 20 as a seed layer. Alternatively, the first circuit pattern 105 may be formed by forming a plating layer (not shown) on the metal layer 20 and etching the formed plating layer.

The first circuit pattern 105 may include at least one metal selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). It may be formed of a material. In addition, the first circuit pattern 105 is selected from among gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding strength. It may be formed of a paste including at least one metal material or a solder paste. Preferably, the first circuit pattern 105 may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

Next, referring to FIG. 5 , a first insulating layer 110 is formed on the metal layer 20 on which the first circuit pattern 105 is formed. In this case, a copper foil layer may be present on the first insulating layer 110 .

The first insulating layer 110 may be formed of a prepreg including glass fiber.

Preferably, the first insulating layer 110 may include glass or plastic. In detail, the first insulating layer 110 may include chemically strengthened/semi-tempered glass such as soda lime glass or aluminosilicate glass, polyimide (PI), or polyethylene terephthalate. , PET), propylene glycol (PPG), reinforced or soft plastic such as polycarbonate (PC), or may include sapphire.

In addition, a first via 115 may be formed in the first insulating layer 110 .

The first via 115 may be formed by filling an inside of a through hole (not shown) penetrating the first insulating layer 110 with a conductive material. The through hole may be formed by any one of machining methods, including mechanical, laser, and chemical machining. When the through hole is formed by machining, methods such as milling, drilling, and routing can be used, and when formed by laser processing, UV or CO ₂ laser method is used. In the case of being formed by chemical processing, at least one insulating layer among the plurality of insulating layers may be opened by using a chemical containing aminosilane, ketones, or the like.

On the other hand, the processing by the laser is a cutting method that takes a desired shape by concentrating optical energy on the surface to melt and evaporate a part of the material. Complex formation by a computer program can be easily processed. Even difficult composite materials can be machined.

In addition, the processing by the laser can have a cutting diameter of at least 0.005 mm, and has a wide advantage in a range of possible thicknesses.

As the laser processing drill, it is preferable to use a YAG (Yttrium Aluminum Garnet) laser, a CO ₂ laser, or an ultraviolet (UV) laser. The YAG laser is a laser that can process both the copper foil layer and the insulating layer, and the CO ₂ laser is a laser that can process only the insulating layer.

When the through hole is formed, the first via 115 may be formed by filling the inside of the through hole with a conductive material. The metal material forming the first via 115 may be any one material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). In addition, the conductive material filling may use any one or a combination of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjetting and dispensing. .

Next, when the first via 115 is formed, a second circuit pattern 120 may be formed on the upper surface of the first insulating layer 110 .

In this case, the process of forming the first insulating layer 110 , the first via 115 , and the second circuit pattern 120 may be simultaneously performed on both surfaces of the carrier board CB.

Next, referring to FIG. 6 , a second insulating layer 125 is stacked on the first insulating layer 110 . Then, a second via 120 is formed in the second insulating layer 125 . In addition, a third circuit pattern 135 is formed on the upper surface of the second insulating layer 125 . In this case, the second insulating layer 125 may be formed of a prepreg including the same glass fiber as the first insulating layer 110 .

In this case, the process of forming the second insulating layer 125 , the second via 120 , and the third circuit pattern 135 may be simultaneously performed on both surfaces of the carrier board CB.

Next, referring to FIG. 7 , a process of separating the first insulating parts respectively formed on the upper part and the lower part from the carrier board CB may be performed. Accordingly, in the embodiment, the plurality of first insulating parts may be simultaneously manufactured in one process. Also, according to an embodiment, the first circuit pattern 105 may be buried under the first insulating layer 110 . A second circuit pattern 120 may be disposed on the upper surface of the first insulating layer 110 . In addition, a third circuit pattern 135 may be disposed on the upper surface of the second insulating layer 125 . At this time, when the first insulating layer 110 and the second insulating layer 125 are viewed as one insulating layer, the lower circuit pattern is buried in the insulating layer, and the upper circuit pattern is the insulating layer. It protrudes and is placed on the top. That is, in the related art, both the circuit patterns disposed on the upper and lower portions protrude from the upper and lower surfaces of the insulating layer. On the contrary, in the embodiment, the first circuit pattern 105 may be buried under the first insulating layer 110 . Accordingly, in the embodiment, the thickness of the fourth insulating layer 150 disposed under the first insulating layer 110 can be reduced by the thickness of the first circuit pattern 105 . That is, since the insulating layer is basically disposed while covering the circuit pattern, the thickness of the circuit pattern is determined as the basic offset thickness. On the other hand, in the embodiment, as the first circuit pattern 105 is buried under the first insulating layer 110 , the thickness of the insulating layer to be subsequently laminated under the first insulating layer 110 is 12 compared to the conventional one. It can be reduced by ~18㎛.

When the first insulating part is manufactured, a cavity C may be formed in the first insulating part. The cavity C may be formed to pass through the first insulating layer 110 and the second insulating layer 125 in common. That is, the cavity C may be the same as the thickness of the electronic device 300 , and may have a thickness greater than the thickness of the electronic devices 300a and 300b to improve reliability. Preferably, the cavity C may have a thickness greater than the thickness of the electronic devices 300a and 300b by about 10 μm. Accordingly, the upper surface of the electronic device 300 may be positioned lower than the upper surface of the second insulating layer 125 . In addition, the width of the cavity C may be greater than the width of the electronic devices 300a and 300b for stable arrangement of the electronic device 300 . The cavity C may be formed by any one of machining methods, including mechanical, laser, and chemical processing. When the through hole is formed by machining, methods such as milling, drilling, and routing can be used, and when formed by laser processing, UV or CO ₂ laser method is used. In the case of being formed by chemical processing, the first insulating layer 110 and the second insulating layer 125 may be opened by using a chemical containing aminosilane, ketones, or the like.

Next, referring to FIG. 8 , a film layer A is formed on the lower surface of the first insulating layer 110 . The film layer (A) is attached to the lower surface of the first insulating layer 110, and thus may be disposed to cover the lower portion of the cavity (C). The film layer (A) may be disposed to cover one surface of the cavity (C) in order to place and fix the electronic device 300 in the cavity (C). The film layer (A) may use a polyimide film, but is not limited thereto.

Preferably, the film layer (A) may be attached to a portion having a relatively large width among the upper and lower portions of the cavity (C). That is, the upper portion of the cavity (C) has a first width (W1), the lower portion of the cavity (C) has a second width (W2) greater than the first width (W1), thus the film layer ( A) closes the lower portion of the cavity C having a large width and may be attached to the lower surface of the first insulating layer 110 .

Next, referring to FIG. 9 , electronic devices 300a and 300b are attached on the film layer A exposed through one surface of the cavity C. As shown in FIG. The electronic devices 300a and 300b may be electronic components such as chips, which may be divided into active devices and passive devices.

The electronic devices 300a and 300b may vary depending on the application to which the printed circuit board is applied. For example, when applied to a NAND flash memory product applied to a smart phone, the electronic devices 300a and 300b) may be a control element component.

Terminals 310a and 310b may be formed on lower surfaces of the electronic devices 300a and 300b. In this case, the lower surfaces of the terminals 310a and 310b may be disposed on the same plane as the lower surface of the first insulating layer 110 . A lower surface of the terminals 310a and 310b may be disposed on the same plane as a lower surface of the first circuit pattern 105 . Meanwhile, top surfaces of the electronic devices 300a and 300b may be disposed on the same plane as the top surface of the second insulating layer 125 . Preferably, upper surfaces of the electronic devices 300a and 300b may be disposed lower than the upper surfaces of the second insulating layer 125 . That is, the cavity C may be the same as the thickness of the electronic devices 300a and 300b, and may have a thickness greater than the thickness of the electronic devices 300a and 300b to improve reliability. Preferably, the cavity C may have a thickness greater than the thickness of the electronic devices 300a and 300b by about 10 μm. Accordingly, upper surfaces of the electronic devices 300a and 300b may be positioned lower than the upper surfaces of the second insulating layer 125 . In addition, the width of the cavity C may be greater than the width of the electronic devices 300a and 300b for stable arrangement of the electronic devices 300a and 300b.

However, the embodiment is not limited thereto, and the electronic devices 300a and 300b may be attached on the film layer A so that the terminals 310a and 310b face upward. Here, the important thing is that the film layer (A) in this embodiment is disposed while closing one surface of the cavity (C) having a relatively large width, and on the other surface of the cavity (C) having a relatively small width. The insulating material filling the cavity (C) is laminated.

Next, referring to FIG. 10 , a second insulating part is formed on the first insulating part. That is, when the disposition process of the electronic devices 300a and 300b is completed, the third insulating layer 140 is formed on the second insulating layer 125 . The third insulating layer 140 may be made of resin coated Cu (RCC). In this case, the third insulating layer 140 is disposed on the second insulating layer 125 and also in the cavity C formed in the second insulating layer 125 and the first insulating layer 110 . That is, the third insulating layer 140 may be disposed on the second insulating layer 125 to have a predetermined thickness while filling the cavity (C).

That is, as described above, the third insulating layer 140 should be disposed on the second insulating layer 125 while stably filling the cavity C and having a uniform thickness. In this case, a predetermined curve may be formed on the upper surface of the third insulating layer 140 according to the area of the cavity C. As shown in FIG. This is because the thickness of the third insulating layer 140 in the region where the cavity C exists is different from that in the region other than that. Accordingly, in the embodiment, the third insulating layer 140 is formed in the RCC type as described above to solve the above problems and to manufacture a reliable substrate.

In addition, a coating layer 141 coated with copper may be formed on the third insulating layer 140 . The coating layer 141 may be a metal layer for forming the fourth circuit pattern 145 later.

Next, as shown in FIG. 11 , when the formation of the third insulating layer 140 is completed, the film layer A attached under the second insulating layer 125 is removed.

Next, referring to FIG. 12 , a fourth insulating layer 150 is formed under the first insulating layer 110 . In this case, the fourth insulating layer 150 may be formed of an insulating material different from that of the first insulating layer 110 , the second insulating layer 125 , and the third insulating layer 140 . Preferably, the fourth insulating layer 150 may be formed of a film-type resin. Preferably, the fourth insulating layer 150 may be formed of a film-type prepreg. Preferably, the fourth insulating layer 150 may be formed of Aginomoto Build-up Film (ABF) or Photo Imagable Dielectric (PID), which is a photosensitive insulating material.

The fourth insulating layer 150 has a predetermined thickness and is disposed under the first insulating layer 110 . In this case, the circuit pattern protruding through the lower surface does not exist in the first insulating layer 110 . That is, the first circuit pattern 105 is formed to be buried under the first insulating layer 110 . Accordingly, the fourth insulating layer 150 may be formed without considering the thickness of the circuit pattern. That is, the general insulating layer is disposed for stable interlayer insulation while covering the circuit pattern, and for this, the final thickness may be determined based on the thickness of the circuit pattern. For example, in the case of the third insulating layer 140 , the thickness should be determined in consideration of the thickness of the third circuit pattern 135 disposed on the second insulating layer 125 . That is, when the thickness of the third circuit pattern 135 is 12 μm, the thickness of the third insulating layer 140 may be 20 μm. Also, when the thickness of the third insulating layer 140 is 10 μm, the thickness of the third insulating layer 140 may be 15 μm. On the other hand, the fourth insulating layer 150 may be formed without considering the thickness of the circuit pattern, and accordingly, it may be formed even with a thin thickness of about 10 μm.

That is, the thickness of the fourth insulating layer 150 may be smaller than the respective thicknesses of the first insulating layer 110 , the second insulating layer 125 , and the third insulating layer 140 .

Next, the fifth circuit pattern 160 may be formed on the lower surface of the fourth insulating layer 150 . Also, a fourth via 155a and a fifth via 155b may be formed in the fourth insulating layer 150 , respectively.

In this case, the fifth circuit pattern 160 formed on the lower surface of the fourth insulating layer 150 may have a line width different from that of other circuit patterns. Preferably, the fifth circuit pattern 160 may have a line width smaller than that of circuit patterns disposed on other layers. Also, the fifth circuit pattern 160 may have a smaller pitch than circuit patterns disposed on other layers. This may be achieved by the physical properties of the fifth insulating layer 165 .

Meanwhile, a fourth via 155a and a fifth via 155b are formed in the fourth insulating layer 150 . The fourth via 155a is a via directly connected to the terminals 310a and 310b of the electronic devices 300a and 300b , and the fifth via 155b is a via connected to the first circuit pattern 105 . Preferably, the fourth via 155a may overlap the electronic devices 300a and 300b in the vertical direction, and the fifth via 155b may not overlap the electronic devices 300a and 300b in the vertical direction. In addition, the fourth via 155a and the fifth via 155b may have different widths. That is, the width of the via formed in the fourth insulating layer 150 may be smaller than that of the via formed in other layers. In this case, when all vias disposed in the fourth insulating layer 150 are formed as small vias, a problem may occur in alignment with vias disposed in other layers. On the other hand, when all the vias disposed on the fourth insulating layer 150 are formed to have the same width as the vias disposed on other layers, the reliability of the vias connected to the terminals 310 of the electronic device 300 is deteriorated. can Accordingly, in the embodiment, the fourth via 155a and the fifth via 155b disposed in the same layer are formed to have different widths according to their respective functions. That is, as the fifth via 155b is connected to the vias of another layer, the fifth via 155b may have the same width as the vias of the other layer. For example, the fifth via 155b may have a minimum width of 40 μm. Preferably, the fifth via 155b may have a width between 40 μm and 100 μm.

Meanwhile, as the fourth via 155a is directly connected to the terminals 310a and 310b of the electronic devices 300a and 300b, it is formed as a small via. Preferably, the fourth via 155a has a smaller width than the fifth via 155b. For example, the fourth via 155a may have a width of 10 μm to 35 μm. For example, the fourth via 155a may have a width of 20 μm to 25 μm.

Next, referring to FIG. 13 , first and second external insulating layers 170 are stacked above the third insulating layer 140 and below the fourth insulating layer 150 , respectively. In this case, a metal layer 171 may be formed on the surfaces of the first and second external insulating layers 170 .

Next, referring to FIG. 14 , a process of forming the first and second external insulating layers 170 and the sixth via 180 may be performed. In addition, a process of forming the external circuit pattern 175 on the surface of the second external insulating layer 170 may be performed using the metal layer 171 .

Next, referring to FIG. 15 , a process of forming the protective layer 190 on the second external insulating layer 170 may be performed.

The protective layer 220 may be formed of at least one layer using any one or more of Solder Resist (SR), oxide, and Au.

At this time, as shown in FIG. 16 , the printed circuit board may be manufactured in units of a panel base. For example, the panel base 100A includes a plurality of units 100-1 and 100-2 respectively corresponding to a plurality of printed circuit boards, and the electronic device 300 may be embedded in each unit. .

Next, as shown in FIG. 17 , a process of forming a slot in units of each unit may be performed. In this case, the slot may be formed to surround the side of the printed circuit board of the unit unit in an open loop shape, not in a closed loop shape. In other words, the slot may not be formed over the entire area of the side surface of the printed circuit board, but may be formed with respect to only a partial area. In this case, in FIG. 17 , the slot may include four unit slots S1 , S2 , S3 , and S4 , and a bridge region may be formed in a region between the unit slots S1 , S2 , S3 , and S4 . In this case, when the four unit slots are formed as described above, a bridge area may be formed in four corner areas among the side surfaces of each printed circuit board. However, when the bridge region is formed in such a structure, the region in which the first plating layer is not formed increases, and accordingly, a problem in electromagnetic wave shielding performance may occur.

As shown in FIG. 18 , in the embodiment, the bridge area as described above is formed only in one corner area among the plurality of corner areas.

That is, the side surface of the printed circuit board includes a plurality of corner regions. In addition, the slot may be formed in a region other than a corner region having the longest distance from an electronic device buried in the insulating substrate among the plurality of corner regions.

According to this, in the embodiment, it is possible to minimize the bridge area as described above, and accordingly, the electromagnetic wave shielding performance can be improved. In addition, since the bridge region is formed in a region furthest from an electronic device among the corner regions, it is possible to minimize the problems of electromagnetic wave shielding performance degradation and heat dissipation performance degradation caused by the bridge region.

Next, as shown in FIG. 19 , a process of forming the first plating layer 210 in the slot as formed in FIG. 18 may be performed. Accordingly, the first plating layer 210 may not be formed entirely on the side surface of the insulating substrate constituting the printed circuit board, and may not be formed in one region corresponding to the bridge region.

Next, as shown in FIG. 20 , a process of forming the second plating layer 220 on the formed first plating layer 210 may be performed. The second plating layer 220 may not be formed entirely on the first plating layer 210 , but may be formed only in a partial region. That is, the first plating layer 210 is formed on the upper surface area of the insulating substrate and the side area except for the bridge area, respectively. In addition, the second plating layer 220 may be formed only on a side area of the insulating substrate.

Next, as shown in FIG. 21 , a marking layer 230 may be formed on the first plating layer 210 formed on the upper surface of the insulating substrate.

22 is a view showing a printed circuit board according to another embodiment.

At this time, in the embodiment, the first plating layer, the second plating layer and A process of forming a coating layer may be performed.

22 has a structure in which an electronic device is additionally disposed on an upper portion and a molding layer for molding the electronic device is additionally disposed compared to the product of FIG. 1 .

That is, FIG. 22 shows an insulating substrate 100 corresponding to the insulating substrate shown in FIG. 1 , electronic devices 400a and 400b mounted on the insulating substrate, and disposed on the insulating substrate 100 , A molding layer 410 for molding the electronic devices 400a and 400b may be included.

And, according to another embodiment, the first plating layer 510 , the second plating layer 520 , and the marking layer 530 are the side surface of the insulating substrate, the side surface of the molding layer 410 , and the upper surface of the molding layer 410 . It may have a structure disposed in

That is, in FIG. 1 , the printed circuit board had a structure including only the insulating substrate, and accordingly, plating layers were formed on the upper surface of the insulating substrate.

Alternatively, in FIG. 22 , a molding layer is additionally disposed on the insulating substrate, and accordingly, the first plating layer 510 may have a structure disposed on the side surface of the molding layer and an upper surface thereof.

In an embodiment, the electromagnetic wave shielding layer formed on the outer side of the insulating substrate is formed using plating, thereby improving the reliability of the formed first plating layer. In addition, in the embodiment, by forming the first plating layer 210 formed on the outside of the insulating substrate through a plating process, it is possible to shorten the time required to form the first plating layer, thereby reducing the manufacturing cost. can In addition, in the embodiment, as the shielding layer for shielding electromagnetic waves is formed by plating, it is easy to control the thickness of the first plating layer 210 formed thereby.

In addition, in the embodiment, a bridge region in which a plating layer is not formed is formed in any one of the plurality of edge regions of the insulating substrate. That is, the side surface of the printed circuit board includes a plurality of corner regions. In addition, the slot may be formed in a region other than a corner region having the longest distance from an electronic device buried in the insulating substrate among the plurality of corner regions. According to this, in the embodiment, it is possible to minimize the bridge area as described above, and accordingly, the electromagnetic wave shielding performance can be improved. In addition, since the bridge region is formed in a region furthest from an electronic device among the corner regions, it is possible to minimize the problems of electromagnetic wave shielding performance degradation and heat dissipation performance degradation caused by the bridge region.

Features, structures, effects, etc. described in the above embodiments are included in at least one embodiment, and are not necessarily limited to only one embodiment. Furthermore, features, structures, effects, etc. illustrated in each embodiment can be combined or modified for other embodiments by those of ordinary skill in the art to which the embodiments belong. Accordingly, the contents related to such combinations and modifications should be interpreted as being included in the scope of the embodiments.

In the above, the embodiment has been mainly described, but this is only an example and does not limit the embodiment, and those of ordinary skill in the art to which the embodiment belongs are provided with several examples not illustrated above in the range that does not deviate from the essential characteristics of the embodiment. It can be seen that variations and applications of branches are possible. For example, each component specifically shown in the embodiment can be implemented by modification. And differences related to such modifications and applications should be construed as being included in the scope of the embodiments set forth in the appended claims.

Claims (10)

an insulating substrate including a plurality of insulating layers, wherein a cavity is formed in at least one insulating layer among the plurality of insulating layers;
a first electronic device disposed in the cavity of the insulating substrate; and
A plating layer disposed on a side surface of the insulating substrate,
The side surface of the insulating substrate,
a first portion on which the plating layer is disposed;
and a second portion excluding the first portion where the plating layer is not disposed,
a distance between the first electronic device and the first portion;
closer than the distance between the first electronic device and the second portion;
printed circuit board. According to claim 1,
The plating layer is
a first portion of the side surface of the insulating substrate and a first plating layer disposed on an upper surface of the insulating substrate; and
comprising a second plating layer disposed on the first plating layer;
printed circuit board. 3. The method of claim 2,
The first plating layer,
a first region formed in the first portion of a side surface of the insulating substrate;
a second region formed on the upper surface of the insulating substrate;
The second plating layer is disposed on the first region of the first plating layer,
printed circuit board. 4. The method of claim 3,
including a marking layer disposed on the second region of the first plating layer;
printed circuit board. According to claim 1,
The side surface of the insulating substrate includes a plurality of corner regions,
The second portion of the side surface of the insulating substrate is a corner region that is the farthest from the electronic device among the plurality of corner regions,
printed circuit board. According to claim 1,
The insulating substrate is
a second electronic device disposed on the uppermost insulating layer of the plurality of insulating layers; and
a molding layer disposed on the uppermost insulating layer and molding the second electronic device;
The plating layer is
disposed on a first portion of a side surface of the plurality of insulating layers and the molding layer,
printed circuit board. manufacturing an insulating substrate including a plurality of insulating layers in which a first electronic device is embedded in a cavity formed in at least one insulating layer among the plurality of insulating layers;
forming a slot passing through the insulating substrate;
Including forming a plating layer by performing plating in the slot,
The slot is
and at least one bridge region having an open loop shape on the insulating substrate;
The side surface of the insulating substrate,
a first portion corresponding to the region in which the slot is formed and on which the plating layer is disposed;
and a second portion corresponding to the bridge region except for the first portion on which the plating layer is not disposed;
a distance between the first electronic device and the first portion;
closer than the distance between the first electronic device and the second portion,
The plating layer is
a first portion of the side surface of the insulating substrate and a first plating layer disposed on an upper surface of the insulating substrate; and
comprising a second plating layer disposed on the first plating layer;
A method for manufacturing a printed circuit board. 8. The method of claim 7,
To manufacture the insulating substrate,
A plurality of units corresponding to the insulating substrate are manufactured as a panel base,
Including forming the slot in each of the plurality of units,
The bridge area is
In the panel base, to prevent the plurality of units from being separated from each other,
A method for manufacturing a printed circuit board. 8. The method of claim 7,
The first plating layer,
a first region formed in the first portion of a side surface of the insulating substrate;
a second region formed on the upper surface of the insulating substrate;
The second plating layer is disposed on the first region of the first plating layer,
Comprising forming a marking layer disposed on the second region of the first plating layer,
A method for manufacturing a printed circuit board. 8. The method of claim 7,
The side surface of the insulating substrate includes a plurality of corner regions,
The second portion of the side surface of the insulating substrate is a corner region that is the farthest from the electronic device among the plurality of corner regions,
A method for manufacturing a printed circuit board.

Images