KR20150099072A - A printed circuit board and a method of manufacturing the same - Google Patents

Abstract

A printed circuit board according to an embodiment includes: a first insulating layer which has a reference pad formed on one of an upper side and a lower side and has an internal via; an upper insulating layer which is formed on the first insulating layer and has an internal via; and a lower insulating layer which is formed under the first insulating layer and has an internal via. The via of the first insulating layer, the via of the upper insulating layer, or the via of the first insulating layer and the via of the lower insulating layer are integrated.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a printed circuit board (PCB)

The present invention relates to a printed circuit board and a method of manufacturing the same.

A printed circuit board (PCB) is a board formed by printing a circuit pattern on an electrically insulating substrate with a conductive material such as copper, and is a board immediately before mounting electronic components. In other words, a circuit board on which a mounting position of each component is determined, and a circuit pattern connecting the components are printed on the surface of the flat plate and fixed is fixed in order to densely mount various kinds of electronic devices on a flat plate.

Recently, with the development of the electronic industry, demands for high-performance, miniaturization, price competitiveness and short delivery time of electronic components are rapidly increasing. To cope with this trend, printed circuit board companies are responding to the trend of thinning and increasing density of printed circuit boards by applying semi-additive process (SAP: Semi Additive Process).

On the other hand, the printed circuit board as described above is formed with conductive vias for interlayer connection. In recent years, a large-size via is larger than a normal via in consideration of the heat radiation performance of a printed circuit board and the like.

1 is a cross-sectional view of a conventional printed circuit board.

1, a printed circuit board includes a first insulating layer 1, a second insulating layer 2, a third insulating layer 3, a fourth insulating layer 4, a fifth insulating layer 5, The first via 8, the second pad 9, the second via 10, the third pad 11, the third via 12, and the third insulating layer 6, the first via 7, the first pad 8, The fourth pad 13, the fourth via 14, the fifth pad 15, the fifth via 16, the sixth pad 17, the sixth via 18, and the seventh pad 19 do.

The printed circuit board is a coreless substrate without a core substrate at the center.

The first to sixth insulating layers 1, 2, 3, 4, 5, and 6 are all formed of the same material. That is, the first to sixth insulating layers 1, 2, 3, 4, 5, and 6 may be an insulating sheet formed only of resin.

The first via 7, the second via 10, the third via 12, the fourth via 14, the fifth via 16, and the sixth via 18 are formed in the first through sixth insulating layers 1, 2, 3, 4, 5, and 6, respectively.

The first pad 8, the second pad 9, the third pad 11, the fourth pad 13, the fifth pad 15, the sixth pad 17 and the seventh pad 19 Are formed on the surfaces of the first to sixth insulating layers 1, 2, 3, 4, 5 and 6 so as to form the first to sixth insulating layers 1, 2, 3, 4, 5, It is extended to the surface.

The first pad 8, the second pad 9, the third pad 11, the fourth pad 13, the fifth pad 15, the sixth pad 17 and the seventh pad 19 And connects the first via 7, the second via 10, the third via 12, the fourth via 14, the fifth via 16 and the sixth via 18 with each other.

Hereinafter, a method of manufacturing a printed circuit board according to the related art will be described.

FIGS. 2 to 4 are cross-sectional views illustrating a method of manufacturing a printed circuit board according to a conventional technique shown in FIG.

First, referring to FIG. 2, a first insulating layer 1 is prepared, a via hole (not shown) is formed in the prepared first insulating layer 1, and then a conductive paste Or the first via 7 is formed by plating a metal material.

A first pad 8 connected to the upper surface of the first via 7 is formed on the upper surface of the first insulating layer 1 and a second pad 8 is formed on the lower surface of the first insulating layer 1, And a second pad 9 connected to the bottom surface of the first substrate 7 is formed.

Next, referring to FIG. 3, a second insulating layer 2 is formed on the first insulating layer 1, and a fifth insulating layer 5 is formed on the first insulating layer 1.

The second vias 10 are formed in the second insulating layer 2 in the same manner as the first vias 7. A third pad 11 connected to the upper surface of the second via 10 is formed on the upper surface of the second insulating layer 2.

A fifth pad 16 is formed on the fifth insulating layer 5 and a sixth pad 17 connected to the lower surface of the fifth pad 16 is formed on the fifth insulating layer 5, As shown in FIG.

Next, referring to FIG. 4, a third insulating layer 3, a fourth insulating layer 4, and a sixth insulating layer 6 are formed in the same manner as described above.

A third pad 12 is formed on the third insulating layer 3 and a fourth pad 13 connected to the upper surface of the third via 12 is formed on the upper surface of the third insulating layer 3, .

A fourth insulating layer 4 is formed on the third insulating layer 3 and a fourth vias 14 is formed on the fourth insulating layer 4. The fourth insulating layer 4 The fifth pad 15 is formed.

A sixth insulating layer 6 is formed under the fifth insulating layer 5, a sixth via 6 is formed in the sixth insulating layer 6, and the sixth insulating layer 6 The seventh pad 19 is formed.

However, the printed circuit board according to the related art has a pad for connection of vias for each insulating layer, which restricts the design of the printed circuit board.

In addition, in the above-described conventional printed circuit board, a laser process and a via plating process must be performed for each insulating layer, leading to an increase in lead time.

Embodiments provide a printed circuit board of a new structure.

Embodiments provide printed circuit boards comprising vias of new construction.

It is to be understood that the technical objectives to be achieved by the embodiments are not limited to the technical matters mentioned above and that other technical subjects not mentioned are apparent to those skilled in the art to which the embodiments proposed from the following description belong, It can be understood.

A printed circuit board according to an exemplary embodiment of the present invention includes a first insulation layer having a reference pad formed on one of an upper surface and a lower surface and having a via formed therein; An upper insulating layer formed on the first insulating layer and having a via formed therein; And a lower insulating layer formed under the first insulating layer and having a via formed therein, the via formed in the first insulating layer, the via formed in the upper insulating layer, or the via formed in the first insulating layer, The vias formed in the lower insulating layer are integrally formed.

In addition, the reference pad may be formed on the upper surface of the first insulating layer, and the vias of the first insulating layer and the vias of the lower insulating layer formed below the reference pad formed on the upper surface may be integrally formed do.

The lower surface of the via formed in the first insulating layer and the upper surface of the via formed in the lower insulating layer are in direct contact with each other with the same width.

The reference pad may be formed on the lower surface of the first insulating layer, and the vias of the first insulating layer and the vias of the upper insulating layer formed on the upper surface of the reference pad formed on the lower surface may be integrally formed do.

The upper surface of the via formed in the first insulating layer and the lower surface of the via formed in the upper insulating layer are in direct contact with each other with the same width.

The upper insulating layer may include a second insulating layer formed on the first insulating layer, and a third insulating layer formed on the second insulating layer. The via formed in the second insulating layer, Are formed integrally with each other.

The lower insulating layer may include a second insulating layer formed under the first insulating layer,

And a third insulating layer formed below the second insulating layer,

The via formed in the second insulating layer and the via formed in the third insulating layer are formed integrally with each other.

The vias formed in the second insulating layer and the third insulating layer are integrally formed with the vias formed in the first insulating layer.

The upper insulating layer and the lower insulating layer are each formed of a plurality of layers. Vias of the plurality of insulating layers located at the upper portion with respect to the reference pad are integrally formed with each other. The vias of the plurality of insulating layers are formed integrally with each other.

In addition, at least one of the vias of the plurality of insulating layers located at the upper portion and the vias of the plurality of insulating layers located at the lower portion has a shape gradually increasing in width from one surface contacting the reference pad to the other surface.

According to another aspect of the present invention, there is provided a method of manufacturing a printed circuit board, including: forming a reference pad on one surface of a first insulating layer; Forming an upper insulating layer on the first insulating layer; Forming a lower insulating layer on a lower portion of the first insulating layer; Forming a first via hole exposing an upper surface of the reference pad by simultaneously opening all the insulating layers located on the upper side of the reference pad formed on the first insulating layer; Forming a second via hole exposing a bottom surface of the reference pad by simultaneously opening all insulating layers located below the reference pad formed on the first insulating layer; Filling the first via hole with a conductive paste to form a first via filling the first via hole; And filling the second via hole with a conductive paste to form a second via filling the second via hole.

The reference pad is formed on the upper surface of the first insulating layer and the second via hole is formed by simultaneously opening the first insulating layer and the lower insulating layer, A second via hole formed by simultaneously opening the first insulating layer and the lower insulating layer is buried.

The lower surface of the second via formed in the first insulating layer and the upper surface of the second via formed in the lower insulating layer are in direct contact with each other with the same width.

The reference pad may be formed on a lower surface of the first insulating layer and the first via hole may be formed by simultaneously opening the first insulating layer and the upper insulating layer, The first via hole formed by simultaneously opening the first insulating layer and the upper insulating layer is buried.

The upper surface of the first via formed in the first insulating layer and the lower surface of the first via formed in the lower insulating layer are in direct contact with each other with the same width.

In addition, at least one of the first via and the second via has a shape extending from one surface contacting with the reference pad to the other surface.

In addition, the upper insulating layer is formed of a plurality of layers, and the first vias are integrally formed in the upper insulating layer composed of the plurality of layers.

Further, the lower insulating layer is composed of a plurality of layers, and the second vias are integrally formed in the lower insulating layer composed of the plurality of layers.

According to the embodiment of the present invention, since it is unnecessary to form an additional pad in addition to the reference pad, the degree of design freedom of the printed circuit board can be increased.

Further, according to the embodiment of the present invention, by forming via-holes for opening a plurality of layers at one time and forming vias for embedding the via-holes thus formed, lead time and process cost for manufacturing a printed circuit board Can be saved.

Further, according to the embodiment of the present invention, since the vias formed in the plurality of layers are integrally formed at the same time, the alignment property of the vias formed in each of the plurality of layers can be improved.

1 is a cross-sectional view of a conventional printed circuit board.
FIGS. 2 to 4 are cross-sectional views illustrating a method of manufacturing a printed circuit board according to a conventional technique shown in FIG.
5 is a cross-sectional view illustrating a printed circuit board according to a first embodiment of the present invention.
FIGS. 6 to 10 are cross-sectional views illustrating a method of manufacturing a printed circuit board according to a first embodiment of the present invention shown in FIG.
11 is a cross-sectional view illustrating a printed circuit board according to a second embodiment of the present invention.
12 to 14 are cross-sectional views illustrating a method of manufacturing a printed circuit board according to a second embodiment of the present invention shown in FIG. 11 in the order of steps.
15 is a cross-sectional view illustrating a printed circuit board according to a third embodiment of the present invention.
16 to 18 are sectional views for explaining the manufacturing method of the printed circuit board according to the third embodiment of the present invention shown in FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

Throughout the specification, when an element is referred to as "comprising ", it means that it can include other elements as well, without excluding other elements unless specifically stated otherwise.

In order to clearly illustrate the present invention in the drawings, thicknesses are enlarged in order to clearly illustrate various layers and regions, and parts not related to the description are omitted, and like parts are denoted by similar reference numerals throughout the specification .

Whenever a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the case where it is "directly on" another portion, but also the case where there is another portion in between. Conversely, when a part is "directly over" another part, it means that there is no other part in the middle.

5 is a cross-sectional view illustrating a printed circuit board according to a first embodiment of the present invention.

5, the printed circuit board 100 includes a first insulating layer 110, a second insulating layer 120, a third insulating layer 130, a fourth insulating layer 140, a fifth insulating layer The first via layer 150, the sixth insulating layer 160, the reference pad 115, the first via 170, the second via 180, the first outer layer pad 190, and the second outer layer pad 195.

The first insulating layer 110, the second insulating layer 120, the third insulating layer 130, the fourth insulating layer 140, the fifth insulating layer 150, Inorganic composite substrate or a glass fiber impregnated substrate. When a polymer resin is included, it may be a thermosetting or thermoplastic polymer substrate, a ceramic substrate, a bismaleimide triazine (BT), an ABF And Ajinomoto Build up Film. Alternatively, the epoxy resin may include a polyimide resin, but is not limited thereto.

The first insulating layer 110, the second insulating layer 120, the third insulating layer 130, the fourth insulating layer 140, the fifth insulating layer 150, and the sixth insulating layer 160 are the same And is preferably an insulating sheet formed of only a resin.

The first insulating layer 110 may be a reference insulating layer. The reference insulating layer includes a first insulating layer 110, a second insulating layer 120, a third insulating layer 130, a fourth insulating layer 140, a fifth insulating layer 150, 6 < / RTI > insulating layer.

A reference pad 115 is formed on one of the reference insulating layers 110.

The reference pad 115 may be formed by a conventional process such as an additive process, a subtractive process, a modified semi- additive process (MSAP), and a semi- additive process (SAP) And detailed description is omitted here.

The reference pad 115 is formed of a metal including copper.

A second insulating layer 120, a third insulating layer 130, and a fourth insulating layer 140 are sequentially stacked on the first insulating layer 110.

A fifth insulating layer 150 and a sixth insulating layer 160 are sequentially stacked under the first insulating layer 110.

A first via hole 175 is formed in the insulating layer formed on the upper portion of the reference pad 115. A second via hole 175 is formed in the insulating layer formed on the lower surface of the reference pad 115, 185 are formed.

The first via hole 175 is formed in the second insulating layer 120, the third insulating layer 130, and the fourth insulating layer 140, respectively.

At this time, the first via hole 175 is formed by simultaneously opening the second insulating layer 120, the third insulating layer 130, and the fourth insulating layer 140.

Accordingly, the width of the first via hole 175 of the second insulating layer 120, the third insulating layer 130, and the fourth insulating layer 140 is greater than the width of the via hole of the insulating layer Hole width of the insulating layer formed in the lower portion.

In other words, the top width of the via hole formed in the second insulating layer 120 is the same as the bottom width of the via hole formed in the third insulating layer 130.

In addition, an upper width of the via hole formed in the third insulating layer 130 is equal to a width of a lower portion of the via hole formed in the fourth insulating layer 140.

A first via 170 is formed in the second insulating layer 120, the third insulating layer 130, and the fourth insulating layer 140. In other words, the first via hole 175 is filled with a metal material, so that the first via 170 is formed.

At this time, the first vias 170 formed in the second insulating layer 120, the third insulating layer 130, and the fourth insulating layer 140 are simultaneously formed.

That is, the first vias 170 are formed in the second insulating layer 120, the third insulating layer 130, and the fourth insulating layer 140. At this time, the second insulating layer 120, The vias formed in the third insulating layer 130 and the fourth insulating layer 140 are formed integrally with each other.

The lower surface of the first via 170 formed in the second insulation layer 120 is in direct contact with the upper surface of the reference pad 115 and the first via 170 formed in the second insulation layer 120 170 are in direct contact with the lower surface of the first via 170 formed in the third insulating layer 130.

The upper surface of the first via 170 formed in the second insulating layer 120 is the same as the lower surface of the first via 170 formed in the third insulating layer 130.

The upper surface of the first via 170 formed in the third insulating layer 130 is in direct contact with the lower surface of the first via 170 formed in the fourth insulating layer 140.

The top surface of the first via 170 formed in the third insulating layer 130 is equal to the bottom width of the first via 170 formed in the fourth insulating layer 140.

A first outer layer pad 190 is formed on the upper surface of the fourth insulating layer 140 to contact the upper surface of the first via 170.

That is, according to the embodiment of the present invention, the pads formed in the laminated structure of the plurality of insulating layers do not exist except for the reference pad 115 described above. Further, an outer layer pad as described above is formed on the exposed surface of the insulating layer formed on the outermost layer.

The second via hole 185 is formed in the first insulating layer 110, the fifth insulating layer 150, and the sixth insulating layer 160.

In other words, the insulating layer formed on the lower side with respect to the reference pad 115 is a first insulating layer 110, a fifth insulating layer 150, and a sixth insulating layer 160, The second via hole 185 is formed in the layer 110, the fifth insulating layer 150, and the sixth insulating layer 160.

The second via hole 185 is formed by simultaneously opening the first insulating layer 110, the fifth insulating layer 150, and the sixth insulating layer 160.

Hence, the width of the second via hole 185 of the first insulating layer 110, the fifth insulating layer 150, and the sixth insulating layer 160 is determined by the width of the via hole of the insulating layer Hole width of the insulating layer formed in the lower portion.

In other words, the bottom width of the via hole formed in the first insulating layer 110 is equal to the top width of the via hole formed in the fifth insulating layer 150.

The lower width of the via hole formed in the fifth insulating layer 150 is the same as the upper width of the via hole formed in the sixth insulating layer 160.

A second via 180 is formed in the first insulating layer 110, the fifth insulating layer 150, and the sixth insulating layer 160. In other words, the second via hole 185 is filled with a metal material, so that the second via 180 is formed.

At this time, the second vias 180 formed in the first insulating layer 110, the fifth insulating layer 150, and the sixth insulating layer 160 are simultaneously formed.

That is, the second vias 180 are formed in the twelfth insulating layer 110, the fifth insulating layer 150, and the sixth insulating layer 160. At this time, the first insulating layer 110, The vias formed in the fifth insulating layer 150 and the sixth insulating layer 160 are formed integrally with each other.

The upper surface of the second vias 180 formed in the first insulating layer 130 is in direct contact with the lower surface of the reference pad 115 and the second vias 180 formed in the fifth insulating layer 150 180 are in direct contact with the lower surface of the second via 180 formed in the first insulating layer 110.

The upper surface of the second via 180 formed in the fifth insulating layer 120 is equal to the lower surface of the second via 180 formed in the first insulating layer 110.

The upper surface of the second via 180 formed in the sixth insulating layer 160 is in direct contact with the lower surface of the second via 180 formed in the fifth insulating layer 150.

The upper surface of the second via 180 formed in the sixth insulating layer 160 is equal to the lower surface of the second via 180 formed in the fifth insulating layer 150.

A second outer layer pad 195 is formed on the lower surface of the sixth insulating layer 160 to contact the lower surface of the second via 170.

Meanwhile, the first vias 170 have a shape gradually increasing in width from one surface contacting the reference pad 115 to the other surface. That is, the first vias 170 have a trapezoidal shape whose upper surface width is larger than the lower surface width.

 The second via 180 has a shape gradually increasing in width from one surface contacting the reference pad 115 to the other surface. That is, the second vias 170 have a trapezoidal shape in which the bottom width is larger than the bottom width.

Also, in the overall structure, the second vias 180 are formed to have a larger width than the first vias 170. [

The first via 170 and the second via 180 may be any one selected from among Cu, Ag, Sn, Au, Ni, and Pd and may be formed by electroless plating, electrolytic plating, screen printing Printing, printing, sputtering, evaporation, inkjetting, or dispensing, or a combination thereof.

According to the embodiment of the present invention, since it is unnecessary to form an additional pad in addition to the reference pad, the degree of design freedom of the printed circuit board can be increased.

Further, according to the embodiment of the present invention, by forming via-holes for opening a plurality of layers at one time and forming vias for embedding the via-holes thus formed, lead time and process cost for manufacturing a printed circuit board Can be saved.

Further, according to the embodiment of the present invention, since the vias formed in the plurality of layers are integrally formed at the same time, the alignment property of the vias formed in each of the plurality of layers can be improved.

FIGS. 6 to 10 are cross-sectional views illustrating a method of manufacturing a printed circuit board according to a first embodiment of the present invention shown in FIG.

First, referring to FIG. 6, a first insulating layer 110 is prepared as a center of a printed circuit board, and a reference pad 115 is formed on an upper surface of the prepared first insulating layer 110.

7, a plurality of insulating layers are sequentially stacked on the upper surface of the first insulating layer 110, and a plurality of insulating layers are sequentially stacked on the lower surface of the first insulating layer 110 do.

In other words, when the reference pad 115 is formed, a second insulating layer 120 is formed on the first insulating layer 110. When the second insulating layer 120 is stacked, a third insulating layer 130 is stacked on the second insulating layer 120. When the third insulating layer 130 is stacked, a fourth insulating layer 140 is stacked on the third insulating layer 130.

A fifth insulating layer 150 is formed under the first insulating layer 110. In addition, when the fifth insulating layer is stacked, a sixth insulating layer 160 is stacked below the fifth insulating layer 150.

Next, referring to FIG. 8, a plurality of insulating layers formed on the upper portion of the reference pad 115 are simultaneously opened to form a first via hole 175.

That is, the second insulating layer 120, the third insulating layer 130, and the fourth insulating layer 140 formed on the upper portion of the reference pad 115 are simultaneously opened to form the upper surface Lt; / RTI >

The first via hole 175 may be formed by any one of mechanical, laser, and chemical processing.

When the first via hole 175 is formed by machining, a method such as milling, drill, and routing may be used. In the case where the first via hole 175 is formed by laser processing, UV or Co2 The second insulating layer 120, the third insulating layer 130, and the fourth insulating layer 140 may be formed using chemical agents including aminosilane, ketones, and the like. Can be opened at the same time.

On the other hand, the processing by laser is a cutting method in which a part of a material is melted and evaporated by concentrating optical energy on the surface to take a desired shape, and complicated formation by a computer program can be easily processed.

In addition, the processing by the laser can have a cutting diameter of at least 0.005 mm, and has a wide range of thickness that can be processed.

As the laser processing drill, it is preferable to use a CO2 laser. The reference pad 115 serves as a stopper and the second insulating layer 120, the third insulating layer 130, and the fourth insulating layer 140 Can be opened at the same time, thereby exposing the upper surface of the reference pad 115 to the outside.

The second via hole 185 is formed by simultaneously opening a plurality of insulating layers formed at the lower portion around the reference pad 115.

That is, the first insulating layer 110, the fifth insulating layer 150, and the sixth insulating layer 160 formed at the lower portion of the reference pad 115 are simultaneously opened to form the lower surface of the reference pad 115 Lt; / RTI >

The second via hole 175 may be formed by any one of mechanical, laser, and chemical processing.

When the second via hole 175 is formed by machining, a method such as milling, drilling, and routing may be used. In the case where the second via hole 175 is formed by laser machining, UV or Co2 The first insulating layer 110, the fifth insulating layer 150, and the sixth insulating layer 160 may be formed using chemical agents including aminosilane, ketones, and the like. Can be opened at the same time.

Referring to FIG. 9, when the first and second via holes 175 and 185 are formed, an upper surface of the fourth insulating layer 140 and an upper surface of the sixth insulating layer 160 (Not shown). A first outer layer pad 190 is formed on an upper surface of the fourth insulating layer 140 to expose the first via hole 175. A lower surface of the sixth insulating layer 160 may have a second via hole The second outer layer pad 195 exposing the hole 185 is formed.

Next, as shown in FIG. 10, a first via 170 filling the first via hole 175 is formed by filling metal paste into the first via hole 175.

The first via 170 is formed over the second insulating layer 120, the third insulating layer 130 and the fourth insulating layer 140. The second insulating layer 120, The first via 170 formed over the first insulating layer 130 and the fourth insulating layer 140 is integrally formed.

The second via hole 185 is filled with a metal paste to form a second via 180 filling the second via hole 185.

The second via 180 is formed over the first insulating layer 110, the fifth insulating layer 150 and the sixth insulating layer 160. The first insulating layer 110, The second via 180 formed over the first insulating layer 150 and the sixth insulating layer 160 is integrally formed.

11 is a cross-sectional view illustrating a printed circuit board according to a second embodiment of the present invention.

11, the printed circuit board 200 includes a first insulating layer 210, a second insulating layer 220, a third insulating layer 230, a fourth insulating layer 240, 250, a sixth insulating layer 260, a reference pad 215, a first via 270, a second via 280, a first outer layer pad 290 and a second outer layer pad 295.

The printed circuit board according to the second embodiment of the present invention is generally the same as the printed circuit board according to the first embodiment, and the positions where the reference pads 215 are formed are different.

The shapes of the first via 270 and the second via 280 according to the position of the reference pad 215 of the printed circuit board according to the second embodiment are the same as those of the printed circuit board according to the first embodiment. The first via 170 and the second via 180 disclosed in FIG.

That is, the printed circuit board 200 has the reference pad 215 formed on the lower surface of the first insulating layer 210.

A second insulating layer 220, a third insulating layer 230, a fourth insulating layer 240, and a fifth insulating layer 250 are sequentially stacked on the first insulating layer 210.

In addition, only the sixth insulating layer 260 is formed under the first insulating layer 210.

The first insulating layer 210, the second insulating layer 220, the third insulating layer 230, the fourth insulating layer 240, and the fifth insulating layer 250 As shown in Fig.

In addition, the second via 280 is formed only in the sixth insulating layer 260.

12 to 14 are cross-sectional views illustrating a method of manufacturing a printed circuit board according to a second embodiment of the present invention shown in FIG. 11 in the order of steps.

12, a first insulating layer 210 serving as a center of a printed circuit board is prepared, and a reference pad 215 is formed on a lower surface of the prepared first insulating layer 210. Referring to FIG.

Next, referring to FIG. 13, a plurality of insulating layers are sequentially stacked on the upper surface of the first insulating layer 210, and one insulating layer is stacked on the lower surface of the first insulating layer 210.

In other words, when the reference pad 215 is formed, a second insulating layer 220 is formed on the first insulating layer 210. When the second insulating layer 220 is stacked, a third insulating layer 230 is stacked on the second insulating layer 220. When the third insulating layer 230 is stacked, a fourth insulating layer 240 is stacked on the third insulating layer 230. When the fourth insulating layer 240 is stacked, a fifth insulating layer 250 is formed on the fourth insulating layer 240.

Also, a sixth insulating layer 260 is formed under the first insulating layer 210.

A plurality of insulating layers formed on the upper portion of the reference pad 215 are simultaneously opened to form a first via hole 275.

That is, the first insulating layer 210, the second insulating layer 220, the third insulating layer 230, the fourth insulating layer 240, and the fifth insulating layer 210 formed on the upper portion of the reference pad 215, (250) are simultaneously opened to expose the upper surface of the formed reference pad (215).

A second via hole 275 exposing the lower surface of the reference pad 215 is formed by opening a sixth insulating layer 260 formed below the reference pad 215.

Referring to FIG. 14, when the first and second via holes 275 and 285 are formed, the first via hole 275 is filled with a metal paste to form the first via hole 275 Thereby forming a first via 270 to be buried. At this time, a first outer layer pad 290 extending to the surface of the fifth insulating layer 250 is formed at an upper end of the first via 270.

The second via hole 285 is filled with a metal paste to form a second via 280 filling the second via hole 285.

15 is a cross-sectional view illustrating a printed circuit board according to a third embodiment of the present invention.

15, the printed circuit board 300 includes a first insulating layer 310, a second insulating layer 320, a third insulating layer 330, a fourth insulating layer 340, a fifth insulating layer A first via layer 350 and a second insulating layer 360. The second insulating layer 360 includes a reference pad 315, a first via 370, a second via 380, a first outer layer pad 390 and a second outer layer pad 395.

The printed circuit board according to the third embodiment of the present invention is generally the same as the printed circuit board according to the first and second embodiments, except that the reference pad 315 is formed at a different position.

The shapes of the first via 370 and the second via 380 may be different from those of the first and second embodiments according to the position of the reference pad 315 of the printed circuit board according to the third embodiment. Is different from the shape of the first via and the second via disclosed in the circuit board.

That is, the printed circuit board 300 has the reference pad 315 formed on the upper surface of the first insulating layer 310.

In addition, only the second insulating layer 320 is formed on the first insulating layer 310.

A third insulating layer 330, a fourth insulating layer 340, a fifth insulating layer 350, and a sixth insulating layer 360 are formed under the first insulating layer 310.

Accordingly, the first via 370 is formed only in the second insulating layer 320, and the second via 380 is formed in the first insulating layer 310, the third insulating layer 330, The insulating layer 340, the fifth insulating layer 350, and the sixth insulating layer 360.

16 to 18 are sectional views for explaining the manufacturing method of the printed circuit board according to the third embodiment of the present invention shown in FIG.

Referring to FIG. 16, a first insulating layer 310 serving as a center of a printed circuit board is prepared, and a reference pad 315 is formed on an upper surface of the prepared first insulating layer 310.

17, one insulating layer is stacked on the upper surface of the first insulating layer 310, and a plurality of insulating layers are sequentially stacked on the lower surface of the first insulating layer 310. Next, as shown in FIG.

In other words, when the reference pad 315 is formed, a second insulating layer 320 is formed on the first insulating layer 310.

Also, a third insulating layer 330 is formed under the first insulating layer 310. When the third insulating layer 330 is stacked, a fourth insulating layer 340 is stacked under the third insulating layer 330. When the fourth insulating layer 340 is stacked, a fifth insulating layer 350 is stacked under the fourth insulating layer 340. When the fifth insulating layer 350 is stacked, a sixth insulating layer 360 is stacked under the fifth insulating layer 350.

Then, the second insulating layer 320 formed on the upper portion of the reference pad 315 is opened to form a first via hole 375.

The first insulating layer 310, the third insulating layer 330, the fourth insulating layer 340, the fifth insulating layer 350, and the sixth insulating layer 350 formed below the reference pad 315, (360) are simultaneously opened to expose the lower surface of the formed reference pad (315).

18, when the first and second via holes 375 and 385 are formed, a metal paste is filled in the first via hole 375, and the first via hole 375 is filled with a metal paste, Thereby forming a first via 370 to be buried. At this time, a first outer layer pad 390 extending to the surface of the second insulating layer 320 is formed at an upper end of the first via 370.

A second via 380 filling the second via hole 385 is formed by filling a metal paste in the second via hole 385.

According to the embodiment of the present invention, since it is unnecessary to form an additional pad in addition to the reference pad, the degree of design freedom of the printed circuit board can be increased.

Further, according to the embodiment of the present invention, by forming via-holes for opening a plurality of layers at one time and forming vias for embedding the via-holes thus formed, lead time and process cost for manufacturing a printed circuit board Can be saved.

Further, according to the embodiment of the present invention, since the vias formed in the plurality of layers are integrally formed at the same time, the alignment property of the vias formed in each of the plurality of layers can be improved.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It belongs to the scope of right.

100, 200, 300: printed circuit board
110, 210 310: first insulating layer
120, 220 320: second insulating layer
130, 230 330: third insulating layer
140, 240 340: fourth insulating layer
150, 250 350: fifth insulating layer
160, 260 360: Sixth insulating layer
170, 270 370: 1st vias
180, 280 380: Second Via
190, 290, 390: first outer layer pad
195, 295, 395: second outer layer pad

Claims (18)

A first insulating layer having a reference pad formed on one surface of the upper surface and the lower surface and having a via formed therein;
An upper insulating layer formed on the first insulating layer and having a via formed therein; And
And a lower insulating layer formed under the first insulating layer and having a via formed therein,
The via formed in the first insulating layer, the via formed in the upper insulating layer, or the via formed in the first insulating layer and the via formed in the lower insulating layer are integrally formed
Printed circuit board. The method according to claim 1,
The reference pad includes:
A second insulating layer formed on the first insulating layer,
The vias of the first insulating layer and the vias of the lower insulating layer formed below the reference pad formed on the upper surface are formed integrally with each other
Printed circuit board. The method according to claim 1,
The lower surface of the via formed in the first insulating layer and the upper surface of the via formed in the lower insulating layer are in direct contact with each other
Printed circuit board. The method according to claim 1,
The reference pad includes:
A second insulation layer formed on the lower surface of the first insulation layer,
The vias of the first insulating layer and the vias of the upper insulating layer formed on the upper portion of the reference pad formed on the lower surface are integrally formed
Printed circuit board. 5. The method of claim 4,
The upper surface of the via formed in the first insulating layer and the lower surface of the via formed in the upper insulating layer are in direct contact with each other,
Printed circuit board. The method according to claim 1,
The upper insulating layer
A second insulating layer formed on the first insulating layer,
And a third insulating layer formed on the second insulating layer,
The via formed in the second insulating layer, and the via formed in the third insulating layer,
Formed integrally with each other
Printed circuit board. The method according to claim 1,
The lower insulating layer
A second insulating layer formed under the first insulating layer,
And a third insulating layer formed below the second insulating layer,
The via formed in the second insulating layer, and the via formed in the third insulating layer,
Formed integrally with each other
Printed circuit board. 7. A method according to any one of claims 6 and 7,
The via formed in the second insulating layer and the third insulating layer,
And a second insulating layer formed integrally with the via formed in the first insulating layer
Printed circuit board. The method according to claim 1,
Wherein the upper insulating layer and the lower insulating layer each comprise a plurality of layers,
The vias of the plurality of insulating layers located at the upper portion with respect to the reference pad are integrally formed with each other,
The vias of the plurality of insulating layers located at the lower portion around the reference pad are formed integrally with each other
Printed circuit board. 10. The method of claim 9,
At least one of the vias of the plurality of insulating layers located at the upper portion and the vias of the plurality of insulating layers located at the lower portion,
The width of the reference pad gradually increases from one surface contacting the reference pad toward the other surface
Printed circuit board. Forming a reference pad on one surface of the first insulating layer;
Forming an upper insulating layer on the first insulating layer;
Forming a lower insulating layer on a lower portion of the first insulating layer;
Forming a first via hole exposing an upper surface of the reference pad by simultaneously opening all the insulating layers located on the upper side of the reference pad formed on the first insulating layer;
Forming a second via hole exposing a bottom surface of the reference pad by simultaneously opening all insulating layers located below the reference pad formed on the first insulating layer;
Filling the first via hole with a conductive paste to form a first via filling the first via hole; And
Filling the second via hole with a conductive paste to form a second via filling the second via hole;
A method of manufacturing a printed circuit board. 12. The method of claim 11,
The reference pad includes:
A second insulating layer formed on the upper surface of the first insulating layer,
And the second via-
The first insulating layer and the lower insulating layer are simultaneously opened,
Wherein the second via comprises:
And a second via hole formed by simultaneously opening the first insulating layer and the lower insulating layer
A method of manufacturing a printed circuit board. 13. The method of claim 12,
The lower surface of the second via formed in the first insulating layer and the upper surface of the second via formed in the lower insulating layer are in direct contact with each other
A method of manufacturing a printed circuit board. 12. The method of claim 11,
The reference pad includes:
A second insulating layer formed on the lower surface of the first insulating layer,
Wherein the first via-
The first insulating layer and the upper insulating layer are simultaneously opened,
Wherein the first via comprises:
A first via hole formed by simultaneously opening the first insulating layer and the upper insulating layer
A method of manufacturing a printed circuit board. 15. The method of claim 14,
The upper surface of the first via formed in the first insulating layer and the lower surface of the first via formed in the lower insulating layer are in direct contact with each other
A method of manufacturing a printed circuit board. 15. A method according to any one of claims 14 and 15,
At least one of the first via and the second via,
And has a shape in which a width is extended from one surface contacting the reference pad toward the other surface
A method of manufacturing a printed circuit board. 12. The method of claim 11,
Wherein the upper insulating layer is composed of a plurality of layers,
And the first via is integrally formed in the upper insulating layer composed of the plurality of layers
A method of manufacturing a printed circuit board. 12. The method of claim 11,
Wherein the lower insulating layer is composed of a plurality of layers,
And the second via is integrally formed in the lower insulating layer composed of the plurality of layers
A method of manufacturing a printed circuit board.

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