KR20220135944A - Circuit board and package substrate including the same - Google Patents

Abstract

According to an embodiment of the present invention, a circuit board comprises: an insulating layer; a first circuit pattern disposed on an upper surface of the insulating layer; a second circuit pattern disposed on a lower surface opposite to the upper surface of the insulating layer; and a via penetrating the insulating layer, and electrically connected to the first and second circuit patterns. The first circuit pattern is buried in the upper surface of the insulating layer, and an upper surface of the via is located higher than a lower surface of the first circuit pattern. The via includes a first via and a second via spaced apart from the first via in a width direction, and a pitch corresponding to a distance from the center of the first via to the center of the second via is 100 μm or less. Therefore, the volume of a package substrate can be reduced.

Description

Circuit board and package board including same {CIRCUIT BOARD AND PACKAGE SUBSTRATE INCLUDING THE SAME}

The embodiment relates to a circuit board, and more particularly, to a circuit board capable of minimizing a pitch between a plurality of adjacent pads, and a package board including the same.

As the performance of electric/electronic products progresses, techniques for attaching a larger number of packages to a substrate having a limited size are being proposed and studied. However, since a general package is based on mounting one semiconductor chip, there is a limit in obtaining desired performance.

A typical package substrate has a form in which a processor package in which a processor chip is disposed and a memory package to which a memory chip is attached are connected as one. Such a package substrate has the advantage of reducing a chip mounting area and enabling high-speed signals through a short pass by manufacturing the processor chip and the memory chip as one integrated package.

Due to these advantages, the package substrate as described above is widely applied to mobile devices and the like.

On the other hand, in recent years, due to the high specification of electronic devices such as mobile devices and the adoption of high bandwidth memory (HBM), a circuit board capable of mounting a plurality of chips on one package board is required.

However, the conventional circuit board for a package has a size limitation due to a design limitation of a pad on which a chip is mounted. For example, in a conventional circuit board for a package, the size of a minimum via, a size of a pad according to the size of the via, a size of a trace disposed between a plurality of pads, and an opening of a solder resist for opening the surface of the pad The size of the Solder resist open region (SOR) is limited. For example, in the conventional circuit board for package, the pitch of the pad for chip mounting exceeds 100 micrometers. Accordingly, when the conventional circuit board for a package is used, the number of chips that can be mounted in a limited space can be reduced. For example, in the related art, there is a problem in that the volume of the circuit board increases in order to mount all of the plurality of chips due to the limitation of the pitch of the pads.

In addition, recently, a circuit board having a fine pitch using a photosensitive material (eg, PID) has been developed. However, the circuit board made of the photosensitive material is vulnerable to warpage, and there is a problem in that the manufacturing cost is high compared to the circuit board manufactured using the prepreg.

In the embodiment, an object of the present invention is to provide a circuit board having a novel structure capable of minimizing the pitch of mounting pads and a package board including the same.

In addition, the embodiment intends to provide a circuit board in which a via passing through an insulating layer, not a pad, can be used as a mounting pad of a chip, and a package board including the same.

In addition, an embodiment is to provide a circuit board having a new structure such that the outermost chip mounting pad has a fine pitch of 100 μm or less in a circuit board made of a prepreg, and a package board including the same.

The technical tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks not mentioned are clear to those of ordinary skill in the art to which the proposed embodiment belongs from the description below. will be able to be understood

A circuit board according to an embodiment includes an insulating layer; a first circuit pattern disposed on an upper surface of the insulating layer; a second circuit pattern disposed on a lower surface of the insulating layer opposite to the upper surface; and a via passing through the insulating layer and electrically connected to the first circuit pattern and the second circuit pattern, wherein the first circuit pattern is buried in the upper surface of the insulating layer, and a top surface of the via is positioned higher than a lower surface of the first circuit pattern, the via includes a first via and a second via spaced apart from the first via in a width direction, from a center of the first via to a center of the second via The pitch corresponding to the distance to is 100 µm or less.

In addition, an upper surface of the first via and an upper surface of the second via are positioned on the same plane as an upper surface of the first circuit pattern.

In addition, each of the first via and the second via has a thickness greater than a thickness of the insulating layer corresponding to a distance from a lower surface of the first circuit pattern to an upper surface of the second circuit pattern.

In addition, the first circuit pattern includes a trace, and at least one trace of the first circuit pattern is disposed between a side surface of the first via and a side surface of the second via.

The second circuit pattern may include: a first pad connected to the first via; and a second pad connected to the second via, wherein a trace of the first circuit pattern overlaps at least one of the first pad and the second pad in a thickness direction.

In addition, an interval between the first pad and the second pad is in a range of 2 μm to 30 μm.

In addition, the second circuit pattern includes a trace, and the trace of the second circuit pattern is an area on a lower surface of the insulating layer except for an area between the first pad and the second pad of the second circuit pattern. is placed on

In addition, the width of the upper surface of each of the first via and the second via is smaller than the width of the lower surface.

In addition, upper surfaces of the first via, the second via, and the first circuit pattern each include a curved surface.

In addition, an upper surface of each of the first via, the second via, and the first circuit pattern is lower than an upper surface of the insulating layer.

It also includes a first surface treatment layer disposed on upper surfaces of the first via and the second via.

In addition, a pitch corresponding to the distance from the center of the first via to the center of the second via is 90 µm or less.

In addition, the insulating layer is composed of a plurality of layers, and the first via and the second via are disposed in a first outermost insulating layer disposed on an outermost side of the plurality of insulating layers, and the first circuit pattern is buried in an upper surface of the first outermost insulating layer, and the second circuit pattern is disposed in a lower surface of the first outermost insulating layer.

The first circuit pattern may include a first pad overlapping the first via in a thickness direction and a second pad overlapping the second via in a thickness direction, and a width of the first pad may include: The width of the upper surface of the first via is smaller than the width of the upper surface of the second via, and the width of the second pad is smaller than the width of the upper surface of the second via.

In addition, the first via is disposed to surround a side surface of the first pad of the first circuit pattern, and the second via is disposed to surround a side surface of the first pad of the first circuit pattern.

On the other hand, the package substrate according to the embodiment includes an insulating layer; a first circuit pattern buried in an upper surface of the insulating layer; a second circuit pattern disposed on a lower surface of the insulating layer opposite to the upper surface; a via passing through the insulating layer and electrically connected to the first circuit pattern and the second circuit pattern; a first surface treatment layer disposed on an upper surface of the via; a first adhesive part disposed on an upper surface of the first surface treatment layer; a chip disposed on the first adhesive part; a molding layer disposed on an upper surface of the insulating layer and molding the chip, an upper surface of the via is positioned higher than a lower surface of the first circuit pattern, and the via has a first via and a width with the first via A pitch corresponding to a distance from a center of the first via to a center of the second via including second vias spaced apart in the direction is 100 μm or less.

In addition, the insulating layer is composed of a plurality of layers, and the first via and the second via are disposed in a first outermost insulating layer disposed at an outermost side among the plurality of insulating layers.

In addition, the chip includes a first chip and a second chip disposed to be spaced apart from each other in a width direction, the first chip corresponding to a central processor (CPU), the second chip to the graphic processor (GPU) respond

A circuit board according to an embodiment includes a via disposed in a region on which a chip is mounted. The via includes a first surface having a first width and a second surface having a second width greater than the first width. Further, in the embodiment, the first surface of the via is used as a mounting pad without forming an additional pad on the first surface of the via. Accordingly, in the embodiment, since the via is used without separately forming a mounting pad that affects the pitch, the pitch, which is the distance between the centers of neighboring vias, can be significantly reduced compared to the comparative example. In addition, in the embodiment, since the pitch can be reduced compared to the comparative example, more chips can be mounted in a limited space, thereby reducing the volume of the circuit board and furthermore the volume of the package board.

In addition, in the embodiment, as the pitch decreases as described above, the length of the transmission line connecting between the terminals of the chip mounted on the circuit board can be reduced, and thus the communication performance can be improved by minimizing the signal transmission loss. have.

In addition, in the embodiment, the pad of the first circuit pattern is embedded in the first surface of the via while using the first surface of the via as a chip mounting pad for chip mounting. Accordingly, in the embodiment, the easiness and reliability of the manufacturing process for forming the via may be improved. For example, according to the second exemplary embodiment, the position where the via is to be arranged can be accurately identified using the pad of the first circuit pattern, and thus the accuracy of the formation position of the via can be improved. Furthermore, in an embodiment, as the pad of the first circuit pattern forms a part of the via, a dimple problem that may occur when the via is formed can be solved, and thus the reliability of the via can be improved.

1A is a diagram illustrating a circuit board according to a first comparative example.
1B is a diagram illustrating a circuit board according to a second comparative example.
1C is a plan view of a mounting pad in Comparative Example 1 and Comparative Example 2;
1D is a diagram for explaining the pitch of pads in Comparative Examples 1 and 2;
2A is a diagram illustrating a circuit board according to a first embodiment.
FIG. 2B is a diagram for explaining a pitch of a via used as a mounting pad in FIG. 2A .
3 is a diagram illustrating a circuit board according to a first modified example.
4A is a diagram illustrating a circuit board according to a second modified example.
FIG. 4B is a diagram for explaining a pitch of vias used as mounting pads in FIG. 4A .
5 is a diagram illustrating a circuit board according to a third modified example.
6A is a diagram illustrating a modified example of a circuit board according to an embodiment.
6B is a SAM diagram showing a trace in an actual product corresponding to FIG. 6A.
7A to 7I are diagrams for explaining the manufacturing method of the circuit board shown in FIG. 2A in order of process.
8 is a diagram illustrating a circuit board according to a second embodiment.
9A to 9E are diagrams for explaining the manufacturing method of the circuit board shown in FIG. 8 in order of process.
10 is a view showing a circuit board of a modified example of the second embodiment.
11 is a view showing a package substrate according to an embodiment.

Hereinafter, the embodiments disclosed in the present specification will be described in detail with reference to the accompanying drawings, but the same or similar components are assigned the same reference numerals regardless of reference numerals, and redundant description thereof will be omitted. The suffixes "module" and "part" for components used in the following description are given or mixed in consideration of only the ease of writing the specification, and do not have distinct meanings or roles by themselves. In addition, in describing the embodiments disclosed in the present specification, if it is determined that detailed descriptions of related known technologies may obscure the gist of the embodiments disclosed in the present specification, the detailed description thereof will be omitted. In addition, the accompanying drawings are only for easy understanding of the embodiments disclosed in this specification, and the technical idea disclosed herein is not limited by the accompanying drawings, and all changes included in the spirit and scope of the present invention , should be understood to include equivalents or substitutes.

Terms including ordinal numbers such as first, second, etc. may be used to describe various elements, but the elements are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another.

When a component is referred to as being “connected” or “connected” to another component, it may be directly connected or connected to the other component, but it is understood that other components may exist in between. it should be On the other hand, when it is said that a certain element is "directly connected" or "directly connected" to another element, it should be understood that the other element does not exist in the middle.

The singular expression includes the plural expression unless the context clearly dictates otherwise.

In the present application, terms such as “comprises” or “have” are intended to designate that a feature, number, step, operation, component, part, or combination thereof described in the specification exists, but one or more other features It is to be understood that this does not preclude the possibility of the presence or addition of numbers, steps, operations, components, parts, or combinations thereof.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

- Comparative Example -

Prior to the description of the embodiment, a comparative example compared with the circuit board of the embodiment of the present application will be described.

1A is a view showing a circuit board according to a first comparative example, FIG. 1B is a view showing a circuit board according to a second comparative example, and FIG. 1C is a plan view of a mounting pad in the first comparative example and the second comparative example, , FIG. 1D is a diagram for explaining the pitch of pads of Comparative Examples 1 and 2;

A pitch limit of a pad of a circuit board according to a comparative example will be described with reference to FIGS. 1A to 1D .

1A and 1D , in Comparative Examples 1 and 2, the pitch between adjacent pads exceeds 100 μm due to design limitations of vias and pads. The circuit boards in Comparative Examples 1 and 2 have an ETS (Embedded Trace Substrate) structure.

Circuit boards according to the first and second comparative examples include an insulating layer 10 , a first circuit pattern 20 , a second circuit pattern 30 , a via 40 , a first protective layer 50 , and a second A protective layer 60 is included.

The insulating layer 10 includes a prepreg. For example, the insulating layer 10 includes a resin and reinforcing fibers in the resin.

The first circuit pattern 20 is disposed on the first surface of the insulating layer 10 .

In addition, the second circuit pattern 30 is disposed on the second surface of the insulating layer 10 . At this time, one of the first circuit pattern 20 and the second circuit pattern 30 has an ETS structure buried in the surface of the insulating layer 10 .

That is, the first circuit pattern 20 is an ETS pattern buried in the first surface of the insulating layer 10 .

In addition, the second circuit pattern 30 has a structure protruding from the second surface of the insulating layer 10 .

The first circuit pattern 20 and the second circuit pattern 30 include pads and traces, respectively. The pad is a part on which a chip is mounted while being connected to a via, or an adhesive part (not shown) connected to the main board of an external substrate is disposed. The trace is a signal line extending long from the pad.

The via 40 is disposed through the insulating layer 10 . One end of the via 40 is connected to the first circuit pattern 20 , and the other end opposite to the one end is connected to the second circuit pattern 30 .

The first protective layer 50 and the second protective layer 60 are respectively disposed on the first and second surfaces of the insulating layer 10 . The first protective layer 50 is disposed on the first surface of the insulating layer 10 and has an opening exposing at least a portion of the surface of the first circuit pattern 20 . In addition, the second protective layer 60 is disposed on the second surface of the insulating layer 10 and has an opening exposing at least a portion of the surface of the second circuit pattern 30 .

In this case, one of the first circuit pattern 20 and the second circuit pattern 30 includes a mounting part on which a chip is mounted, and the other includes a terminal part connected to the main board of an external board. For example, one of the first circuit pattern 20 and the second circuit pattern 30 is used as a mounting pad on which a chip is mounted, and the other is used as a terminal pad connected to the main board.

Specifically, the circuit board of the first comparative example of FIG. 1A uses the third circuit pattern 30 as the mounting pad, and the circuit board of the second comparative example of FIG. 1B uses the second circuit pattern 20 as described above. It is used as a mounting pad.

In this case, in Comparative Examples 1 and 2, there is a limit to the size of the mounting pad according to the size of the via, so that the pitch, which is the distance between the centers of the neighboring mounting pads, exceeds 100 μm.

That is, the insulating layer 10 is formed of a prepreg. Accordingly, in order to form a via hole in the insulating layer 10, laser processing should be performed. At this time, due to the characteristics of general laser processing, the via 40 has a size greater than a certain level.

For example, the width of the first surface and the width of the second surface of the via 40 are different by filling the inside of the via hole formed by laser processing. For example, the width w2 of the first surface of the via 40 is smaller than the width w1 of the second surface. In addition, the first comparative example uses a relatively wide second circuit pattern 30 connected to the second surface of the via 40 as a mounting pad. In addition, the second comparative example uses a relatively narrow first circuit pattern 20 connected to the first surface of the via 40 as a mounting pad.

The width w1 of the second surface of the via 40 has a minimum of 45 μm or more due to the limitation of the laser process. In addition, the width w2 of the first surface of the via 40 has a width of 40 μm or more, which is 80% of the width w1 of the second surface.

In addition, the width w3 of the pad of the second circuit pattern 30 in direct contact with the second surface of the via 40 is at least 70 μm. That is, the pad of the second circuit pattern 30 has a width greater than or equal to the width w1 of the second surface of the via 40 . In addition, the width w4 of the pad of the first circuit pattern 20 in direct contact with the first surface of the via 40 is at least 67 μm. That is, the pad of the first circuit pattern 20 has a width greater than or equal to the width w2 of the first surface of the via 40 .

Accordingly, in the pad of the second circuit pattern 30 , the width (w5=(w3-w1)/2) of the portion affecting the pitch with respect to the neighboring pad is at least 12.5 μm. That is, the horizontal straight line distance w5 in the width direction from one end of the second surface of the via 40 to one end of the pad of the second circuit pattern 30 is at least 12.5 μm. Accordingly, in the pad of the first circuit pattern 20 , the width (w6=(w4-w2)/2) of the portion affecting the pitch with respect to the neighboring pad is at least 13.5 μm. That is, the horizontal straight line distance w5 in the width direction from one end of the first surface of the via 40 to the one end of the pad of the first circuit pattern 20 is at least 12.5 μm. In addition, a horizontal straight line distance (w7=(w4-w1)/2) in the width direction from one end of the second surface of the via 40 to one end of the pad of the first circuit pattern 20 is at least 11 μm level.

Accordingly, when the second circuit pattern 30 is used as a mounting pad, the spacing between adjacent mounting pads is at least 8 μm, and thus has a pitch of about 78 μm.

Also, when the first circuit pattern 20 is used as a mounting pad, a pitch of about 75 μm may be taken in consideration of the spacing between the neighboring mounting pads.

However, according to the recent high specification, at least one trace exists between the adjacent mounting pads, and the number of the patches is increased by the traces.

That is, when any one of the first circuit pattern 20 and the second circuit pattern 30 is used as a pad, at least one trace is formed between the first pad PAD1 and the second pad PAD2 as shown in FIG. 1C . (TRACE) must be located.

For example, when the second circuit pattern 30 is used as a mounting pad, at least one trace 31 exists between adjacent pads. The trace 31 is a signal line connecting the pad and the pad of the second circuit pattern 30 . In this case, the trace 31 has a line width w8 of at least 7 μm and a spacing w9 of at least 8 μm.

In addition, when the first circuit pattern 20 is used as a pad, at least one trace 21 exists between adjacent pads. The trace 21 is a signal line connecting the pad and the pad of the first circuit pattern 20 . In this case, the trace 21 has a line width w8' of at least 7 µm and a spacing w9' of at least 8 µm.

Accordingly, as in (a) of FIG. 1D , when the second circuit pattern 30 is used as a mounting pad, the width of the first pad PAD1 and the second pad PAD2 and the line width of the trace 31 . and a gap between them, the pitch p1 between the first pad PAD1 and the second pad PAD2 exceeds 110 μm.

Also, as shown in (b) of FIG. 1D , when the first circuit pattern 20 is used as a mounting pad, the width of the first pad PAD1 and the second pad PAD2 and the line width of the trace 31 . and a gap between them, the pitch p2 between the first pad PAD1 and the second pad PAD2 exceeds 100 μm.

As described above, in the comparative example, the pitch between the center of the first pad PAD1 and the center of the second pad PAD2 exceeds at least 100 μm, and thus it is difficult to mount a plurality of chips within a limited space. can For example, as the pitch increases, there is a problem in that the width in the width direction of the circuit board required to mount the chip increases. In addition, an increase in the pitch means an increase in signal transmission lines between adjacent pads, and there is a problem in that a signal transmission loss increases as the signal transmission lines increase.

In addition, as the performance of electric/electronic products is progressing recently, techniques for attaching a larger number of packages to a substrate having a limited size are being studied, and accordingly, miniaturization of circuit patterns is required. However, in the case of the package substrate using the circuit board of the comparative example, there is a limit to the miniaturization of the pad pitch. In addition, as functions processed by an application processor (AP) increase in recent years, it is becoming difficult to implement them in a single chip. However, it is difficult to mount two application processors (APs) having different functions in a limited space using the circuit board provided in the comparative example.

The embodiment is intended to solve the problems of the comparative example, and the pitch of the mounting pad can be reduced to 100 μm or less, preferably 90 μm or less, and more preferably 80 μm or less. Furthermore, in the embodiment, it is possible to mount a plurality of chips on one circuit board according to the reduction of the pitch. For example, in the embodiment, it is possible to provide a circuit board having a new structure on which a plurality of processor chips or memory chips having different functions can be mounted on a single circuit board, and a package board including the same.

-Electronic device-

Prior to the description of the embodiment, an electronic device including the package substrate of the embodiment will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and/or electrically connected to various components. For example, the main board may be connected to the package substrate of the embodiment. Various chips may be mounted on the package substrate. Broadly, the package substrate includes a volatile memory (eg, DRAM), a non-volatile memory (eg, ROM), a memory chip such as a flash memory, a central processor (eg, CPU), a graphics processor (eg, GPU), An application processor chip such as a digital signal processor, an encryption processor, a microprocessor, and a microcontroller, and a logic chip such as an analog-to-digital converter and an ASIC (application-specific IC) may be mounted.

In addition, the embodiment provides a circuit board and a package board capable of refining the pitch of the pads and capable of mounting at least two different types of chips on a single board according to the miniaturization of the pitch. Furthermore, the embodiment provides a circuit board and a package substrate in which more traces than in the comparative example can be disposed between mounting pads having a smaller pitch than in the comparative example.

In this case, the electronic device includes a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, and a computer. ), a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, and the like. However, the present invention is not limited thereto, and may be any other electronic device that processes data in addition to these.

-First embodiment-

Hereinafter, a circuit board according to an embodiment and a package board including the same will be described.

FIG. 2A is a diagram illustrating a circuit board according to the first embodiment, and FIG. 2B is a diagram for explaining a pitch of vias used as mounting pads in FIG. 2A .

Referring to FIG. 2A , the circuit board 100 provides a mounting space in which at least one chip can be mounted. The number of chips mounted on the circuit board 100 may be one, alternatively, two, or alternatively, three or more. For example, one processor chip may be mounted on the circuit board 100 , and at least two processor chips having different functions may be mounted differently. Alternatively, one processor chip and one memory chip may be mounted on the circuit board 100 . This may be mounted, otherwise, at least two processor chips and at least one memory chip having different functions may be mounted.

The circuit board 100 includes an insulating layer 110 . The insulating layer 110 has a structure of at least one layer. At this time, although FIG. 2A shows that the circuit board 100 has a one-layer structure based on the number of layers of the insulating layer 110 , the present invention is not limited thereto. For example, the circuit board 100 may have a stacked structure of two or more layers based on the number of layers of the insulating layer 110 . However, hereinafter, the circuit board 100 will be described as having a one-layer structure based on the number of layers of the insulating layer 110 .

The insulating layer 110 may include a prepreg (PPG, prepreg). The prepreg may be formed by impregnating a fiber layer in the form of a fabric sheet, such as a glass fabric woven with glass yarn, with an epoxy resin, and then performing thermocompression. However, the embodiment is not limited thereto, and the prepreg constituting the insulating layer 110 may include a fiber layer in the form of a fabric sheet woven with carbon fiber yarn.

The insulating layer 110 may include a resin and a reinforcing fiber disposed in the resin. The resin may be an epoxy resin, but is not limited thereto. The resin is not particularly limited to the epoxy resin, for example, one or more epoxy groups may be included in the molecule, and alternatively, two or more epoxy groups may be included. Alternatively, four or more epoxy groups may be included. In addition, the resin of the insulating layer 110 may include a naphthalene group, for example, may be an aromatic amine type, but is not limited thereto. For example, the resin is a bisphenol A type epoxy resin, a bisphenol F type epoxy resin, a bisphenol S type epoxy resin, a phenol novolak type epoxy resin, an alkylphenol novolak type epoxy resin, a biphenyl type epoxy resin, an aralkyl type epoxy resin Resin, dicyclopentadiene type epoxy resin, naphthalene type epoxy resin, naphthol type epoxy resin, epoxy resin of condensate of phenol and aromatic aldehyde having phenolic hydroxyl group, biphenyl aralkyl type epoxy resin, fluorene type epoxy resin resins, xanthene-type epoxy resins, triglycidyl isocyanurate, rubber-modified epoxy resins, phosphorous-based epoxy resins, and the like, and naphthalene-based epoxy resins, bisphenol A-type epoxy resins, and phenol novolac epoxy resins , cresol novolac epoxy resins, rubber-modified epoxy resins, and phosphorous-based epoxy resins. In addition, the reinforcing fiber is glass fiber, carbon fiber, aramid fiber (eg, aramid-based organic material), nylon (nylon), silica (silica)-based inorganic material or titania-based inorganic material is used. can The reinforcing fibers may be arranged in the resin to cross each other in a planar direction.

Meanwhile, the glass fiber, carbon fiber, aramid fiber (eg, aramid-based organic material), nylon, silica-based inorganic material or titania-based inorganic material may be used.

The insulating layer 110 may have a thickness T1 in the range of 10 μm to 60 μm. For example, the insulating layer 110 may have a thickness T1 in the range of 15 μm to 55 μm. For example, the insulating layer 110 may have a thickness T1 in the range of 20 μm to 50 μm. The thickness T1 of the insulating layer 110 may mean a distance between circuit patterns respectively disposed on the surface thereof. For example, the thickness T1 of the insulating layer 110 is a straight line between the second surface or lower surface of the first circuit pattern 120 and the first surface or upper surface of the second circuit pattern 130 , which will be described below. It can mean distance.

A first circuit pattern 120 is disposed on the first surface of the insulating layer 110 . In addition, a second circuit pattern 130 is disposed on the second surface of the insulating layer 110 . In this case, the circuit board 100 may be manufactured using an Embedded Trace Substrate (ETS) method. Accordingly, any one of the first circuit pattern 120 and the second circuit pattern 130 included in the circuit board 100 may have an ETS structure. For example, in an embodiment, any one of the first circuit pattern 120 and the second circuit pattern 130 may have a structure buried in the surface of the insulating layer 110 , and the other of the first circuit pattern 120 and the second circuit pattern 130 may have a structure buried in the surface of the insulating layer 110 . 110) may have a structure protruding from the surface.

In the embodiment, it is assumed that the first circuit pattern 120 has a buried structure corresponding to the ETS structure and the second circuit pattern 130 has a protruding structure.

The first circuit pattern 120 is disposed on the first surface of the insulating layer 110 . The first surface may be a top surface of the insulating layer 110 . The first circuit pattern 120 may have a structure buried in the first surface of the insulating layer 110 .

The first circuit pattern 120 may include a trace 121 . In this case, the traces 121 of the first circuit pattern 120 may be positioned substantially on the same plane as the vias 140 to be described later. For example, the first circuit pattern 120 may not be disposed on the top surface of the via 140 , but may be disposed on the side of the via 140 . That is, a typical circuit pattern includes pads and traces. Then, the pad is disposed on the top surface of the via, and the trace is disposed on the side of the pad. Accordingly, the general trace is positioned higher than the via.

On the other hand, in the embodiment, the via 140 is used as a mounting pad for chip mounting. Accordingly, the first circuit pattern 120 in the embodiment may not include a mounting pad for mounting a chip.

Accordingly, the first surface or top surface of the first circuit pattern 120 may be positioned on the same plane as the first surface or top surface of the via 140 . That is, the lower surface of the general first circuit pattern is positioned on the same plane as the upper surface of the via. On the other hand, in the embodiment, the via 140 is used as a mounting pad, and accordingly, the top surface of the first circuit pattern 120 and the top surface of the via 140 may be located on the same plane.

The first circuit pattern 120 may include at least one metal selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). It may be formed of a material. In addition, the first circuit pattern 120 is selected from among gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding strength. It may be formed of a paste or solder paste including at least one metal material. Preferably, the first circuit pattern 120 may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

The first circuit pattern 120 may have a thickness in a range of 5 μm to 20 μm. For example, the first circuit pattern 120 may have a thickness in a range of 6 μm to 17 μm. The first circuit pattern 120 may have a thickness in a range of 7 μm to 13 μm. When the thickness of the first circuit pattern 120 is less than 5 μm, the resistance of the first circuit pattern 120 may increase. When the thickness of the first circuit pattern 120 exceeds 20 μm, the line width of the trace 121 constituting the first circuit pattern 120 increases, and thus the overall volume of the circuit board 100 decreases. can increase

The trace 121 of the first circuit pattern 120 may have a specific line width W6 and a specific interval W7. For example, the line width W6 of the trace 121 of the first circuit pattern 120 may range from 6 μm to 20 μm. For example, the line width W6 of the trace 121 of the first circuit pattern 120 may be in a range of 7 μm to 15 μm. For example, the line width W6 of the trace 121 of the first circuit pattern 120 may be in a range of 8 μm to 12 μm. Also, the interval W7 between the traces of the first circuit pattern 120 may be in a range of 6 μm to 20 μm. For example, the interval W7 between the traces of the first circuit pattern 120 may be in a range of 7 μm to 15 μm. For example, the interval W7 between the traces of the first circuit pattern 120 may be in a range of 8 μm to 12 μm. Here, the spacing W7 may mean a spacing between a plurality of traces constituting the first circuit pattern 120 . Also, the gap W7 may mean a gap between the trace 121 constituting the first circuit pattern 120 and the via 140 used as a mounting pad in the embodiment.

At least one trace 121 of the first circuit pattern 120 may be positioned between a plurality of vias 140 used as mounting pads. That is, in the embodiment, the plurality of vias 140 serve as mounting pads. In this case, the mounting pads may be electrically connected to each other. For example, at least one trace may be positioned between the mounting pads. That is, as shown in FIG. 1C , a trace may be disposed between neighboring pads or between the neighboring pads to connect different pads. However, since the trace in FIG. 1C is connected to the pad of the first circuit pattern 20 or the second circuit pattern 30 , the trace 121 in the embodiment uses the via 140 as a pad. , may be connected to a side surface of the via 140 .

The second circuit pattern 130 may be disposed on the second surface or the lower surface of the insulating layer 110 . For example, the second circuit pattern 130 may be disposed on the surface of the insulating layer 110 , opposite to the surface on which the first circuit pattern 120 is disposed. However, the first circuit pattern 120 has an ETS structure buried in the first surface or the top surface of the insulating layer 110 , whereas the second circuit pattern 130 is the second circuit pattern of the insulating layer 110 . It has a structure that protrudes downward from two sides or the lower surface.

The second circuit pattern 130 may be connected to the via 140 .

The second circuit pattern 130 may include a pad and a trace. For example, the second circuit pattern 130 may include pads 131 and 132 connected to the via 140 . In addition, the second circuit pattern 130 may include traces (not shown) connected to the pads 131 and 132 .

The pads 131 and 132 of the second circuit pattern 130 may function as terminals connected to the main board of the electronic device. For example, the pads 131 and 132 of the second circuit pattern 130 may be terminal pads on which solder balls are disposed to be connected to the main board of the electronic device.

The pads 131 and 132 of the second circuit pattern 130 may be connected to the second surface or the lower surface of the via 140 . Specifically, the first surface or upper surface of the pads 131 and 132 of the second circuit pattern 130 may directly contact the second surface or lower surface of the via 140 . Traces of the second circuit pattern 130 may not be disposed between the pads 131 and 132 . That is, in the embodiment, although the second circuit pattern 130 includes pads 131 and 132 and traces, the traces of the second circuit pattern 130 are the second surface of the insulating layer 110 . Alternatively, on the lower surface, it may be disposed avoiding the area between the pads 131 and 132 . Accordingly, in the embodiment, the gap between the pads 131 and 132 of the second circuit pattern 130 may be minimized, and accordingly, the pitch of the mounting pads of the circuit board (specifically, the pitch of the via) may be minimized. can do. For example, in the embodiment, since traces are not disposed between the pads 131 and 132 of the second circuit pattern 130, the pitch between the vias 140 functioning as mounting pads is set to 100 μm or less, and further It is 90 micrometers or less, Furthermore, it can be set as 80 micrometers or less.

The gap W4 between the pads 131 and 132 of the second circuit pattern 130 may be 30 μm or less. For example, the gap W4 between the pads 131 and 132 of the second circuit pattern 130 may be 20 μm or less. For example, the gap W4 between the pads 131 and 132 of the second circuit pattern 130 may be 10 μm or less. For example, the gap W4 between the pads 131 and 132 of the second circuit pattern 130 may be 7 μm or less. For example, an interval between the pads 131 and 132 of the second circuit pattern 130 may be 5 μm or less. For example, an interval between the pads 131 and 132 of the second circuit pattern 130 may be 2 μm or more.

Specifically, the gap W4 between the pads 131 and 132 of the second circuit pattern 130 may be in a range of 2 μm to 30 μm. For example, the gap W4 between the pads 131 and 132 of the second circuit pattern 130 may be in a range of 2.5 μm to 20 μm. For example, an interval between the pads 131 and 132 of the second circuit pattern 130 may be in a range of 2.5 μm to 7 μm. Preferably, the spacing between the pads 131 and 132 of the second circuit pattern 130 is smaller than the line width or spacing of the traces 121 of the first circuit pattern 120 or the traces of the second circuit pattern 130 . can

If the interval W4 between the pads 131 and 132 of the second circuit pattern 130 is less than 2 μm, a reliability problem in which the pads 131 and 132 are connected to each other may occur. If the interval W4 between the pads 131 and 132 of the second circuit pattern 130 is less than 2 μm, a problem may occur in communication performance due to signal interference between the pads 131 and 132 . When the interval W4 of the second circuit pattern 130 is greater than 30 μm, it may be difficult to adjust the pitch of the vias 140 by the pads 131 and 132 to 100 μm or less. That is, when the interval W4 between the second circuit patterns 130 is greater than 30 μm, the overall volume of the circuit board 100 may increase according to an increase in the pitch of the vias 140 .

The pads 131 and 132 of the second circuit pattern 130 may overlap the traces 121 of the first circuit pattern 120 in a thickness direction (or a vertical direction or a z-axis direction in a three-dimensional coordinate system). .

That is, the second circuit pattern 130 has a first pad 131 and a second pad 132 spaced apart in the width direction (or the x-axis, y-axis, and a diagonal direction therebetween in a horizontal direction or a three-dimensional coordinate system). ) is included.

And, in an embodiment, the trace of the second circuit pattern 130 is not disposed between the first pad 131 and the second pad 132 of the second circuit pattern 130 . And, in an embodiment, the distance between the first pad 131 and the second pad 132 of the second circuit pattern 130 is minimized so that the pitch of the via 140 is 100 μm or less. . At this time, as described above, the interval between the first pad 131 and the second pad 132 of the second circuit pattern 130 is set to be smaller than the line width or interval of the trace 121 , and accordingly, the first circuit At least a portion of the trace 121 of the pattern 120 may overlap the first pad 131 or the second pad 132 in a thickness direction. For example, at least a portion of the trace 121 of the first circuit pattern 120 may overlap the first pad 131 in the thickness direction. Also, at least a portion of the trace 121 of the first circuit pattern 120 may overlap the second pad 132 in a thickness direction. In addition, at least a portion of the trace 121 of the first circuit pattern 120 may overlap the first pad 131 in the thickness direction, and another portion may overlap the second pad 132 in the thickness direction. have.

Widths of the first pad 131 and the second pad 132 of the second circuit pattern 130 may correspond to each other. For example, the width W3 of the first pad 131 and the second pad 132 may be 60 μm to 80 μm. For example, the width W3 of the first pad 131 and the second pad 132 may be 65 μm to 75 μm. For example, the width W3 of the first pad 131 and the second pad 132 may be 67 μm to 73 μm.

In an embodiment, the circuit board 100 includes a via 140 passing through the insulating layer 110 . A first surface of the via 140 may be exposed as the first surface of the insulating layer 110 . This may mean that the first circuit pattern 120 is not disposed on the first surface of the via 140 . The via 140 may be connected to the first circuit pattern 120 through a side surface. For example, a side surface of the via 140 may be directly connected to a side surface of the trace 121 of the first circuit pattern 120 .

The via 140 may be formed by forming a via hole (not shown) penetrating the insulating layer 110 and filling the formed via hole with a conductive material.

The via hole may be formed by any one of mechanical, laser, and chemical processing. When the via hole is formed by machining, methods such as milling, drilling, and routing can be used, and when formed by laser processing, UV or CO ₂ laser method is used. In the case of being formed by chemical processing, at least one insulating layer among the plurality of insulating layers may be opened by using a chemical containing aminosilane, ketones, or the like.

On the other hand, the processing by the laser is a cutting method that melts and evaporates a part of the material by concentrating optical energy on the surface to take a desired shape, and complex formation by a computer program can be easily processed. Even difficult composite materials can be machined.

In addition, the processing by the laser can have a cutting diameter of at least 0.005 mm, and has a wide advantage in a range of possible thicknesses.

As the laser processing drill, it is preferable to use a YAG (Yttrium Aluminum Garnet) laser, a CO ₂ laser, or an ultraviolet (UV) laser. The YAG laser is a laser that can process both the copper foil layer and the insulating layer, and the CO ₂ laser is a laser that can process only the insulating layer.

When the via hole is formed, the via 140 may be formed by filling the interior of the via hole with a conductive material. The metal material forming the via 140 may be any one material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). , The conductive material may be filled using any one or a combination of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjetting and dispensing.

A thickness T2 of the via 140 may be greater than a thickness T1 of the insulating layer 110 . Preferably, the thickness T2 of the via 140 may correspond to the sum of the thickness T1 of the insulating layer 110 and the thickness of the first circuit pattern 120 . For example, the thickness of the via in the comparative example corresponds to the thickness of the circuit pattern. On the other hand, in the embodiment, the thickness T2 of the via 140 may be greater than the thickness T1 of the insulating layer 110 .

The via 140 includes a first surface and a second surface. For example, a first surface of the via 140 may be an upper surface, and a second surface of the via 140 may be a lower surface.

The first surface of the via 140 may be positioned on the same plane as the first surface of the first circuit pattern 120 . The second surface of the via 140 may directly contact upper surfaces of the pads 131 and 132 of the second circuit pattern 130 .

At least a portion of a side surface of the via 140 may directly contact the first circuit pattern 120 . For example, at least a portion of a side surface of the via 140 may directly contact a side surface of the trace 121 of the first circuit pattern 120 .

The width W1 of the first surface of the via 140 may be smaller than the width W2 of the second surface. For example, the via 140 may have a trapezoidal shape in which the width of the first surface and the second surface are different from each other. And, in the embodiment, a portion having a relatively small width on the first surface and the second surface of the via 140 is used as a mounting pad for chip mounting. For example, as the via 140 has a trapezoidal shape as described above, the spacing between adjacent vias may be different from each other on the first surface side (or upper side) and the second surface side (or lower side).

For example, the via 140 includes a first via 141 and a second via 142 that are adjacent to each other. In this case, the spacing between the first via 141 and the second via 142 may be different from each other on the upper side and the lower side. For example, the width of the first surface of each of the first via 141 and the second via 142 is smaller than the width of the second surface. Accordingly, the separation distance between the first via 141 and the second via 142 on the first surface side is greater than the separation distance on the second surface side. That is, the spacing between the first via 141 and the second via 142 may be greatest on the first surface side and gradually decrease toward the second surface side.

Accordingly, in the embodiment, the first surfaces of the first via 141 and the second via 142 having relatively small widths are used as mounting pads. Accordingly, in the embodiment, compared to using the second surface of the first via 141 and the second via 142 as a mounting pad, the space between the first via 141 and the second via 142 is may increase, and thus the distance between the traces 121 of the first circuit pattern 120 that may be disposed between the first via 141 and the second via 142 may be increased, The number of traces 121 may be increased.

The sizes of the first via 141 and the second via 142 may correspond to each other. For example, the width W1 of the first surface of the first via 141 and the second via 142 may be 20 μm to 40 μm. For example, the width W1 of the first surface of the first via 141 and the second via 142 may be 22 μm to 37 μm. For example, the width W1 of the first surface of the first via 141 and the second via 142 may be 25 μm to 35 μm.

The width W1 of the first surface of the first via 141 and the second via 142 may be less than 20 μm. That is, the first via 141 and the second via 142 are formed by forming a via hole in the insulating layer 110 formed of prepreg using a laser, and filling the formed via hole with a metal material. is formed In this case, it may be difficult to form the width of the first surface of the via hole to be 20 μm or less using the laser. For example, when the width W1 of the first surface of the first via 141 and the second via 142 exceeds 40 μm, a pitch between the vias may increase.

Alternatively, the width W2 of the second surface of the first via 141 and the second via 142 may be 25 μm to 55 μm. For example, the width W2 of the second surface of the first via 141 and the second via 142 may be 27 μm to 50 μm. For example, the width W2 of the second surface of the first via 141 and the second via 142 may be 30 μm to 47 μm.

That is, the pitch of the general mounting pad is determined by the width of the via and the width of the mounting pad having a width greater than the width of the via. In addition, at least one trace should be disposed between the mounting pads. Accordingly, in the comparative example, the pitch of the mounting pads exceeds 100 μm due to the width of the mounting pad and the width of the trace. Unlike this, in the embodiment, the mounting pad for mounting the chip is not separately formed, and a portion of the via is used as the mounting pad. Accordingly, in the embodiment, since the via itself is used as a mounting pad, the pitch of the mounting pad only needs to consider the width of the via, and thus the pitch of the mounting pad can be reduced compared to the comparative example.

In other words, the structures of the first circuit pattern 120 , the second circuit pattern 130 , and the via 140 illustrated in FIG. 2A are summarized as follows.

In an embodiment, the via 140 includes a first via 141 and a second via 142 that are spaced apart from each other in the width direction. In this case, each of the first via 141 and the second via 142 has a thickness greater than that of the insulating layer 110 . For example, each of the first via 141 and the second via 142 may have a thickness obtained by adding the thickness of the insulating layer 110 to the thickness of the first circuit pattern 120 . The first surface or top surface of the first via 141 and the second via 142 may be located on the same plane as the first surface or top surface of the first circuit board 100 . The first via 141 and the second via 142 may be connected to the first circuit pattern 120 through side surfaces. That is, side surfaces of the first via 141 and the second via 142 may be connected to the side surface of the first circuit pattern 120 .

That is, the first circuit pattern 120 may include at least one trace 121 disposed between the first via 141 and the second via 142 . Accordingly, one side of the trace 121 may be disposed to directly face the side of the first via 141 . In addition, the other side of the trace 121 may be disposed to directly face the side of the second via 142 .

In addition, the second circuit pattern 130 includes a first pad 131 connected to the first via 141 and a second pad 132 connected to the second via 142 . In this case, although the second circuit pattern 130 includes traces, it may be disposed while avoiding a region between the first pad 131 and the second pad 132 . Accordingly, in the embodiment, the gap between the first pad 131 and the second pad 132 may be minimized. In the structure of the circuit board of the general comparative example, the first pad and the second pad do not overlap the traces of the first circuit pattern in the thickness direction. For example, in the comparative example, the first pad and the second pad are connected to the pads of the first circuit pattern in the thickness direction. In contrast, in the embodiment, since the mounting pad of the first circuit pattern 120 is removed and the first via 141 and the second via 142 are used as the mounting pads, in the comparative example, the mounting pads are disposed More traces can be placed in the area where they were. Accordingly, in an embodiment, the trace 121 of the first circuit pattern 120 overlaps with at least one of the first pad 131 and the second pad 132 of the second circuit pattern 130 in the thickness direction. can be

With the above structure, in the embodiment, the first via 141 and the second via 142 themselves are used as the mounting pad, so that the pitch of the mounting pad can be reduced.

A first passivation layer 150 is disposed on a first surface of the insulating layer 110 , and a second passivation layer 155 is disposed on a second surface of the insulating layer 110 .

The first passivation layer 150 and the second passivation layer 155 may be solder resist. The first passivation layer 150 and the second passivation layer 155 may include at least one opening.

A width W8 of the opening of the first passivation layer 150 may be greater than a width W1 of the first surface of the via 140 . That is, the opening of the first circuit pattern 120 has a greater width than the first surface of the via 140 , and thus the entire first surface of the via 140 may be exposed. However, this is only an example, and the width W8 of the opening of the first passivation layer 150 may be smaller than the width of the first surface of the via 141 . At least a portion of the first surface may be covered by the first passivation layer 150 .

The width of the opening of the second passivation layer 155 may be smaller than the width W3 of the first pad 131 and the second pad 132 of the second circuit pattern 130 . Accordingly, at least a portion of the second surface or lower surface of the first pad 131 and the second pad 132 of the second circuit pattern 130 may be covered by the second passivation layer 155 . However, this is only an example, and the width of the opening of the second protective layer 155 may be greater than the width of the first pad 131 and the second pad 132 of the second circuit pattern 130 . Accordingly, the entire area of the second surface or lower surface of the first pad 131 and the second pad 132 may be exposed through the opening of the second passivation layer 155 .

In an embodiment, the circuit board 100 includes a surface treatment layer. The surface treatment layer may be formed to increase solderability while preventing corrosion and oxidation of the pad. In this case, the surface treatment layer is generally disposed on the first circuit pattern and the second circuit pattern. On the other hand, in an embodiment, the first circuit pattern does not include a mounting pad, and the via functions as a mounting pad. Accordingly, in the embodiment, a surface treatment layer may be disposed on the via.

For example, the first surface treatment layer 160 may be disposed on the first surface of the via 140 exposed through the opening of the first passivation layer 150 .

The first surface treatment layer 160 may be an Organic Solderability Preservative (OSP) layer. Preferably, the first surface treatment layer 160 may be an organic layer formed of an organic material such as benzimidazole coated on the first surface of the via 140 .

Alternatively, the first surface treatment layer 160 may be a plating layer. For example, the first surface treatment layer 160 may include a gold (Au) plating layer electrolessly plated on the first surface of the via 140 . For example, the first surface treatment layer 160 includes a nickel (Ni) plating layer electrolessly plated on the first surface of the via 140 and a gold (Au) plating layer electrolessly plated on the nickel plating layer. can do. For example, the first surface treatment layer 160 may include a nickel (Ni) plating layer electrolessly plated on the first surface of the via 140, a palladium (Pd) plating layer electrolessly plated on the nickel plating layer, and; It may include a gold (Au) plating layer electroless-plated on the palladium plating layer.

In an embodiment, the first surface treatment layer 160 may have a width corresponding to the width of the first surface of the via 140 . That is, as described above, the first surface treatment layer 160 may be selectively formed only on the first surface of the via 140 by electroless plating. Accordingly, in an embodiment, the width of the first surface treatment layer 160 may correspond to the width W1 of the first surface of the via 140 .

Correspondingly, the second surface treatment layer 170 is disposed on the second surface or lower surface of the first pad 131 and the second pad 132 . The second surface treatment layer 170 may be an Organic Solderability Preservative (OSP) layer. Preferably, the second surface treatment layer 170 is an organic layer formed of an organic material such as benzimidazole coated on the second surface or lower surface of the first pad 131 and the second pad 132 . can

Alternatively, the second surface treatment layer 170 may be a plating layer. For example, the second surface treatment layer 170 may include an electroless-plated gold (Au) plating layer. For example, the second surface treatment layer 170 may include an electroless plating nickel (Ni) plating layer and a gold (Au) plating layer electroless plating on the nickel plating layer. For example, the second surface treatment layer 170 may include an electroless plated nickel (Ni) plated layer, a palladium (Pd) plated layer electrolessly plated on the nickel plated layer, and an electroless plated gold (Pd) plated layer on the palladium plated layer. Au) may include a plating layer.

Referring to FIG. 2B , in the embodiment, the pitch P1 between the vias 140 may be 100 μm or less. For example, in the embodiment, the pitch P1 between the vias 140 may be 90 μm or less. For example, in the embodiment, the pitch P1 between the vias 140 may be 80 μm or less.

That is, in the embodiment, the first surface having a relatively small width among the surfaces of the via 140 is used as the mounting pad. Accordingly, the pitch P1, which is a distance between centers of a plurality of adjacent vias, may be reduced compared to the comparative example.

That is, in the embodiment, an additional mounting pad disposed on the via 140 is removed. In addition, in the embodiment, the gap between the first pad 131 and the second pad 132 in contact with the second surface of the via 140 is minimized. At this time, even in the comparative example as in Fig. 1b, it seems that the pitch of the mounting pads composed of the first circuit pattern 20 can be reduced by minimizing the spacing between the plurality of pads of the second circuit pattern 30, In fact, in FIG. 1B , it is difficult to reduce the pitch of the mounting pads formed of the first circuit pattern to 100 μm or less. In this case, at least one trace 21 should be disposed between the mounting pads formed of the first circuit pattern 20 . Accordingly, in the comparative example, the pad of the second circuit pattern 30 is determined by the width of the mounting pads formed of the first circuit pattern 20 and the line width and spacing of the traces 21 disposed therebetween. This is because the gap between them cannot be reduced to less than 30 μm. That is, in the comparative example, the interval between the first pad and the second pad of the second circuit pattern could not be reduced to 30 μm or less, and accordingly, the pitch between the mounting pads formed of the first circuit pattern exceeded 100 μm. did.

In contrast, in the embodiment, the first surface of the via 140 is used as a mounting pad. Accordingly, in the embodiment, even if the distance between the first pad 131 and the second pad 132 of the second circuit pattern 130 is reduced to 30 μm or less (and further reduced to 2 μm), the plurality of A space for arranging at least one trace 121 is sufficiently provided in the space between the vias. Accordingly, in the embodiment, as the distance between the first pad 131 and the second pad 132 of the second circuit pattern 130 is reduced to 30 μm or less while using the via 140 as a mounting pad, The pitch P1 , which is a distance between the centers of the vias 140 , may be lowered to 100 μm or less, further to 90 μm or less, and further to 80 μm or less.

Hereinafter, a modified example of the circuit board according to the first embodiment shown in FIG. 2A will be described.

-Variation example-

3 is a diagram illustrating a circuit board according to a first modified example.

In FIG. 3 , there is a difference in the width of the opening of the first passivation layer 150 and the width of the first surface treatment layer 160 according to FIG. 2A .

The circuit board 100a according to the first modified example corresponds to the circuit board of FIG. 2A , the insulating layer 110 , the first circuit pattern 120 , the second circuit pattern 130 , the via 140 , and the second It includes a protective layer 155 and a second surface treatment layer 170 .

The circuit board 100a includes a first passivation layer 150a. The first protective layer 150a is disposed on the first surface or the upper surface of the insulating layer 110 .

The first passivation layer 150a includes an opening exposing at least a portion of the first surface of the via 140 . In addition, the first passivation layer 150a may be disposed to cover the traces 121 of the first circuit pattern 120 buried in the first surface of the insulating layer 110 .

In this case, the width W8 ′ of the first passivation layer 150a may be smaller than the width W1 of the first surface of the via 140 . For example, the first passivation layer 150a may be disposed to cover at least a portion of the first surface of the via 140 .

In addition, the first surface treatment layer 160a may be disposed on the first surface of the via 140 exposed through the opening of the first passivation layer 150a. Accordingly, the first surface treatment layer 160a may have the same width as the width W8' of the first passivation layer 150a. For example, the first surface treatment layer 160a may be formed using the opening of the first passivation layer 150a as a mask, and thus the width W8 of the opening of the first passivation layer 150a. ') and may be formed with the same width.

4A is a diagram illustrating a circuit board according to a second modified example, and FIG. 4B is a diagram illustrating a pitch of vias used as mounting pads in FIG. 4A .

Referring to FIG. 4A , the circuit board 100b according to the second modified example is different from FIG. 2A in the first circuit pattern 120 .

For example, in FIG. 2A , only one trace 121 of the first circuit pattern 120 is disposed in a space between the first via 141 and the second via 142 . Accordingly, in FIG. 2A , compared to the comparative example, it is possible to reduce the pitch of the mounting pads and increase the spacing between the traces and the mounting pads in the same space.

Alternatively, the circuit board 100b according to the second modification includes the first circuit pattern 120 . In this case, the first circuit pattern 120 includes a trace disposed between the side surface of the first via 141 and the side surface of the second via 142 .

In this case, in an embodiment, in the first circuit pattern 120 , at least two traces may be disposed between the first via 141 and the second via 142 . For example, the first circuit pattern 120 may include a first trace 121a spaced apart from a side surface of the first via 141 by a predetermined distance W7 ′, the second trace 121a and the second via. A second trace 121b spaced apart from each other by a predetermined distance W7' between the sides of the 142 may be included.

The plurality of traces 121a and 121b of the first circuit pattern 120 may have a specific line width W6 and a specific interval W7'. For example, the line width W6 of the traces 121a and 121b of the first circuit pattern 120 may be in a range of 6 μm to 20 μm. For example, the line width W6 of the traces 121a and 121b of the first circuit pattern 120 may be in a range of 7 μm to 15 μm. For example, the line width W6 of the traces 121a and 121b of the first circuit pattern 120 may be in a range of 8 μm to 12 μm. Also, the interval W7 ′ between the traces 121a and 121b of the first circuit pattern 120 may be in a range of 6 μm to 20 μm. For example, the interval W7 ′ between the traces 121a and 121b of the first circuit pattern 120 may be in a range of 7 μm to 15 μm. For example, the interval W7 ′ between the traces 121a and 121b of the first circuit pattern 120 may be in a range of 8 μm to 12 μm. Here, the spacing W7 ′ may mean a spacing between a plurality of traces constituting the first circuit pattern 120 . Also, the gap W7 ′ may mean a gap between the traces 121a and 121b constituting the first circuit pattern 120 and the via 140 used as a mounting pad in the embodiment.

Referring to FIG. 4B , in the embodiment, since the first surface of each of the first via 141 and the second via 142 is used instead of separately forming the mounting pad as described above, a separate method as in the comparative example is used. It is possible to reduce the pitch of the mounting pad compared to that in which the mounting pad is formed. Furthermore, in the embodiment, while the pitch of the mounting pad is reduced, a space between the first via 141 and the second via 142 used as the mounting pad may be sufficiently secured. Accordingly, in the embodiment, not one trace, but at least two traces may be disposed in the space between the first via 141 and the second via 142 . In this case, in the embodiment, even if the first trace 121a and the second trace 121b are disposed in the space between the first via 141 and the second via 142 , the pitch P1 between the plurality of vias ) may be 100 µm or less, further 90 µm or less, and further 80 µm or less.

5 is a diagram illustrating a circuit board according to a third modified example.

Referring to FIG. 5 , the circuit board 100c may have a multi-layered structure based on the number of insulating layers.

For example, the circuit board 100 in FIG. 2A has a one-layer structure based on the number of insulating layers.

On the other hand, as shown in FIG. 5 , the circuit board 100c according to the third modification may have a multi-layered structure. For example, the circuit board 100c may have a five-layer structure based on the number of insulating layers. However, this is only an example, and the circuit board 100c may have 2 to 4 layers based on the number of insulating layers, or may have 6 or more layers differently.

The circuit board 100c includes an insulating layer 110c.

The insulating layer 110c is formed by sequentially forming a first insulating layer 111c, a second insulating layer 112c, a third insulating layer 113c, a fourth insulating layer 114c, and a fifth insulating layer 115c from above. may include

The first insulating layer 111c may be a first outermost insulating layer disposed on the first outermost side of the circuit board 100c. Also, the fifth insulating layer 115c may be a second outermost insulating layer disposed on the second outermost side opposite to the first outermost side of the circuit board 100c.

Also, the second insulating layer 112c , the third insulating layer 113c , and the fourth insulating layer 114c may be inner insulating layers disposed inside the circuit board 100c .

The circuit board 100c includes circuit patterns respectively disposed on the surface of the insulating layer 110c.

For example, the circuit board 100c includes a first circuit pattern 120 disposed on a first surface of the first insulating layer 111c, a first surface of the first insulating layer 111c, and a second insulating layer 112c. ) and a second circuit pattern 130 disposed between the second surfaces.

In this case, the insulating layer 110 in the circuit board 100 shown in FIG. 2A is an insulating layer disposed closest to the chip mounting region in which the chip is mounted. For example, when the circuit board has a multilayer structure, the insulating layer 110 in FIG. 2A is the first outermost insulating layer. Accordingly, the insulating layer, the first circuit pattern, the second circuit pattern and the via shown in FIGS. 2A, 3 and 4A are the first insulating layer 111c corresponding to the first outermost insulating layer in FIG. 5 . , a first circuit pattern 120 disposed on a first surface of the first insulating layer 111c, a second circuit pattern 130 disposed on a second surface of the first insulating layer 111c, and the first It may correspond to the via 140 penetrating the insulating layer 111c.

However, although the second surface treatment layer 170 is disposed on the second surfaces of the first pad 131 and the second pad 132 of the second circuit pattern 130 in FIG. 2A , the multilayer structure shown in FIG. 5 . , the second surface treatment layer 170 may be disposed on the lower surface of the circuit pattern 182 disposed on the lower surface of the fifth insulating layer 115c, which is the second lowermost insulating layer. In addition, although the second protective layer 155 is disposed on the lower surface of the insulating layer 110 in FIG. 2A , in the multilayer structure as shown in FIG. 5 , the second protective layer 155 is a fifth lowermost insulating layer. It may be disposed on the lower surface of the insulating layer 115c.

On the other hand, the circuit board 100c in the multilayer structure includes circuit patterns 181 , 182 , 183 disposed inside the insulating layer 110c , and vias 191 , 192 passing through each insulating layer 110c , 193, 194) may be further included.

Here, in the multilayer structure, thicknesses of vias disposed in each insulating layer 110c may be different.

That is, the via 140 disposed on the first insulating layer 111c may function as a mounting pad as described above, and thus may have a thickness greater than the thickness of the first insulating layer 111c. .

In contrast, vias 191 , 192 , 193 , and 194 respectively disposed in the second insulating layer 112c , the third insulating layer 113c , the fourth insulating layer 114c , and the fifth insulating layer 115c are Each of the second insulating layer 112c, the third insulating layer 113c, the fourth insulating layer 114c, and the fifth insulating layer 115c may have the same thickness.

6A is a diagram illustrating a modified example of a circuit board according to an embodiment, and FIG. 6B is a SAM diagram showing traces in an actual product corresponding to FIG. 6A.

6A and 6B , the first circuit pattern 120 and the via 140 according to the embodiment are manufactured by the ETS method.

Accordingly, the circuit board is manufactured by a metal seed layer (not shown) disposed on the first surface of the first circuit pattern 120 and the first surface of the via 140 , and in the final manufacturing step The metal seed layer is removed by etching.

In this case, in the embodiment, when the metal seed layer is etched, at least a portion of the first circuit pattern 120 and the via 140 are also removed.

Accordingly, the circuit board 100d has an insulating layer 110d, a first circuit pattern 120d, a second circuit pattern 130d, a via 140d, a first passivation layer 150d, and a second passivation layer 155d. , a first surface treatment layer 160d and a second surface treatment layer 170d.

At this time, the insulating layer 110d, the second circuit pattern 130d, the first passivation layer 150d, the second passivation layer 155d, and the second surface treatment layer 170d are the circuit board 100 described with reference to FIG. 2A . ) and the detailed description thereof will be omitted accordingly.

The first circuit pattern 120d is disposed to be buried in the first surface or the upper surface of the insulating layer 110d. In this case, the first circuit pattern 120d includes traces disposed between the plurality of vias 140d as described above.

In this case, the first surface or upper surface of the trace of the first circuit pattern 120d may be positioned lower than the first surface or upper surface of the insulating layer 110d. For example, in the embodiment, when the metal seed layer is removed, at least a part of the first surface or the upper surface of the trace of the first circuit pattern 120d is also removed, so that the trace of the first circuit pattern 120d is removed. The first surface or upper surface of the insulating layer 110d is positioned lower than the first surface or upper surface of the insulating layer 110d.

A first surface or an upper surface of the trace of the first circuit pattern 120d may include a curved surface. For example, the first surface or the upper surface of the trace of the first circuit pattern 120d may have a curved surface due to a difference in the nickname between the edge region and the region other than the edge when the metal seed layer is nicknamed. . In this case, the first surface or the upper surface of the trace of the first circuit pattern 120d may be a curved surface convex in an upward direction. However, the embodiment is not limited thereto, and the first surface or the upper surface of the trace of the first circuit pattern 120d may be a curved surface concave in the downward direction.

The first surface of the via 140d may be removed together when the metal seed layer is removed, similarly to the trace of the first circuit pattern 120d.

Accordingly, the first surface or upper surface of the via 140d may be positioned lower than the first surface or upper surface of the insulating layer 110d.

The first surface or upper surface of the via 140d may include a curved surface. For example, the first surface or the top surface of the via 140d may include a curved surface convex in an upward direction. However, the embodiment is not limited thereto, and the first surface or the upper surface of the via 140d may include a curved surface concave in the downward direction.

The first surface treatment layer 160a is disposed on the first surface or the upper surface of the via 140d. Accordingly, the first surface treatment layer 160a may include a curved surface to correspond to the curved surface of the first surface or the upper surface of the via 140d.

In this case, the first surface treatment layer 160a is disposed on the first surface or the upper surface of the via 140d, and accordingly, the second surface or the lower surface of the first surface treatment layer 160a is the insulating layer 110d. It may be located lower than the first surface or the upper surface.

In addition, the first protective layer 150a is disposed on the first surface or the upper surface of the insulating layer 110d. In this case, the first protective layer 150a is disposed to cover the first circuit pattern 120d buried in the first surface or the upper surface of the insulating layer 110d. In this case, the first surface or upper surface of the first circuit pattern 120d is disposed lower than the first surface or upper surface of the insulating layer 110d. Accordingly, the first protective layer 150a is disposed to cover the first surface or the upper surface of the first circuit pattern 120d, and accordingly, at least a portion of the lower surface of the first protective layer 150a is It may be positioned lower than the upper surface of the insulating layer 110d.

That is, as shown in FIG. 6B , when the metal layer B disposed in the insulating layer A is etched and the seed layer disposed on the metal layer B is etched, in the embodiment, the metal layer B ) to proceed with etching at least a part of the upper surface. In addition, the metal layer B may be a via 140d in the embodiment, or a trace of the first circuit pattern 120d.

Hereinafter, a method of manufacturing a circuit board according to an embodiment will be described.

The following description is a manufacturing method for the circuit board shown in FIG. 2A, and based on this, the circuit board as shown in FIGS. 3, 4A, 5 and 6A may be manufactured.

7A to 7I are diagrams for explaining the manufacturing method of the circuit board shown in FIG. 2A in order of process.

Referring to FIG. 7A , in the embodiment, a basic material for manufacturing a circuit board may be prepared by the ETS method.

For example, in the embodiment, the carrier board CB in which the carrier insulating layer CB1 and the metal layer CB2 are disposed on at least one surface of the carrier insulating layer CB1 may be prepared. In this case, the metal layer CB2 may be disposed on only one of the first and second surfaces of the carrier insulating layer CB1 , or alternatively, it may be disposed on both surfaces of the carrier insulating layer CB1 . For example, the metal layer CB2 is disposed on only one surface of the carrier insulating layer CB1 , and accordingly, the ETS process for manufacturing the circuit board may be performed only on the one surface. Alternatively, the metal layer CB2 may be disposed on both surfaces of the carrier insulating layer CB1, and accordingly, the ETS process for manufacturing the circuit board may be simultaneously performed on both surfaces of the carrier board CB. In this case, two circuit boards can be manufactured at once.

The metal layer CB2 may be formed by electroless plating on the carrier insulating layer CB1 . Alternatively, the carrier insulating layer CB1 and the metal layer CB2 may be copper clad laminate (CCL).

Next, referring to FIG. 7B , in the embodiment, a first dry film DF1 is formed on the metal layer CB2 . In this case, the first dry film DF1 may be disposed to cover the entirety of the metal layer CB2 . Thereafter, in an embodiment, the first dry film DF1 may be exposed and developed to form an opening (not shown). In this case, the opening of the first dry film DF1 may expose an area in which the first circuit pattern 120 is to be formed. In this case, the opening of the general first dry film DF1 is also formed in a region overlapping the via connected to the mounting pad in the thickness direction. Unlike this, in the embodiment, since the mounting pad is not included in the first circuit pattern 120 and the via 140 is used as the mounting pad, the opening of the first dry film DF1 serves as the mounting pad of the chip. It may not overlap in the thickness direction of the used via 140 .

Thereafter, in an embodiment, the process of forming the first circuit pattern 120 filling the opening of the first dry film DF1 may be performed by electroplating the metal layer CB2 as a seed layer.

Next, referring to FIG. 7C , in the embodiment, a process of forming the insulating layer 110 on the metal layer CB2 may be performed. The insulating layer 110 may include a prepreg as described above.

Next, referring to FIG. 7D , in the embodiment, a laser mask RM may be formed on the insulating layer 110 . In this case, the laser mask RM includes an opening. For example, the laser mask RM may include an opening exposing a region where the via hole VH is to be formed. Thereafter, in an embodiment, a via hole VH passing through the insulating layer 110 may be formed by irradiating a laser beam into the opening of the laser mask RM.

In this case, in a general circuit board manufacturing process, a circuit pattern (electrolytic plating layer electrolytically plated using a seed layer) is used as a laser stopper. For example, in the ETS process according to the comparative example, the pad of the first circuit pattern is positioned on the metal layer CB2 in which the via hole VH is to be formed. In addition, the pad of the first circuit pattern may be used as a stopper in the laser process.

Alternatively, in the embodiment, when the first circuit pattern 120 is formed, a pad connected to the via 140 is not formed. Accordingly, in the embodiment, in the process of forming the via hole VH, the metal layer CB2 serving as the seed layer of the first circuit pattern 120 may be used as the laser stopper. Accordingly, in the embodiment, unlike the comparative example, the surface of the metal layer CB2 is exposed while the via hole VH is formed.

Next, as shown in FIG. 7E , in the embodiment, a second dry film DF2 is formed on the insulating layer 110 . In this case, the second dry film DF2 may be entirely formed on the insulating layer 110 . Thereafter, in an embodiment, the second dry film DF2 may be exposed and developed to form an opening. For example, the second dry film DF2 may include an opening exposing the formed via hole and an opening exposing a region in which the second circuit pattern 130 is to be formed. At this time, although not shown in the drawings in the embodiment, a chemical copper plating layer may be formed on the surface of the insulating layer 110 and the inner wall of the via hole VH before the formation of the second dry film DF2 . The chemical copper plating layer may be a seed layer for forming the second circuit pattern 130 by electrolytic plating.

Next, as shown in FIG. 7F , in the embodiment, a process of forming the second circuit pattern 130 filling the inside of the via hole VH and the opening of the second dry film DF2 may be performed. . For example, in the embodiment, the second circuit pattern 130 filling the inside of the via hole VH and the opening of the second dry film DF2 is formed by electroplating the chemical copper plating layer as a seed layer. can be formed

Next, as shown in FIG. 7G , in the embodiment, a process of removing the second dry film DF2 may be performed. At this time, although not shown in the drawings in the embodiment, a process of etching and removing the chemical copper plating layer used as the seed layer of the second circuit pattern 130 may be additionally performed.

Thereafter, in the embodiment, the circuit board progressed from both sides of the carrier board CB may be separated from each other. For example, in the embodiment, when the manufacturing process of the second circuit pattern 130 is completed, a process of separating and removing the carrier insulating layer CB1 may be performed.

Accordingly, in the embodiment, two circuit boards may be simultaneously manufactured on both sides of the carrier board CB as a center. On the other hand, the manufacturing process as described above is a description of a case in which the circuit board has a one-layer structure centered on the number of insulating layers. However, when the circuit board has a multilayer structure of two or more layers based on the number of insulating layers, the multilayer board may be manufactured by further performing the processes of FIGS. 7C to 7F .

Next, as shown in FIG. 7H , a process of removing the seed layer used to manufacture the first circuit pattern 120 may be performed. For example, as shown in FIG. 7F , the carrier insulating layer CB1 is removed to separate the circuit board including the metal layer CB2 , and an etching process is performed on the separated circuit board to perform an etching process on the metal layer CB2 . ) can be removed. In this case, only the metal layer CB2 may be selectively removed during the etching process of the metal layer CB2 . In this case, the first surface of the via 140 , the first surface of the trace of the first circuit pattern 120 , and the first surface of the insulating layer 110 may all be positioned on the same plane.

However, when the metal layer CB2 is substantially etched, it is difficult to selectively remove only the metal layer CB2 , and furthermore, when a part of the metal layer CB2 is not removed, the adjacent first circuit pattern 120 . There is a problem that a short occurs due to the interconnection between the traces. Accordingly, in the embodiment, over-etching is performed when the metal layer CB2 is etched, so that at least a portion of the first surface of the via 140 and the trace of the first circuit pattern 120 together with the metal layer CB2 . At least a portion of the first surface of the may be removed together. Accordingly, in the embodiment, the first surface of the trace of the first circuit pattern 120 and the first surface of the via 140 may be positioned lower than the first surface of the insulating layer 110 .

Thereafter, in an embodiment, a process of forming the first protective layer 150 on the first surface of the insulating layer 110 may be performed. The first protective layer 150 protects the first surface of the insulating layer 110 and protects the first surface of the trace of the first circuit pattern 120 buried in the first surface of the insulating layer 110 . can protect

In addition, in an embodiment, a process of forming the second protective layer 155 on the second surface of the insulating layer 110 may be performed. The second protective layer 155 may include an opening exposing at least a portion of the second surface of the second circuit pattern 130 while protecting the second surface of the insulating layer 110 .

Next, as shown in FIG. 7I , in the embodiment, a first surface treatment layer 160 is formed on the first surface of the via 140 and exposed through the opening of the second protective layer 155 . A process of forming the second surface treatment layer 170 on the second surface of the second circuit pattern 130 may be performed. As described above, the first surface treatment layer 160a and the second surface treatment layer 170 may be processed by the OSP process, or alternatively, by the ENEPIG process.

-Second embodiment-

8 is a diagram illustrating a circuit board according to a second embodiment.

Referring to FIG. 8 , the circuit board 200 is similar to the circuit board 100 of FIG. 2A , and is different in the configuration of the first circuit pattern and vias.

Referring to FIG. 2A , the entire portion of the circuit board 100 used as a mounting pad is formed of the first surface of the via 140 . Alternatively, as shown in FIG. 8 , a first portion of a portion used as a mounting pad in the circuit board 200 is configured as a pad 222 of the first circuit pattern 220 , and the remaining second portion is a via 240 . ) may be configured as the first surface of However, the width W2 of the first surface of the via 240 is substantially the same as the width of the first surface of the via 140 in FIG. 2A .

That is, the circuit board 200 includes an insulating layer 210 , a first circuit pattern 220 , a second circuit pattern 230 , a via 240 , a first passivation layer 250 , and a second passivation layer 260 . may include

Here, the insulating layer 210, the second circuit pattern 230, the first passivation layer 250, and the second passivation layer 260 in the circuit board 100 of the first embodiment, the insulating layer 110, The second circuit pattern 130 , the first passivation layer 150 , and the second passivation layer 155 are substantially the same, and thus a detailed description thereof will be omitted.

In an embodiment, the circuit board 200 includes a first circuit pattern 220 having an ETS structure buried in a first surface or an upper surface of the insulating layer 210 . In this case, the first circuit pattern 220 in the first embodiment does not include a pad for mounting a chip, but in the second embodiment, the first circuit pattern 220 may include a pad for mounting a chip. have.

For example, the first circuit pattern 220 includes a trace 221 and a pad 222 .

The pad 222 of the first circuit pattern 220 includes a first pad 222-1 connected to the first via 241 and a second pad 222-2 connected to the second via 242. includes

The first pad 222-1 of the first circuit pattern 220 may be disposed to overlap the first via 241 in the thickness direction. Accordingly, the first pad 222-1 of the first circuit pattern 220 may be disposed in direct contact with the first via 241 .

However, the first pad 222-1 of the first circuit pattern 220 may have a width smaller than the width W1 of the first surface of the first via 241 . Accordingly, the first pad 222-1 of the first circuit pattern 220 may have a structure buried in the first surface of the first via 241 . For example, the first pad 222-1 of the first circuit pattern 220 may be surrounded by the first via 241 .

Accordingly, the first surface or top surface of the first pad 222-1 may be positioned on the same plane as the first surface or top surface of the first via 241 .

That is, it is possible to directly form the via 140 without forming the first pad 222-1 as in the first embodiment, but as in the second embodiment, the first pad 222- In the state in which 1) is formed, it is also possible to form the via 240 having the same size as the via 140 of the first embodiment. The first pad 222-1 may be formed to increase product reliability without affecting the pitch of the mounting pad by the first via 241 according to an embodiment.

For example, as in the first embodiment, when the via hole is formed in a state in which the first pad 222-1 is not formed, it may be difficult to accurately select a position where the via hole is to be formed. Accordingly, the position of the via hole may be shifted, and further, the position of the via may be shifted. On the other hand, in the second embodiment, in a state in which the first pad 222-1 is formed as described above, the via hole and the first via 241 are formed based on the first pad 222-1. The position of the first via 241 may be accurately determined, and thus reliability of the first via 241 may be improved.

Furthermore, when the inside of the via hole is filled with plating in the absence of the first pad 222-1, a dimple phenomenon in which the surface is concave may occur depending on the size of the via hole. Accordingly, in the embodiment, in a state in which the first pad 222-1 is disposed inside the via hole, the plating process of the first via 241 is performed, so that the first pad 222-1 has The degree of the dimple phenomenon may be reduced corresponding to the area, and thus product reliability may be improved.

Meanwhile, the second pad 222 - 2 of the first circuit pattern 220 may have a structure corresponding to the first pad 222 - 1 . In addition, the second via 242 may be disposed to correspond to the first via 241 and surround the periphery of the second pad 222 - 2 . For example, the second pad 222 - 2 of the first circuit pattern 220 may have a structure buried in the first surface or the top surface of the second via 242 .

Also, as described in the first embodiment, the second circuit pattern 230 includes a first pad 231 connected to the first via 241 and a second pad 232 connected to the second via 242 . includes

Meanwhile, in an embodiment, the first surface treatment layer 260 may be formed on the first surface or upper surface of each of the first via 241 and the second via 242 as well as of the first circuit pattern 220 . It may also be disposed on the first surface or upper surface of the first pad 222-1 and the second pad 222-2.

As described above, in the circuit board according to the second embodiment, the pad of the first circuit pattern is embedded in the first surface of the via while using the first surface of the via as a chip mounting pad for chip mounting. Accordingly, in the embodiment, the easiness and reliability of the manufacturing process for forming the via may be improved. For example, according to the second exemplary embodiment, the position where the via is to be arranged can be accurately identified using the pad of the first circuit pattern, and thus the accuracy of the formation position of the via can be improved. Furthermore, in an embodiment, as the pad of the first circuit pattern forms a part of the via, a dimple problem that may occur when the via is formed can be solved, and thus the reliability of the via can be improved.

9A to 9E are diagrams for explaining the manufacturing method of the circuit board shown in FIG. 8 in order of process.

Referring to FIG. 9A , in the embodiment, a basic material for manufacturing a circuit board may be prepared by the ETS method.

For example, in the embodiment, the carrier board CB in which the carrier insulating layer CB1 and the metal layer CB2 are disposed on at least one surface of the carrier insulating layer CB1 may be prepared. In this case, the metal layer CB2 may be disposed on only one of the first and second surfaces of the carrier insulating layer CB1 , or alternatively, it may be disposed on both surfaces of the carrier insulating layer CB1 . For example, the metal layer CB2 is disposed on only one surface of the carrier insulating layer CB1 , and accordingly, the ETS process for manufacturing the circuit board may be performed only on the one surface. Alternatively, the metal layer CB2 may be disposed on both surfaces of the carrier insulating layer CB1, and accordingly, the ETS process for manufacturing the circuit board may be simultaneously performed on both surfaces of the carrier board CB. In this case, two circuit boards can be manufactured at once.

Then, a first dry film DF1 is formed on the metal layer CB2 . In this case, the first dry film DF1 may be disposed to cover the entirety of the metal layer CB2 . Thereafter, in an embodiment, the first dry film DF1 may be exposed and developed to form an opening (not shown). In this case, the opening of the first dry film DF1 may expose a region where the first circuit pattern 220 is to be formed. In this case, the opening of the first dry film DF1 according to the second embodiment is also formed in a region overlapping the via in the thickness direction. However, in general, the opening of the first dry film formed in the region overlapping the via in the thickness direction has a width greater than the size of the via. Alternatively, in the second embodiment, the opening of the first dry film formed in the region overlapping the via in the thickness direction may have a width smaller than the size of the via.

Thereafter, in an embodiment, a process of forming the first circuit pattern 220 filling the opening of the first dry film DF1 may be performed by electroplating the metal layer CB2 as a seed layer. In this case, the first circuit pattern 220 may include a trace 221 and a pad 222 .

Next, referring to FIG. 9B , in the embodiment, a process of forming the insulating layer 210 on the metal layer CB2 may be performed. The insulating layer 210 may include a prepreg as described above.

Next, referring to FIG. 9C , in the embodiment, a laser mask RM may be formed on the insulating layer 210 . In this case, the laser mask RM includes an opening. For example, the laser mask RM may include an opening exposing a region where the via hole VH is to be formed. Thereafter, in an embodiment, a via hole VH passing through the insulating layer 210 may be formed by irradiating a laser beam into the opening of the laser mask RM.

In this case, in a general circuit board manufacturing process, a circuit pattern (electrolytic plating layer electrolytically plated using a seed layer) is used as a laser stopper. For example, in the ETS process according to the comparative example, the pad of the first circuit pattern is positioned on the metal layer CB2 in which the via hole VH is to be formed. In addition, the pad of the first circuit pattern may be used as a stopper in the laser process.

Alternatively, in the embodiment, when the first circuit pattern 220 is formed, the pad 222 connected to the via 240 is formed, but the width of the pad 222 is that of the via 240 . formed smaller than the width. Accordingly, in the embodiment, the metal layer CB2 serving as the seed layer of the first circuit pattern 120 is used as a laser stopper in some areas, and the pads 222 of the first circuit pattern 220 are used in the remaining partial areas. use it Accordingly, in an embodiment, as the via hole VH is formed, not only the pad 222 of the first circuit pattern 220 but also a portion of the metal layer CB2 may be exposed.

Next, as shown in FIG. 9D , in the embodiment, a second dry film DF2 is formed on the insulating layer 210 . In this case, the second dry film DF2 may be entirely formed on the insulating layer 210 . Thereafter, in an embodiment, the second dry film DF2 may be exposed and developed to form an opening. For example, the second dry film DF2 may include an opening exposing the formed via hole and an opening exposing an area in which the second circuit pattern 230 is to be formed. At this time, although not shown in the drawings in the embodiment, a chemical copper plating layer may be formed on the surface of the insulating layer 210 and the inner wall of the via hole VH before the formation of the second dry film DF2 . The chemical copper plating layer may be a seed layer for forming the second circuit pattern 230 by electrolytic plating.

Thereafter, in the embodiment, a process of forming the via 240 and the second circuit pattern 230 filling the inside of the via hole VH and the opening of the second dry film DF2 may be performed. For example, in the embodiment, the via 240 and the second circuit filling the inside of the via hole VH and the opening of the second dry film DF2 by electroplating the chemical copper plating layer as a seed layer. A pattern 230 may be formed. In this case, the via hole VH in the embodiment has a greater width than the pad 222 of the first circuit pattern 220 , and thus the via 242 may be formed around the pad 222 . can For example, the via 240 may be formed to surround at least three surfaces of the pad 222 , and at least a portion of the via 240 may contact the metal layer CB2 .

Next, as shown in FIG. 9E , a circuit board may be manufactured by performing processes corresponding to FIGS. 7G to 7I .

As described above, in the embodiment, the pad of the first circuit pattern is buried in the first surface of the via while maintaining the size of the via, so that the reliability of the via can be improved.

10 is a view showing a circuit board of a modified example of the second embodiment.

Referring to FIG. 10 , the circuit board includes an insulating layer 310 , a first circuit pattern 320 , a second circuit pattern 330 , a via 340 , a first passivation layer 350 , and a second passivation layer 355 . ), a first surface treatment layer 360 , and a second surface treatment layer 370 .

In this case, in the second embodiment, the pad 222 of the first circuit pattern 220 has a width smaller than the width of the first surface of the via 240 , and accordingly, the via 240 is the pad 222 . ) was placed around the

Alternatively, in a modified example thereof, the pad 322 of the first circuit pattern 320 may have the same width as the width of the first surface of the via 340 . Accordingly, in the modified example, the pad 322 of the first circuit pattern 320 functions as a mounting pad, but the pad 322 has substantially the same width as the width of the first surface of the via 340 . Accordingly, the pitch P1 of the pad described above is not affected.

That is, as a modified example of the second embodiment, the via 340 is formed to have the same thickness as the thickness of the insulating layer 310 as in the comparative example, and the pad ( 322) is formed. In this case, the pad 322 has substantially the same width, which is not greater than the width of the first surface of the via 340 as in the comparative example. Accordingly, in the embodiment, the pitch of the mounting pad may be 100 µm or less, further 90 µm or less, and further 80 µm or less.

- Package board -

11 is a view showing a package substrate according to an embodiment.

Referring to FIG. 11 , the package substrate may include the circuit board shown in any one of FIGS. 2A, 3, 4A, 5, 6A, 8, and 9 . However, as the package substrate, a chip is mounted using a multilayer substrate, and accordingly, the package substrate including the circuit substrate shown in FIG. 5 will be described. However, the embodiment is not limited thereto, and the circuit board may include a circuit board included in other drawings.

The package substrate includes a circuit board.

In addition, the package substrate includes the first adhesive portion 410 disposed on the mounting pad of the circuit board 100c. Preferably, in the embodiment, the circuit board 100c does not include a pad in the first circuit pattern 120 , and thus the first adhesive part 410 is disposed on the first surface or the upper surface of the via 140 . can be Preferably, the first adhesive part 410 may be disposed on the first surface treatment layer 160 disposed on the first surface or upper surface of the via 140 .

The first adhesive part 410 may have a hexahedral shape, for example. For example, a cross-section of the first adhesive part 410 may have a rectangular shape. For example, a cross-section of the first adhesive part 410 may have a rectangular or square shape. As another example, the first adhesive part 410 may have a spherical shape. For example, a cross-section of the first adhesive part 410 may have a circular shape or a semicircular shape. For example, the cross-section of the first adhesive part 410 may include a partially or entirely rounded shape. For example, the cross-sectional shape of the first adhesive part 410 may include a flat surface on one side and a curved surface on the other side opposite to the one side. Meanwhile, the first adhesive part 410 may be a micro ball, but is not limited thereto.

A chip 420 may be mounted on the first adhesive part 410 . A chip 420 to which the terminal 430 is connected may be mounted on the first adhesive part 410 .

For example, the chip 420 may include a drive IC chip. For example, the chip 420 may refer to various chips including sockets or devices other than a drive IC chip. For example, the chip 420 may include at least one of a diode chip, a power supply IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, and a chip capacitor. For example, the chip 420 may be a power management integrated circuit (PMIC). For example, the chip 420 may be a memory chip such as a volatile memory (eg, DRAM), a non-volatile memory (eg, ROM), a flash memory, or the like. For example, the chip 420 is an application processor (AP) chip such as a central processor (eg, CPU), a graphic processor (eg, GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, or an analog It may be a logic chip such as a digital converter or an application-specific IC (ASIC). Here, although it is illustrated that only one chip is mounted on the package substrate in the drawings, the present invention is not limited thereto. For example, a plurality of chips may be mounted on the circuit board spaced apart from each other. The plurality of chips may include a first AP chip corresponding to a central processor (CPU) and a second AP chip corresponding to a graphics processor (GPU).

A molding layer 430 may be formed on the circuit board. The molding layer 430 may be disposed to cover the mounted chip 420 . For example, the molding layer 230 may be an epoxy mold compound (EMC) formed to protect the mounted chip 420 , but is not limited thereto.

Meanwhile, when the circuit board has a multilayer structure, the line widths or intervals of circuit patterns disposed on each insulating layer may be different from each other. For example, a circuit pattern disposed closest to the chip may have the smallest line width and spacing, and a circuit pattern disposed furthest from the chip may have the largest line width and spacing.

Accordingly, the vias included in the circuit board 100c in the embodiment may have different widths.

For example, the via disposed in the insulating layer disposed adjacent to the chip may have a width corresponding to the via 140 described above. In addition, the width of a via disposed in another insulating layer may gradually increase as it moves away from the via 140 . For example, a via disposed on the lowermost side of the circuit board may have the largest width.

Meanwhile, in an embodiment, the second adhesive part 450 may be disposed on the lowermost side of the circuit board and on the circuit pattern exposed through the opening of the protective layer. The second adhesive part 450 may be a solder ball. The second adhesive part 450 may be connected to the main board of the external substrate.

Features, structures, effects, etc. described in the above embodiments are included in at least one embodiment, and are not necessarily limited to only one embodiment. Furthermore, features, structures, effects, etc. illustrated in each embodiment can be combined or modified for other embodiments by those of ordinary skill in the art to which the embodiments belong. Accordingly, the contents related to such combinations and modifications should be interpreted as being included in the scope of the embodiments.

In the above, the embodiment has been mainly described, but this is only an example and does not limit the embodiment, and those of ordinary skill in the art to which the embodiment pertains are provided with several examples not illustrated above within a range that does not depart from the essential characteristics of the embodiment. It can be seen that variations and applications of branches are possible. For example, each component specifically shown in the embodiment can be implemented by modification. And differences related to such modifications and applications should be interpreted as being included in the scope of the embodiments set forth in the appended claims.

Claims (18)

insulating layer;
a first circuit pattern disposed on an upper surface of the insulating layer;
a second circuit pattern disposed on a lower surface of the insulating layer opposite to the upper surface; and
a via passing through the insulating layer and electrically connected to the first circuit pattern and the second circuit pattern;
The first circuit pattern is embedded in the upper surface of the insulating layer,
The upper surface of the via is located higher than the lower surface of the first circuit pattern,
The via includes a first via and a second via spaced apart from the first via in a width direction;
A pitch corresponding to a distance from the center of the first via to the center of the second via is 100 μm or less,
circuit board. According to claim 1,
a top surface of the first via and a top surface of the second via,
located on the same plane as the upper surface of the first circuit pattern,
circuit board. According to claim 1,
Each thickness of the first via and the second via is,
greater than the thickness of the insulating layer corresponding to the distance from the lower surface of the first circuit pattern to the upper surface of the second circuit pattern;
circuit board. According to claim 1,
the first circuit pattern includes a trace,
At least one trace of the first circuit pattern is disposed between a side surface of the first via and a side surface of the second via;
circuit board. 5. The method of claim 4,
The second circuit pattern is
a first pad connected to the first via; and
a second pad connected to the second via;
The trace of the first circuit pattern,
overlapping with at least one of the first pad and the second pad in the thickness direction,
circuit board. 6. The method of claim 5,
A distance between the first pad and the second pad is in the range of 2 μm to 30 μm,
circuit board. 6. The method of claim 5,
the second circuit pattern includes a trace,
the traces of the second circuit pattern are disposed on a lower surface of the insulating layer except for a region between the first pad and the second pad of the second circuit pattern;
circuit board. According to claim 1,
each of the first via and the second via,
The width of the upper surface is smaller than the width of the lower surface,
circuit board. 9. The method according to any one of claims 1 to 8,
Each of the first via, the second via, and the upper surface of the first circuit pattern includes a curved surface,
circuit board. 9. The method according to any one of claims 1 to 8,
an upper surface of each of the first via, the second via, and the first circuit pattern is positioned lower than an upper surface of the insulating layer;
circuit board. 9. The method according to any one of claims 1 to 8,
a first surface treatment layer disposed on upper surfaces of the first via and the second via;
circuit board. 9. The method according to any one of claims 1 to 8,
A pitch corresponding to a distance from the center of the first via to the center of the second via is 90 μm or less,
circuit board. 9. The method according to any one of claims 1 to 8,
The insulating layer is composed of a plurality of layers,
The first via and the second via are disposed in a first outermost insulating layer disposed on an outermost side of the plurality of insulating layers,
The first circuit pattern is buried in the upper surface of the first outermost insulating layer,
The second circuit pattern is disposed on a lower surface of the first outermost insulating layer,
circuit board. 9. The method according to any one of claims 1 to 8,
The first circuit pattern is
a first pad overlapping the first via in a thickness direction and a second pad overlapping the second via in a thickness direction;
a width of the first pad is smaller than a width of an upper surface of the first via;
a width of the second pad is smaller than a width of a top surface of the second via;
circuit board. 15. The method of claim 14,
The first via is
disposed to surround a side surface of the first pad of the first circuit pattern;
The second via is
disposed to surround a side surface of the first pad of the first circuit pattern,
circuit board. insulating layer;
a first circuit pattern buried in an upper surface of the insulating layer;
a second circuit pattern disposed on a lower surface of the insulating layer opposite to the upper surface;
a via passing through the insulating layer and electrically connected to the first circuit pattern and the second circuit pattern;
a first surface treatment layer disposed on an upper surface of the via;
a first adhesive part disposed on an upper surface of the first surface treatment layer;
a chip disposed on the first adhesive part;
It is disposed on the upper surface of the insulating layer, comprising a molding layer for molding the chip,
The upper surface of the via is located higher than the lower surface of the first circuit pattern,
The via includes a first via and a second via spaced apart from the first via in a width direction;
A pitch corresponding to a distance from the center of the first via to the center of the second via is 100 μm or less,
package board. 17. The method of claim 16,
The insulating layer is composed of a plurality of layers,
The first via and the second via are disposed in a first outermost insulating layer disposed on an outermost side of the plurality of insulating layers,
package board. 17. The method of claim 16,
The chip includes a first chip and a second chip disposed to be spaced apart from each other in the width direction,
The first chip corresponds to a central processor (CPU),
The second chip corresponds to a graphics processor (GPU),
package board.

Images