CN116314045A - 半导体装置、半导体模块、电子元器件以及SiC半导体装置 - Google Patents

半导体装置、半导体模块、电子元器件以及SiC半导体装置 Download PDF

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CN116314045A
CN116314045A CN202310512362.8A CN202310512362A CN116314045A CN 116314045 A CN116314045 A CN 116314045A CN 202310512362 A CN202310512362 A CN 202310512362A CN 116314045 A CN116314045 A CN 116314045A
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chip
main surface
substrate
semiconductor
insulating layer
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明田正俊
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Rohm Co Ltd
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Rohm Co Ltd
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Abstract

本发明提供一种半导体装置、半导体模块、电子元器件以及SiC半导体装置。电子元器件包含:基板,其具有一侧的第一主面和另一侧的第二主面;芯片,其具有一侧的第一芯片主面和另一侧的第二芯片主面、以及在所述第一芯片主面和/或所述第二芯片主面形成的多个电极,且配置于所述基板的所述第一主面;封固绝缘层,其以使所述基板的所述第二主面露出的方式在所述基板的所述第一主面上封固所述芯片,且具有与所述基板的所述第一主面对置的封固主面;以及多个外部端子,其以从所述封固绝缘层的所述封固主面露出的方式贯通所述封固绝缘层而形成,并与所述芯片的所述多个电极分别电连接。

Description

半导体装置、半导体模块、电子元器件以及SiC半导体装置
本发明是申请号为201880026608.8(国际申请号为PCT/JP2018/016373)、发明名称为“电子元器件和半导体装置”、申请日为2018年4月20日的发明申请的分案申请。
技术领域
本发明涉及电子元器件和半导体装置。
背景技术
专利文献1公开了一种作为电子元器件一例的功率模块半导体装置。该功率模块半导体装置包含陶瓷基板。在陶瓷基板上配置有半导体器件和端子电极。
端子电极横贯陶瓷基板的侧面并从陶瓷基板的内侧的区域向外侧的区域引出。端子电极经由键合引线与半导体器件电连接。
在半导体器件上立设有柱状电极。陶瓷基板、半导体器件、柱状电极和端子电极的一部分被树脂层封固。树脂层形成于陶瓷基板的外表面的整个区域。
现有技术文献
专利文献
专利文献1:日本特开2013-172044号公报
发明内容
发明所要解决的课题
在现有的功率模块半导体装置中,由于陶瓷基板的外表面的整面被树脂层覆盖,因此半导体器件产生的热容易滞留于树脂层。因此,通过将端子电极引出到树脂层外来使树脂层内的热向树脂层外散放。端子电极需要经由键合引线等连接部件与半导体器件连接。这种设计会妨碍电子元器件的小型化。
为此,本发明的一实施方式提供一种能够兼顾小型化和散热性的提高的电子元器件和半导体装置。
用于解决课题的方案
本发明的一实施方式提供一种电子元器件,其包含:基板,其具有一侧的第一主面和另一侧的第二主面;芯片,其具有一侧的第一芯片主面和另一侧的第二芯片主面、以及在所述第一芯片主面和/或所述第二芯片主面形成的多个电极,且配置于所述基板的所述第一主面;封固绝缘层,其以使所述基板的所述第二主面露出的方式在所述基板的所述第一主面上封固所述芯片,且具有与所述基板的所述第一主面对置的封固主面;以及多个外部端子,其以从所述封固绝缘层的所述封固主面露出的方式贯通所述封固绝缘层而形成,并与所述芯片的所述多个电极分别电连接。
根据该电子元器件,基板的第二主面从封固绝缘层露出。因此,即使未从基板的侧面引出外部端子,也能够使芯片产生的热从基板的第二主面向外部散放。
而且,由于不必从基板的侧面引出外部端子,因此不必使用键合引线等连接部件。由此,能够削减零件数量而实现缩减化。因此,可提供一种能够兼顾小型化和散热性的提高的的电子元器件。
本发明的一实施方式提供一种半导体装置,其包含:半导体基板,其具有一侧的第一主面和另一侧的第二主面;主面绝缘层,其形成在所述半导体基板的所述第一主面;半导体芯片,其具有多个电极且配置于所述主面绝缘层;封固绝缘层,其以使所述半导体基板的所述第二主面露出的方式在所述半导体基板的所述第一主面封固所述半导体芯片,且具有与所述半导体基板的所述第一主面对置的封固主面;以及多个外部端子,其以从所述封固绝缘层的所述封固主面露出的方式贯通所述封固绝缘层而形成,并与所述半导体芯片的所述多个电极分别电连接。
根据该半导体装置,半导体基板的第二主面从封固绝缘层露出。因此,即使未从半导体基板的侧面引出外部端子,也能够使半导体芯片产生的热从半导体基板的第二主面向外部散放。
而且,由于不必从半导体基板的侧面引出外部端子,因此不必使用键合引线等连接部件。由此,能够削减零件数量而实现缩减化。因此,可提供一种能够兼顾小型化和散热性的提高的的半导体装置。
特别是,根据该半导体装置,在半导体基板的第一主面形成有主面绝缘层。由此,能够利用半导体基板有效地散热并提高半导体芯片对施加电压的绝缘耐量。
本发明的上述的或者此外其它的目的、特征和效果可通过参照附图对下述实施方式的说明而更加清楚明了。
附图说明
图1是本发明的第一实施方式的电子元器件的立体图。
图2是用于对图1的电子元器件的内部结构进行说明的俯视图。
图3是沿着图2的III-III线的剖视图。
图4是沿着图2的IV-IV线的剖视图。
图5A是用于对图1的电子元器件的制造方法的一例进行说明的剖视图。
图5B是表示图5A之后的工序的剖视图。
图5C是表示图5B之后的工序的剖视图。
图5D是表示图5C之后的工序的剖视图。
图5E是表示图5D之后的工序的剖视图。
图5F是表示图5E之后的工序的剖视图。
图5G是表示图5F之后的工序的剖视图。
图5H是表示图5G之后的工序的剖视图。
图5I是表示图5H之后的工序的剖视图。
图5J是表示图5I之后的工序的剖视图。
图5K是表示图5J之后的工序的剖视图。
图6是与图3对应的部分的剖视图,是用于对本发明的第二实施方式的电子元器件的结构进行说明的图。
图7是与图4对应的部分的剖视图,是用于对图6的电子元器件的结构进行说明的图。
图8是与图3对应的部分的剖视图,是用于对本发明的第三实施方式的电子元器件的结构进行说明的图。
图9是与图4对应的部分的剖视图,是用于对图8的电子元器件的结构进行说明的图。
图10A是用于对图8的电子元器件的制造方法的一例进行说明的剖视图。
图10B是表示图10A之后的工序的剖视图。
图10C是表示图10B之后的工序的剖视图。
图10D是表示图10C之后的工序的剖视图。
图10E是表示图10D之后的工序的剖视图。
图11是与图3对应的部分的剖视图,是用于对本发明的第四实施方式的电子元器件的结构进行说明的图。
图12A是用于对图11的电子元器件的制造方法的一例进行说明的剖视图。
图12B是表示图12A之后的工序的剖视图。
图12C是表示图12B之后的工序的剖视图。
图13是与图3对应的部分的剖视图,是用于对本发明的第五实施方式的电子元器件的结构进行说明的图。
图14是用于对本发明的第六实施方式的电子元器件的结构进行说明的图。
图15是用于对本发明的第七实施方式的电子元器件的内部结构进行说明的俯视图。
图16是沿着图15的XVI-XVI线的剖视图。
图17是用于对图15所示电子元器件的电气结构进行说明的电路图。
图18是与图3对应的部分的剖视图,是用于对本发明的第八实施方式的电子元器件的结构进行说明的图。
具体实施方式
图1是本发明的第一实施方式的电子元器件1的立体图。
电子元器件1是包含作为半导体开关元件的一例的MISFET(Metal InsulatorSemiconductor Field Effect Transistor:金属-绝缘体-半导体场效应晶体管)的半导体装置。电子元器件1也可以包含进行大电流的开关控制的MISFET。在该方式中,MISFET是在芯片的一面侧具有栅极电极、源极电极和源极取样电极并在芯片的另一面侧具有漏极电极的所谓纵型结构。
参照图1,电子元器件1包含呈长方体形状的元器件主体2。元器件主体2包含:一侧的安装面3、另一侧的非安装面4、以及将安装面3和非安装面4连接的侧面5。安装面3是当电子元器件1安装于安装基板等连接对象物时与连接对象物对置的对置面。
安装面3和非安装面4形成为在从它们的法线方向观察的俯视角度下(以下简称为“俯视”)呈四边形状(在该方式中为长方形状)。元器件主体2的侧面5也可以是磨削面。侧面5也可以具有磨削加工痕。
元器件主体2是包含基板6、主面绝缘层7和封固绝缘层8的层叠结构。基板6形成为长方体形状。基板6包含:一侧的第一基板主面9、另一侧的第二基板主面10、以及将第一基板主面9和第二基板主面10连接的基板侧面11。基板6使MISFET产生的热高效地向外部散放。
第一基板主面9和第二基板主面10形成为俯视呈四边形状(在该方式中为长方形状)。基板6的第二基板主面10形成了元器件主体2的非安装面4。基板6的基板侧面11形成了元器件主体2的侧面5的一部分。
基板6优选为由具有100W/mK以上的导热率的材料形成。基板6可以包含由用于制造半导体元件、半导体装置等的材料形成的基板。即,基板6可以包含半导体基板。
半导体基板在导热率、获得性、加工性、成本等方面优于其它材料。在基板6采用半导体基板的情况下,其厚度考虑到对MISFET的应力和散热性而优选为50μm以上1000μm以下。
基板6可以是添加了杂质的半导体基板,也可以是不添加杂质的半导体基板。半导体基板可以是单晶基板,也可以是多晶基板。
半导体基板可以包含硅基板、碳化硅基板、蓝宝石基板或者化合物半导体基板。化合物半导体基板可以包含氮化物半导体基板和氧化物半导体基板。在该方式中,对于基板6由作为半导体基板的一例的硅基板构成的例子进行说明。
主面绝缘层7覆盖了基板6的第一基板主面9的整个区域。主面绝缘层7是为了使MISFET和基板6之间绝缘而设置的。在基板6安装有散热板等的情况下,主面绝缘层7也使MISFET和散热板等之间绝缘。主面绝缘层7形成了元器件主体2的侧面5的一部分。主面绝缘层7优选为具有至少1MV/cm以上的绝缘破坏电场强度。
主面绝缘层7可以包含氧化硅、氮化硅、氮氧化硅、氧化铝、氮化铝和氮氧化铝中的至少一种。
主面绝缘层7优选为采用CVD(Chemical Vapor Deposition:化学气相沉积)法、PVD(Physical Vapor Deposition:物理气相沉积)法等半导体制造工艺形成。采用这些方法,能够提高主面绝缘层7的膜质。
由此,能够形成具有比较小的厚度并具有足够高的绝缘破坏电场强度的主面绝缘层7。另外,通过减小主面绝缘层7的厚度而能够抑制导热率的降低。另外,通过在第二基板主面10侧连接散热器等,从而能够获得进一步的散热效果。
主面绝缘层7的厚度可以为0.1μm以上100μm以下。主面绝缘层7的厚度考虑到导热率和制造效率而优选为0.1μm以上10μm以下。主面绝缘层7优选为由具有比较高的导热率的绝缘材料形成。
例如,氮化硅的导热率高于氧化硅的导热率。因此,优选采用氮化硅作为主面绝缘层7的绝缘材料。除了氮化硅以外,具有比氧化硅的导热率高的导热率的绝缘材料也适合作为主面绝缘层7的绝缘材料。
封固绝缘层8形成为长方体形状。封固绝缘层8例如保护MISFET不受湿气等侵害。封固绝缘层8包含:一侧的第一封固主面12、另一侧的第二封固主面13、以及将第一封固主面12和第二封固主面13连接的封固侧面14。第一封固主面12和第二封固主面13形成为俯视呈四边形状(在该方式中为长方形状)。
封固绝缘层8的第一封固主面12形成了元器件主体2的安装面3。封固绝缘层8的第二封固主面13与主面绝缘层7连接。封固绝缘层8的封固侧面14形成了元器件主体2的侧面5的一部分。封固绝缘层8的封固侧面14和基板6的基板侧面11形成为大致表面一致。
封固绝缘层8可以包含氧化硅、氮化硅、聚酰亚胺树脂和环氧树脂中的至少一种。封固绝缘层8可以包含正型或者负型的光致抗蚀剂。在该方式中,封固绝缘层8由包含环氧树脂的封固树脂层构成。
封固绝缘层8的厚度大于主面绝缘层7的厚度。封固绝缘层8的厚度可以为10μm以上8000μm以下(在本实施方式中为300μm左右)。
电子元器件1包含:栅极外部端子15、源极外部端子16、源极取样外部端子17和漏极外部端子18。栅极外部端子15、源极外部端子16和源极取样外部端子17分别形成为芯片侧外部端子。漏极外部端子18形成为配线层侧外部端子。
栅极外部端子15、源极外部端子16、源极取样外部端子17和漏极外部端子18与后述的MISFET24的栅极端子电极28、源极端子电极29、源极取样端子电极30和漏极端子电极31分别电连接(一并参照图5等)。
栅极外部端子15、源极外部端子16和源极取样外部端子17俯视而言是在元器件主体2的一端部侧的区域形成。漏极外部端子18俯视而言是在元器件主体2的另一端部侧的区域形成。
栅极外部端子15、源极外部端子16、源极取样外部端子17和漏极外部端子18均贯通封固绝缘层8,并且从封固绝缘层8的第一封固主面12露出。即,栅极外部端子15、源极外部端子16、源极取样外部端子17和漏极外部端子18均从元器件主体2的安装面3露出。
栅极外部端子15、源极外部端子16、源极取样外部端子17和漏极外部端子18均形成在被基板6的周缘包围的区域内。即,栅极外部端子15、源极外部端子16、源极取样外部端子17和漏极外部端子18未横贯基板6的基板侧面11,而是在基板6的第一基板主面9上的区域配置。
栅极外部端子15、源极外部端子16、源极取样外部端子17和漏极外部端子18分别形成为俯视呈四边形状。栅极外部端子15、源极外部端子16、源极取样外部端子17和漏极外部端子18也可以分别形成为俯视呈四边形状以外的任意的形状。栅极外部端子15、源极外部端子16、源极取样外部端子17和漏极外部端子18也可以分别形成为俯视呈圆形状。
这样,电子元器件1构成为从元器件主体2的安装面3露出多个外部端子,且各外部端子并未从元器件主体2的非安装面4和侧面5露出。
图2是用于对图1的电子元器件1的内部结构进行说明的俯视图。图3是沿着图2的III-III线的剖视图。图4是沿着图2的IV-IV线的剖视图。
参照图2~图4,电子元器件1包含配线层20和MISFET芯片21。配线层20在主面绝缘层7上形成。配线层20形成为俯视呈四边形状。具体而言,配线层20形成为沿着基板6的长度方向延伸的长方形状。配线层20可以是以铜为主成分的铜配线层。
配线层20可以包含从主面绝缘层7侧起依次层叠的铜种层和铜镀敷层。配线层20可以包括含钛的势垒层。该情况下,铜种层可以形成在势垒层上。
配线层20包含第一连接区域22和第二连接区域23。第一连接区域22和第二连接区域23分别为连接不同部件的区域。第一连接区域22俯视而言是在基板6的一端部侧的区域形成。第二连接区域23俯视而言是相对于第一连接区域22在基板6的另一端部侧的区域形成。
配线层20只要包含第一连接区域22和第二连接区域23则可以采取任意的方式。例如,配线层20可以包含:岛状的第一连接区域22、岛状的第二连接区域23、以及将第一连接区域22和第二连接区域23连接的线状的连接区域。
该情况下,第一连接区域22和第二连接区域23可以形成为俯视呈四边形状、圆形状等任意的形状。另外,连接区域可以在第一连接区域22和第二连接区域23之间的区域选择性地引绕。
MISFET芯片21包含长方体形状的芯片主体24。芯片主体24包含:一侧的第一芯片主面25、另一侧的第二芯片主面26、以及将第一芯片主面25和第二芯片主面26连接的芯片侧面27。MISFET芯片21的第一芯片主面25是形成有电路元件(在该方式中为MISFET)的元件形成面。
MISFET芯片21可以是具有含Si的芯片主体24的Si-MISFET芯片。Si-MISFET芯片的耐压可以为30V以上4500V以下。MISFET芯片的耐压由能够施加于漏极/源极间的最大的电压VDS定义。
MISFET芯片21可以是具有包含化合物半导体的芯片主体24的MISFET芯片。芯片主体24可以包含氮化物半导体或者氧化物半导体作为化合物半导体。
氮化物半导体可以包含氮化镓(GaN)。氧化物半导体可以包含氧化镓(Ga2O3)。包含化合物半导体的MISFET芯片的耐压可以为600V以上10000V以下。
MISFET芯片21可以是具有包含SiC的芯片主体24的SiC-MISFET芯片。SiC-MISFET芯片的耐压可以为600V以上15000V以下。
尤其是,在包含化合物半导体的MISFET芯片、SiC-MISFET芯片中,可能会因为大电流所引起的发热而达到高温。电子元器件1具有对于这些高功率型的芯片而言有益的结构。
MISFET芯片21包含:栅极端子电极层28、源极端子电极层29、源极取样端子电极层30和漏极端子电极层31。栅极端子电极层28、源极端子电极层29和源极取样端子电极层30在芯片主体24的第一芯片主面25上选择性地形成。漏极端子电极层31与芯片主体24的第二芯片主面26连接。
MISFET芯片21以使芯片主体24的第二芯片主面26与基板6的第一基板主面9对置的姿态与配线层20的第一连接区域22接合。漏极端子电极层31经由导电性接合材32与配线层20的第一连接区域22接合。即,配线层20形成了漏极配线层。
导电性接合材32可以包含低熔点金属或者金属制膏体。低熔点金属可以包含焊锡等。金属制膏体可以包含铜膏体、银膏体、金膏体等。
栅极端子电极层28、源极端子电极层29、源极取样端子电极层30和漏极端子电极层31的配置、形状、大小等并不限定于特定的方式。栅极端子电极层28、源极端子电极层29、源极取样端子电极层30和漏极端子电极层31的配置、形状、大小等可以根据MISFET芯片21的规格而采用多种方式。
例如,栅极端子电极层28、源极端子电极层29和/或源极取样端子电极层30可以包含:在岛状的焊垫部、和从焊垫部起在芯片主体24的第一芯片主面25上选择性地引绕的线状的线部。
MISFET芯片21可以包含形成在芯片主体24的第一芯片主面25上的多层配线结构。多层配线结构可以是配线层和绝缘层交替层叠的结构。栅极端子电极层28、源极端子电极层29和/或源极取样端子电极层30可以在多层配线结构中形成为最上配线层。
参照图3和图4,封固绝缘层8在基板6的第一基板主面9上(具体而言是在主面绝缘层7上)封固了MISFET芯片21。在封固绝缘层8形成有:栅极焊垫开口33、源极焊垫开口34、源极取样焊垫开口35和漏极焊垫开口36。
栅极焊垫开口33使MISFET芯片21的栅极端子电极层28选择性地露出。源极焊垫开口34使MISFET芯片21的源极端子电极层29选择性地露出。
源极取样焊垫开口35使MISFET芯片21的源极取样端子电极层30选择性地露出。漏极焊垫开口36使配线层20的第二连接区域23选择性地露出。
栅极外部端子15埋入栅极焊垫开口33。栅极外部端子15在栅极焊垫开口33内与栅极端子电极层28连接。栅极外部端子15包含沿着芯片主体24的第一芯片主面25的法线方向立设的柱状的栅极柱状电极层40。
栅极柱状电极层40包含进行外部连接的栅极连接部41。栅极连接部41从封固绝缘层8的第一封固主面12露出。栅极连接部41具有与封固绝缘层8的第一封固主面12表面一致的连接面。
栅极柱状电极层40可以是以铜为主成分的铜电极层。栅极柱状电极层40可以包含铜种层、和在铜种层上形成的铜镀敷层。栅极柱状电极层40还可以包括含钛的势垒层。该情况下,铜种层可以形成在势垒层上。
源极外部端子16埋入源极焊垫开口34。源极外部端子16在源极焊垫开口34内与源极端子电极层29连接。源极外部端子16包含沿着芯片主体24的第一芯片主面25的法线方向立设的柱状的源极柱状电极层42。
源极柱状电极层42包含进行外部连接的源极连接部43。源极连接部43从封固绝缘层8的第一封固主面12露出。源极连接部43具有与封固绝缘层8的第一封固主面12表面一致的连接面。源极柱状电极层42可以是与栅极柱状电极层40的结构同样的结构。
源极取样外部端子17埋入源极取样焊垫开口35。源极取样外部端子17在源极取样焊垫开口35内与源极取样端子电极层30连接。源极取样外部端子17包含沿着芯片主体24的第一芯片主面25的法线方向立设的柱状的源极取样柱状电极层44。
源极取样柱状电极层44包含进行外部连接的源极取样连接部45。源极取样柱状电极层44从封固绝缘层8的第一封固主面12露出。源极取样连接部45具有与封固绝缘层8的第一封固主面12表面一致的连接面。源极取样柱状电极层44可以是与栅极柱状电极层40的结构同样的结构。
漏极外部端子18埋入漏极焊垫开口36。漏极外部端子18在漏极焊垫开口36内与配线层20的第二连接区域23连接。
漏极外部端子18经由配线层20与MISFET芯片21的漏极端子电极层31电连接。漏极外部端子18包含沿着基板6的第一基板主面9的法线方向立设的柱状的漏极柱状电极层46。
漏极柱状电极层46包含进行外部连接的漏极连接部47。漏极柱状电极层46从封固绝缘层8的第一封固主面12露出。漏极连接部47具有与封固绝缘层8的第一封固主面12表面一致的连接面。漏极柱状电极层46可以是与栅极柱状电极层40的结构同样的结构。
以上,在电子元器件1中,基板6是由具有比较高的导热率的半导体基板构成。基板6的基板侧面11从封固绝缘层8露出。而且,在电子元器件1中,基板6的基板6的基板侧面11也从封固绝缘层8露出。
因此,即使不从基板6的基板侧面11引出外部端子,也能够使MISFET芯片21产生的热从基板6的第二基板主面10和基板侧面11向外部高效地散放。由此,能够适当地抑制封固绝缘层8内部的温度上升。
而且,不必从基板6的基板侧面11引出栅极外部端子15、源极外部端子16、源极取样外部端子17和漏极外部端子18。因此,MISFET芯片21与这些外部端子的连接不必使用键合引线等连接部件。其结果是,能够削减零件数量而实现缩减化。因此,可提供一种能够兼顾小型化和散热性的提高的电子元器件1。
特别是,在电子元器件1中,栅极外部端子15、源极外部端子16、源极取样外部端子17和漏极外部端子18均为其整个区域形成在由基板6的周缘包围的区域内。
此外,栅极外部端子15、源极外部端子16和源极取样外部端子17俯视而言是收敛在被MISFET芯片21的周缘包围的四边形状的区域内。
由此,不必以沿着基板6的第一基板主面9相邻的方式来配置MISFET芯片21、栅极外部端子15、源极外部端子16和源极取样外部端子17。因此,就多个外部端子的布局而言,能够适当地实现电子元器件1的小型化。
另外,在基板6由半导体基板构成的情况下,能够利用半导体装置的制造工艺来制造电子元器件1。即,能够在精细化的基板6上配置微小的MISFET芯片21。因此,在基板6由半导体基板构成的情况下,就半导体装置的制造工艺而言,也能够实现电子元器件1的小型化。
另外,在电子元器件1中,是在基板6的第一基板主面9上形成有主面绝缘层7。由此,能够利用半导体基板散热效果的优点并提高MISFET芯片21对施加电压的绝缘耐量。特别是,当主面绝缘层7由氮化硅构成时,能够适当地实现散热性的提高和绝缘耐量的提高。
另外,在电子元器件1中,在基板6的第一基板主面9上形成有配线层20。该配线层20的俯视面积大于MISFET芯片21的俯视面积。
由此,能够使MISFET芯片21产生的热经由配线层20向主面绝缘层7和基板6高效地传导。因此,能够高效地抑制封固绝缘层8内部的温度上升。
在小型的电子元器件中,认为会由于电流路径的面积缩小而使电阻值升高。考虑到这一点,在电子元器件1中,栅极外部端子15包含栅极柱状电极层40。另外,源极外部端子16包含源极柱状电极层42。另外,源极取样外部端子17包含源极取样柱状电极层44。另外,漏极外部端子18包含漏极柱状电极层46。
由此,与键合引线等的连接部件相比能够确保比较大面积的电流路径。因此,能够抑制电阻值的上升。尤其是,在栅极柱状电极层40、源极柱状电极层42、源极取样柱状电极层44和漏极柱状电极层46均含铜的情况下,能够有效地抑制电阻值的上升。
此外,在电子元器件1中,栅极外部端子15、源极外部端子16、源极取样外部端子17和漏极外部端子18均从元器件主体2的安装面3露出。
由此,在电子元器件1安装于安装基板等的连接对象物的情况下,能够经由该多个外部端子使MISFET芯片21产生的热向连接对象物传导。因此,也能够使多个外部端子促进散热性的提高。
图5A~图5K是用于说明图1的电子元器件1的制造方法的一例的剖视图。虽然在电子元器件1的制造工序中能够同时制造多个电子元器件1,但是在图5A~图5K中为了便于说明而仅示出了形成两个电子元器件1的区域。
首先,参照图5A来准备成为基板6的基底的板状的基底基板51。基底基板51的材料可与基板6的材料对应地进行选择。在该方式中,基底基板51由硅晶圆构成。
基底基板51包含一侧的第一基板主面52和另一侧的第二基板主面53。基底基板51的第一基板主面52与基板6的第一基板主面9对应。基底基板51的第二基板主面53与基板6的第二基板主面10对应。
在基底基板51设定有划出多个元器件形成区域54和多个元器件形成区域54的边界区域55。元器件形成区域54是形成电子元器件1的区域。边界区域55是分割线。
接下来,参照图5B在基底基板51的第一基板主面52上形成主面绝缘层7。在此,形成由氮化硅构成的主面绝缘层7。主面绝缘层7形成为与所需的绝缘耐压对应的厚度。
主面绝缘层7的厚度可以为0.1μm以上100μm以下(优选为0.1μm以上10μm以下)。主面绝缘层7可以通过CVD法或者PVD法形成。
也可以形成取代氮化硅而包含氧化硅的主面绝缘层7,或者是形成除了氮化硅之外还包括氧化硅的主面绝缘层7。此时,主面绝缘层7可以采用CVD法形成。主面绝缘层7可以通过氧化处理法使基底基板51的表面氧化而形成。氧化处理法可以是热氧化处理法,也可以为湿氧化处理法。
接下来,参照图5C,配线层20在各元器件形成区域54形成。在该工序中,首先,在主面绝缘层7上形成含钛的势垒层(未图示)和铜种层(未图示)。势垒层和铜种层可以分别通过溅射法形成。
接下来,在铜种层上形成铜镀敷层(未图示)。铜镀敷层可以采用电解铜镀敷法形成。接下来,将包含势垒层、铜种层和铜镀敷层的层叠膜通过经由抗蚀剂掩模(未图示)的蚀刻法选择性地除去。由此,在各元器件形成区域54形成配线层20。
接下来,参照图5D,使MISFET芯片21与各配线层20接合。使MISFET芯片21经由导电性接合材32与各配线层20的第一连接区域22接合。
导电性接合材32可以是焊锡。MISFET芯片21的结构和MISFET芯片21与各配线层20的连接方式如图1~图4所示。
接下来,参照图5E,在主面绝缘层7上形成具有预定的图案的抗蚀剂掩模56。抗蚀剂掩模56具有多个开口57。多个开口57在抗蚀剂掩模56中使要形成栅极柱状电极层40、源极柱状电极层42、源极取样柱状电极层44和漏极柱状电极层46的区域分别露出。
接下来,参照图5F,在多个开口57内形成栅极柱状电极层40、源极柱状电极层42、源极取样柱状电极层44和漏极柱状电极层46。栅极柱状电极层40、源极柱状电极层42、源极取样柱状电极层44和漏极柱状电极层46可以通过经由抗蚀剂掩模56的多个开口57的电解铜镀敷法形成。
接下来,参照图5G,将抗蚀剂掩模56除去。由此,栅极柱状电极层40、源极柱状电极层42、源极取样柱状电极层44和漏极柱状电极层46以立设状态残留。
栅极柱状电极层40、源极柱状电极层42、源极取样柱状电极层44和漏极柱状电极层46也可以取代经由抗蚀剂掩模56的电解铜镀敷法而利用烧制工艺形成。
在烧制工艺中,首先,在主面绝缘层7上涂布成为柱状电极层的基底的导电性膏体。导电性膏体可以是铜膏体。接下来,按照与栅极柱状电极层40、源极柱状电极层42、源极取样柱状电极层44和漏极柱状电极层46对应的图案将导电性膏体的不需要的部分除去。
之后,对导电性膏体进行烧制。由此,形成栅极柱状电极层40、源极柱状电极层42、源极取样柱状电极层44和漏极柱状电极层46。
接下来,参照图5H,在主面绝缘层7上涂布成为封固绝缘层8的基底的封固树脂58。封固树脂58可以包含环氧树脂或者聚酰亚胺树脂。
封固树脂58在主面绝缘层7上将配线层20、MISFET芯片21、栅极柱状电极层40、源极柱状电极层42、源极取样柱状电极层44和漏极柱状电极层46一并封固。
封固绝缘层8可以由氧化硅或者氮化硅形成。该情况下,氧化硅或者氮化硅可以通过CVD法在主面绝缘层7上沉积。
接下来,参照图5I,从MISFET芯片21的第二芯片主面26侧将封固树脂58的外表面部分地除去。将封固树脂58的外表面除去,直到栅极柱状电极层40、源极柱状电极层42、源极取样柱状电极层44和漏极柱状电极层46露出为止。封固树脂58的除去工序也可以通过磨削法进行。
由此,参照图5J,形成栅极柱状电极层40、源极柱状电极层42、源极取样柱状电极层44和漏极柱状电极层46露出的封固绝缘层8。
接下来,参照图5K,沿着边界区域55将基底基板51切断。基底基板51也可以使用分割刀通过磨削进行切断。由此,从一个基底基板51切出多个电子元器件1。
基底基板51也可以通过蚀刻法进行切断。蚀刻法可以是等离子体蚀刻法。该情况下,可形成侧面5没有磨削加工痕的元器件主体2。经由以上工序来制造电子元器件1。
图6是与图3对应的部分的剖视图,用于对本发明的第二实施方式的电子元器件61的结构进行说明。图7是与图4对应的部分的剖视图,用于对图6的电子元器件61的结构进行说明。以下对于与针对电子元器件1进行了说明的结构对应的结构标记同一参照符号而省略说明。
在该方式中,栅极外部端子15包含形成在栅极柱状电极层40上的栅极导电接合层62。栅极导电接合层62与栅极连接部41电连接。栅极导电接合层62在栅极连接部41上形成。
栅极导电接合层62可以具有将封固绝缘层8的第一封固主面12覆盖的覆盖部。栅极导电接合层62的整体从栅极焊垫开口33露出。栅极导电接合层62可以包含低熔点金属。低熔点金属可以包含焊锡。栅极导电接合层62可以具有凸弯曲状的外表面。
源极外部端子16包含形成在源极柱状电极层42上的源极导电接合层63。源极导电接合层63与源极连接部43电连接。源极导电接合层63在源极连接部43上形成。
源极导电接合层63可以具有将封固绝缘层8的第一封固主面12覆盖的覆盖部。源极导电接合层63的整体从源极焊垫开口34露出。源极导电接合层63可以包含低熔点金属。低熔点金属可以包含焊锡。源极导电接合层63可以具有凸弯曲状的外表面。
源极取样外部端子17包含形成在源极取样柱状电极层44上的源极取样导电接合层64。源极取样导电接合层64与源极取样连接部45电连接。源极取样导电接合层64在源极取样连接部45上形成。
源极取样导电接合层64可以具有将封固绝缘层8的第一封固主面12覆盖的覆盖部。源极取样导电接合层64的整体从源极取样焊垫开口35露出。
源极取样导电接合层64可以包含低熔点金属。低熔点金属可以包含焊锡。源极取样导电接合层64可以具有凸弯曲状的外表面。
漏极外部端子18包含形成在漏极柱状电极层46上的漏极导电接合层65。漏极导电接合层65与漏极连接部47电连接。漏极导电接合层65在漏极连接部47上形成。
漏极导电接合层65可以具有将封固绝缘层8的第一封固主面12覆盖的覆盖部。漏极导电接合层65的整体从漏极焊垫开口36露出。漏极导电接合层65可以包含低熔点金属。低熔点金属可以包含焊锡。漏极导电接合层65可以具有凸弯曲状的外表面。
在电子元器件1的制造方法中,通过进一步实施形成栅极导电接合层62、源极导电接合层63、源极取样导电接合层64和漏极导电接合层65的工序而能够制得电子元器件61。
导电接合层的形成工序可以在前述的封固树脂58的磨削工序(参照图5J)之后并且在前述的基底基板51的切断工序(参照图5K)之前实施。导电接合层可以通过电解焊锡镀敷法形成。
以上采用电子元器件61也能够获得与针对电子元器件1进行了说明的效果同样的效果。
图8是与图3对应的部分的剖视图,用于对本发明的第三实施方式的电子元器件71的结构进行说明。图9是与图4对应的部分的剖视图,用于对图8的电子元器件71的结构进行说明。以下对于与针对电子元器件1进行了说明的结构对应的结构标记同一参照符号而省略说明。
栅极外部端子15取代栅极柱状电极层40而包含栅极电极膜72和栅极导电接合层73。栅极电极膜72是构成栅极导电接合层73的基底的基底层,也称为UBM(under bumpmetal:凸点下金属)层。栅极电极膜72沿着栅极焊垫开口33的内壁形成为膜状。栅极电极膜72在栅极焊垫开口33内划分出凹状的空间。
栅极电极膜72在栅极焊垫开口33外的区域具有将封固绝缘层8的第一封固主面12覆盖的覆盖部74。栅极电极膜72可以包含铜膜、金膜、钛膜和镍膜中的至少一种。
栅极导电接合层73在栅极电极膜72上形成。栅极导电接合层73埋没栅极焊垫开口33。栅极导电接合层73比封固绝缘层8的第一封固主面12向上方突出。
栅极导电接合层73在栅极焊垫开口33外的区域将栅极电极膜72的覆盖部74覆盖。栅极导电接合层62可以包含低熔点金属。低熔点金属可以包含焊锡。栅极导电接合层62可以具有凸弯曲状的外表面。
源极外部端子16取代源极柱状电极层42而包含源极电极膜75和源极导电接合层76。源极电极膜75是构成源极导电接合层76的基底的基底层,也称为UBM层。源极电极膜75沿着源极焊垫开口34的内壁形成为膜状。源极电极膜75在源极焊垫开口34内划分出凹状的空间。
源极电极膜75在源极焊垫开口34外的区域具有将封固绝缘层8的第一封固主面12覆盖的覆盖部77。源极电极膜75可以包含铜膜、金膜、钛膜和镍膜中的至少一种。
源极导电接合层76在源极电极膜75上形成。源极导电接合层76埋没源极焊垫开口34,并比封固绝缘层8的第一封固主面12向上方突出。
源极导电接合层76在源极焊垫开口34外的区域将源极电极膜75的覆盖部77覆盖。源极导电接合层76可以包含低熔点金属。低熔点金属可以包含焊锡。源极导电接合层76可以具有凸弯曲状的外表面。
源极取样外部端子17取代源极取样柱状电极层44而包含源极取样电极膜78和源极取样导电接合层79。源极取样电极膜78是构成源极取样导电接合层79的基底的基底层,也称为UBM层。
源极取样电极膜78沿着源极取样焊垫开口35的内壁形成为膜状。源极取样电极膜78在源极取样焊垫开口35内划分出凹状的空间。
源极取样电极膜78在源极取样焊垫开口35外的区域具有将封固绝缘层8的第一封固主面12覆盖的覆盖部80。源极取样电极膜78可以包含铜膜、金膜、钛膜和镍膜中的至少一种。
源极取样导电接合层79在源极取样电极膜78上形成。源极取样导电接合层79埋没源极取样焊垫开口35,并比封固绝缘层8的第一封固主面12向上方突出。
源极取样导电接合层79在源极取样焊垫开口35外的区域将源极取样电极膜78的覆盖部80覆盖。源极取样电极膜78可以包含低熔点金属。低熔点金属可以包含焊锡。源极取样电极膜78可以具有凸弯曲状的外表面。
漏极外部端子18取代漏极柱状电极层46(参照图3)而包含漏极电极膜81和漏极导电接合层82。漏极电极膜81是构成漏极导电接合层82的基底的基底层,也称为UBM层。
漏极电极膜81沿着漏极焊垫开口36的内壁形成为膜状。漏极电极膜81在漏极焊垫开口36内划分出凹状的空间。
漏极电极膜81在漏极焊垫开口36外的区域具有将封固绝缘层8的第一封固主面12覆盖的覆盖部83。漏极电极膜81可以包含铜膜、金膜、钛膜和镍膜中的至少一种。
漏极导电接合层82在漏极电极膜81上形成。漏极导电接合层82埋没漏极焊垫开口36,并比封固绝缘层8的第一封固主面12向上方突出。
漏极导电接合层82在漏极焊垫开口36外的区域将漏极电极膜81的覆盖部83覆盖。漏极导电接合层82可以包含低熔点金属。低熔点金属可以包含焊锡。漏极导电接合层82可以具有凸弯曲状的外表面。
图10A~图10E是用于对图8的电子元器件71的制造方法的一例进行说明的剖视图。在此,对于和前述的第一实施方式的电子元器件1的制造工序共通的工序省略具体的说明。
首先,参照图10A来准备MISFET芯片21的接合工序后的基底基板51(一并参照图5D)。
接下来,参照图10B,在主面绝缘层7上涂布成为封固绝缘层8的基底的封固树脂84。封固树脂84在主面绝缘层7上将配线层20和MISFET芯片21一并封固。
接下来,参照图10C,在封固树脂84形成栅极焊垫开口33、源极焊垫开口34、源极取样焊垫开口35和漏极焊垫开口36。在封固树脂84由光致抗蚀剂构成的情况下,各开口可以通过曝光和显影而形成。
封固树脂84可以由氧化硅或者氮化硅等的绝缘材料形成。氧化硅或者氮化硅可以通过CVD法在主面绝缘层7上沉积。当封固树脂84由绝缘材料构成时,各开口可以通过蚀刻法形成。
接下来,参照图10D,形成栅极电极膜72、源极电极膜75、源极取样电极膜78和漏极电极膜81。在该工序中,首先,通过溅射法和/或电解镀敷法形成导电材料层。
接下来,将导电材料层通过经由抗蚀剂掩模(未图示)的蚀刻法选择性地除去。由此,形成栅极电极膜72、源极电极膜75、源极取样电极膜78和漏极电极膜81。
接下来,参照图10E,形成栅极导电接合层62、源极导电接合层76、源极取样导电接合层79和漏极导电接合层82。各导电接合层可以通过电解焊锡镀敷法形成。
之后,沿着边界区域55将基底基板51切断(一并参照图5K)。由此,从一个基底基板51切出多个电子元器件71。经由以上的工序来制造电子元器件71。
以上采用电子元器件71也能够获得与针对电子元器件1进行了说明的效果同样的效果。
图11是与图3对应的部分的剖视图,用于对本发明的第四实施方式的电子元器件91的结构进行说明。以下对于与针对电子元器件1进行了说明的结构对应的结构标记同一参照符号而省略说明。
电子元器件91包含使MISFET芯片21产生的热向外部散放的散热结构92。散热结构92在基板6的第二基板主面10设置。
在该方式中,散热结构92包含形成在基板6的第二基板主面10的翼片结构93。翼片结构93在基板6的第二基板主面10包含从基板6的第二基板主面10朝向第一基板主面9下挖的一个或者多个沟槽94。各沟槽的深度可以为1μm以上500μm以下。
在翼片结构93包含一个沟槽94的情况下,一个沟槽94可以形成为俯视呈格子状、曲折状、梳齿状或者螺旋状。在翼片结构93包含多个沟槽94的情况下,多个沟槽94可以形成为俯视呈条带状或者点状。也可以形成由这些俯视形状组合而成的一个或者多个沟槽94。
图12A~图12C是用于对图11的电子元器件91的制造方法的一例进行说明的剖视图。在此,对于和前述的第一实施方式的电子元器件1的制造工序共通的工序省略具体的说明。
形成翼片结构93的工序可以在前述的基底基板51的切断工序(参照图5K)之前在任意的时刻实施。以下对于形成翼片结构93的工序在基底基板51的准备工序(参照图5A)之后并且在主面绝缘层7的形成工序(参照图5B)之前实施的例子进行说明。
参照图12A,在准备了基底基板51之后,在基底基板51的第二基板主面53形成具有预定的图案的抗蚀剂掩模95。抗蚀剂掩模95具有使要形成沟槽94的区域选择性地露出的开口96。
接下来,参照图12B,通过经由抗蚀剂掩模95的蚀刻法将基底基板51的不需要的部分除去。由此,在基底基板51的第二基板主面53形成包含一个或者多个沟槽94的翼片结构93。
接下来,参照图12C,将抗蚀剂掩模95除去。之后,依次执行图5B~图5K的工序来制造电子元器件91。
以上采用电子元器件91也能够获得与针对电子元器件1进行了说明的效果同样的效果。
另外,根据电子元器件91,在基板6的第二基板主面10形成有包含翼片结构93的散热结构92。采用翼片结构93,能够增加基板6的表面积。由此,能够使从MISFET芯片21向基板6传导的热向外部高效地散放。
另外,根据电子元器件91,能够利用基板6的一部分的区域来形成翼片结构93。由此,不必在基板6的第二基板主面10安装例如金属制散热片等散热器具。因此,能够抑制元器件主体2沿着安装面3和非安装面4的法线方向变厚。因此,能够实现电子元器件91的小型化并提高散热性。
散热结构92可以取代翼片结构93而包含作为散热部件的金属膜。金属膜可以沿着基板6的第二基板主面10和沟槽94的内壁形成。
金属膜可以将第二基板主面10的整个区域覆盖并充满沟槽94内部的整个区域。金属膜可以包含铜膜、金膜、银膜、镍膜、钛膜、铝膜等。
金属膜可以通过溅射法和/或镀敷法形成。形成金属膜的工序可以在前述的抗蚀剂掩模95的除去工序(一并参照图12C)之后在任意的时刻实施。采用这种结构的散热结构92,能够进一步提高基板6的散热性。
也可以将第二实施方式的结构、或者第三实施方式的结构、或者是第二实施方式的结构和第三实施方式的结构组合而成的结构适用于电子元器件91。
图13是与图3对应的部分的剖视图,用于对本发明的第五实施方式的电子元器件101的结构进行说明。以下对于与针对电子元器件1进行了说明的结构对应的结构标记同一参照符号而省略说明。
电子元器件101包含使MISFET芯片21产生的热向外部散放的散热结构102。散热结构102在基板6的第二基板主面10设置。在该方式中,散热结构102包含将基板6的第二基板主面10覆盖的散热部件103。
散热部件103可以是与基板6的第二基板主面10连接的散热板。散热板可以是金属板。金属板可以包含铜板、金板、镍板、钛板、铝板等。
散热部件103可以取代散热板而是通过溅射法和/或镀敷法形成的金属膜。金属膜可以包含铜膜、金膜、银膜、镍膜、钛膜、铝膜等。形成散热部件103的工序可以在前述的基底基板51的切断工序(一并参照图5K)之前实施。
以上采用电子元器件101也能够获得与针对电子元器件1进行了说明的效果同样的效果。
另外,根据电子元器件101,在基板6的第二基板主面10形成有包含散热部件103的散热结构102。由此,能够使从MISFET芯片21向基板6传导的热向外部高效地散放。
特别是,采用包含金属膜的散热部件103,能够抑制元器件主体2沿着安装面3和非安装面4的法线方向变厚。因此,能够实现电子元器件101的小型化并提高散热性。
也可以将第二实施方式的结构、第三实施方式的结构、或者第四实施方式的结构、或者是第二~第四实施方式的结构中的任意的两个结构或者三个结构组合而成的结构适用于电子元器件101。
图14是用于对本发明的第六实施方式的电子元器件111的结构进行说明的图。以下对于与针对电子元器件1进行了说明的结构对应的结构标记同一参照符号而省略说明。
电子元器件111是包含作为半导体整流元件的一例的二极管的半导体装置。二极管可采用pn结二极管、快速恢复二极管、齐纳二极管、肖特基势垒二极管等多种二极管。在本实施方式中二极管采用了肖特基势垒二极管。
电子元器件111取代MISFET芯片21而包含二极管芯片112。二极管芯片112包含长方体形状的芯片主体113。芯片主体113包含:一侧的第一芯片主面114、另一侧的第二芯片主面115、以及将第一芯片主面114和第二芯片主面115连接的芯片侧面116。
二极管芯片112可以是具有含Si的芯片主体113的Si-二极管芯片。Si-二极管芯片的耐压可以为30V以上6500V以下。Si-二极管芯片的耐压由能够施加于正极/负极间的最大的反向电压VR定义。
二极管芯片112可以是具有包含化合物半导体的芯片主体113的二极管芯片。芯片主体113可以包含作为化合物半导体的氮化物半导体或者氧化物半导体。
氮化物半导体可以包含氮化镓(GaN)。氧化物半导体可以包含氧化镓(Ga2O3)。包含化合物半导体的二极管芯片的耐压可以为600V以上10000V以下。
二极管芯片112可以是具有包含SiC的芯片主体113的SiC-二极管芯片。SiC-二极管芯片的耐压可以为600V以上15000V以下。
尤其是,在包含化合物半导体的二极管芯片、SiC-二极管芯片,可能会因为大电流引起的发热而达到高温。电子元器件111是对于这些高功率型的二极管芯片有益的结构。
二极管芯片112包含负极端子电极层117和正极端子电极层118。负极端子电极层117在芯片主体113的第一芯片主面114上形成。正极端子电极层118在芯片主体113的第二芯片主面115上形成。
二极管芯片112以使芯片主体113的第二芯片主面115与基板6的第一基板主面9对置的姿态在基板6的第一基板主面9上配置。正极端子电极层118经由导电性接合材119与配线层20的第一连接区域22接合。即,配线层20形成了正极配线层。
导电性接合材119可以包含低熔点金属或者金属制膏体。低熔点金属可以包含焊锡。金属制膏体可以包含铜膏体、银膏体、金膏体等。
负极端子电极层117和正极端子电极层118的配置、形状、大小等并不限定于特定的方式。负极端子电极层117和正极端子电极层118的配置、形状、大小等可以根据二极管芯片112的规格而采用多种方式。
负极端子电极层117可以包含形成在第一芯片主面114上的岛状的焊垫部、和从焊垫部起在第一芯片主面114上选择性地引绕的线状的线部。
正极端子电极层118可以包含形成在第一芯片主面114上的岛状的焊垫部、和从焊垫部起在第二芯片主面115上选择性地引绕的线状的线部。
二极管芯片112可以包含形成在芯片主体113的第一芯片主面114和/或第二芯片主面115上的多层配线结构。多层配线结构可以包含配线层和绝缘层交替层叠的结构。
在第一芯片主面114上形成有多层配线结构的情况下,负极端子电极层117可以在多层配线结构中形成为最上配线层。在第二芯片主面115上形成有多层配线结构的情况下,正极端子电极层118可以在多层配线结构中形成为最上配线层。
二极管芯片112可以包含多个(两个以上)的负极端子电极层117。二极管芯片112可以包含多个(两个以上)的正极端子电极层118。
在封固绝缘层8形成有负极焊垫开口120和正极焊垫开口121。负极焊垫开口120使二极管芯片112的负极端子电极层117选择性地露出。正极焊垫开口121使配线层20的第二连接区域23选择性地露出。
电子元器件111包含负极外部端子122和正极外部端子123。负极外部端子122形成为芯片侧外部端子。正极外部端子123形成为配线层侧外部端子。
负极外部端子122埋入负极焊垫开口120。负极外部端子122在负极焊垫开口120内与负极端子电极层117连接。
负极外部端子122包含沿着芯片主体113的第一芯片主面114的法线方向立设的柱状的负极柱状电极层124。负极柱状电极层124包含进行外部连接的负极连接部125。
负极连接部125从封固绝缘层8的第一封固主面12露出。负极连接部125具有与封固绝缘层8的第一封固主面12表面一致的连接面。负极柱状电极层124可以包含铜。
正极外部端子123埋入正极焊垫开口121。正极外部端子123在正极焊垫开口121内与配线层20的第二连接区域23连接。正极外部端子123经由配线层20与二极管芯片112的正极端子电极层118电连接。
正极外部端子123包含沿着基板6的第一基板主面9的法线方向立设的柱状的正极柱状电极层126。正极柱状电极层126包含进行外部连接的正极连接部127。
正极连接部127从封固绝缘层8的第一封固主面12露出。正极连接部127具有与封固绝缘层8的第一封固主面12表面一致的连接面。正极柱状电极层126可以包含铜。
电子元器件111能够经过与前述的电子元器件1的制造方法大致同样的工序来制造。以上采用取代MISFET芯片21而包含二极管芯片112的电子元器件111也能够获得与针对电子元器件1进行了说明的效果同样的效果。
二极管芯片112可以是以芯片主体113的第一芯片主面114与基板6的第一基板主面9对置的姿态在基板6的第一基板主面9上配置。即,也可以采用交换了正极和负极的连接方式的结构。该情况下,负极端子电极层117经由导电性接合材119与配线层20的第一连接区域22接合。即,配线层20形成负极配线层。
也可以将第二实施方式的结构、第三实施方式的结构、第四实施方式的结构或者第五实施方式的结构、或者是第二~第五实施方式中的任意的两个结构、三个结构或者四个结构组合而成的结构适用于电子元器件111。
图15是用于对本发明的第七实施方式的电子元器件131的内部结构进行说明的俯视图。图16是沿着图15的XVI-XVI线的剖视图。以下对于与针对电子元器件1进行了说明的结构对应的结构标记同一参照符号而省略说明。
参照图15和图16,电子元器件131是包含多个芯片的半导体功率模块。电子元器件131除了MISFET芯片21之外还包括二极管芯片112和IC芯片132(控制芯片)。MISFET芯片21、二极管芯片112和IC芯片132相对于基板6的第一基板主面9的配置位置是任意的,而并不限定于特定的配置位置。
电子元器件131包含:MISFET芯片21用的第一配线层133、二极管芯片112用的第二配线层134、和IC芯片132用的第三配线层135。第一配线层133、第二配线层134和第三配线层135具有与前述的配线层20同样的结构。
在第一配线层133连接有MISFET芯片21和漏极外部端子18。MISFET芯片21和漏极外部端子18相对于第一配线层133的连接方式与前述的电子元器件1的情况是同样的。
在第二配线层134连接有二极管芯片112。二极管芯片112相对于第二配线层134的连接方式与前述的电子元器件111的情况是同样的。但是在该方式中,并未设置负极外部端子122和正极外部端子123。
在第三配线层135连接有输入外部端子136和IC芯片132。输入外部端子136形成为配线层侧外部端子。输入外部端子136是用于向IC芯片132供电的端子。输入外部端子136经由第三配线层135与IC芯片132电连接。
输入外部端子136的结构与漏极外部端子18的结构是大致同样的。输入外部端子136相对于第三配线层135的连接方式与漏极外部端子18相对于第一配线层133的连接方式是同样的。
在该方式中,IC芯片132是用于对MISFET芯片21的栅极进行驱动控制的栅极驱动器IC。IC芯片132包含长方体形状的芯片主体141。芯片主体141包含:一侧的第一芯片主面142、另一侧的第二芯片主面143、以及将第一芯片主面142和第二芯片主面143连接的芯片侧面144。
IC芯片132包含输出端子电极层145和输入端子电极层146。输出端子电极层145在芯片主体141的第一芯片主面142上形成。输入端子电极层146在芯片主体141的第二芯片主面143上形成。
输入端子电极层146经由导电性接合材147与第三配线层135接合。由此,IC芯片132经由第三配线层135与输入外部端子136电连接。
导电性接合材147可以包含低熔点金属或者金属制膏体。低熔点金属可以包含焊锡。金属制膏体可以包含铜膏体、银膏体、金膏体等。
输出端子电极层145和输入端子电极层146的配置、形状、大小等并不限定于特定的方式。输出端子电极层145和输入端子电极层146的配置、形状、大小等可以根据IC芯片132的规格而采用多种方式。
多个输出端子电极层145可以在芯片主体141的第一芯片主面142上形成。一个或者多个输出端子电极层145可以包含岛状的焊垫部、和从焊垫部起在第一芯片主面142上选择性地引绕的线状的线部。
IC芯片132可以包含在芯片主体141的第一芯片主面142和/或第二芯片主面143上形成的多层配线结构。多层配线结构可以具有配线层和绝缘层交替层叠的结构。
在第一芯片主面142上形成有多层配线结构的情况下,输出端子电极层145可以在多层配线结构中形成为最上配线层。在第二芯片主面143上形成有多层配线结构的情况下,输入端子电极层146可以在多层配线结构中形成为最上配线层。
参照图16,电子元器件131包含中间绝缘层148。中间绝缘层148在主面绝缘层7上形成。在该方式中,中间绝缘层148的周缘相对于基板6的周缘在基板6的内侧区域空开间隔而形成。在中间绝缘层148的周缘和基板6的周缘之间的区域形成有台阶部。
中间绝缘层148可以将基板6的第一基板主面9的整个区域覆盖。该情况下,中间绝缘层148可以形成为与基板6的基板侧面11大致表面一致。中间绝缘层148可以具有与封固绝缘层8的封固侧面14和基板6的基板侧面11表面一致的侧面。
中间绝缘层148将MISFET芯片21、二极管芯片112和IC芯片132封固。中间绝缘层148可以包含氧化硅、氮化硅、环氧树脂和聚酰亚胺树脂中的至少一种。在该方式中,中间绝缘层148由包含聚酰亚胺树脂的中间封固树脂层构成。
在中间绝缘层148形成有栅极接触孔149、源极接触孔150、源极取样接触孔151、漏极接触孔152和负极接触孔153。在中间绝缘层148形成有输出接触孔154、第一配线接触孔155、第二配线接触孔156和输入接触孔157。
栅极接触孔149使MISFET芯片21的栅极端子电极层28选择性地露出。源极接触孔150使MISFET芯片21的源极端子电极层29选择性地露出。
源极取样接触孔151使MISFET芯片21的源极取样端子电极层30选择性地露出。漏极接触孔152使第一配线层133选择性地露出。
负极接触孔153使二极管芯片112的负极端子电极层117选择性地露出。输出接触孔154使IC芯片132的输出端子电极层145选择性地露出。
第一配线接触孔155使第一配线层133中异于漏极接触孔152的区域选择性地露出。第二配线接触孔156使第二配线层134选择性地露出。输入接触孔157使第三配线层135选择性地露出。
电子元器件131包含第一连接配线层161、第二连接配线层162和第三连接配线层163。第一连接配线层161、第二连接配线层162和第三连接配线层163在中间绝缘层148上分别形成。
第一连接配线层161在中间绝缘层148上选择性地引绕。第一连接配线层161在源极端子电极层29和第二配线层134之间的区域选择性地引绕。第一连接配线层161包含第一连接部164和第二连接部165。
第一连接部164与MISFET芯片21的源极端子电极层29连接。具体而言,第一连接部164从中间绝缘层148上进入源极接触孔150。第一连接部164在源极接触孔150内与源极端子电极层29连接。
第二连接部165与第二配线层134连接。具体而言,第二连接部165从中间绝缘层148上进入第二配线接触孔156。第一连接配线层161的第二连接部165在第二配线接触孔156内与第二配线层134连接。
第二连接配线层162在中间绝缘层148上选择性地引绕。第二连接配线层162在负极端子电极层117和第一配线层133之间的区域选择性地引绕。第二连接配线层162包含第一连接部166和第二连接部167。
第一连接部166与二极管芯片112的负极端子电极层117电连接。具体而言,第一连接部166从中间绝缘层148上进入负极接触孔153。第一连接部166在负极接触孔153内与负极端子电极层117连接。
第二连接部167与第一配线层133电连接。具体而言,第二连接部167从中间绝缘层148上进入第一配线接触孔155。第二连接部167在第一配线接触孔155内与第一配线层133连接。
第三连接配线层163在中间绝缘层148上选择性地引绕。第三连接配线层163在栅极端子电极层28和输出端子电极层145之间的区域选择性地引绕。第三连接配线层163包含第一连接部168和第二连接部169。
第一连接部168与MISFET芯片21的栅极端子电极层28电连接。具体而言,第一连接部168从中间绝缘层148上进入栅极接触孔149。第一连接部168在栅极接触孔149内与栅极端子电极层28连接。
第二连接部169与IC芯片132的输出端子电极层145电连接。具体而言,第二连接部169从中间绝缘层148上进入输出接触孔154。第三连接配线层163的第二连接部169在输出接触孔154内与输出端子电极层145连接。
在该方式中,封固绝缘层8在基板6的第一基板主面9上封固了中间绝缘层148。由此,MISFET芯片21、二极管芯片112和IC芯片132被中间绝缘层148和封固绝缘层8一并封固。
在封固绝缘层8形成有:栅极焊垫开口33、源极焊垫开口34、源极取样焊垫开口35、漏极焊垫开口36和输入端子焊垫开口170。漏极焊垫开口36与漏极接触孔152连通。输入端子焊垫开口170与输入接触孔157连通。
栅极外部端子15埋入栅极焊垫开口33。栅极外部端子15经由第三连接配线层163的第一连接部168与MISFET芯片21的栅极端子电极层28电连接。
源极外部端子16埋入源极焊垫开口34。源极外部端子16经由第一连接配线层161的第一连接部164与MISFET芯片21的源极端子电极层29电连接。
源极取样外部端子17埋入源极取样焊垫开口35。漏极外部端子18埋入漏极焊垫开口36。输入外部端子136埋入输入端子焊垫开口170。
图17是用于对图15所示电子元器件131的电气结构进行说明的电路图。
参照图17,二极管芯片112与MISFET芯片21连接。二极管芯片112作为续流二极管与MISFET芯片21连接。IC芯片132与MISFET芯片21的栅极连接。
以上采用电子元器件131也能够获得与针对电子元器件1进行了说明的效果同样的效果。
另外,根据电子元器件131,MISFET芯片21、二极管芯片112和IC芯片132进行单封装化。由此,通过将电子元器件131安装于安装基板等连接对象物,从而能够在一次的步骤中将MISFET芯片21、二极管芯片112和IC芯片132安装于安装基板。
另外,根据电子元器件131,中间绝缘层148夹设于基板6的第一基板主面9和封固绝缘层8之间的区域。中间绝缘层148将MISFET芯片21、二极管芯片112和IC芯片132覆盖。
在该中间绝缘层148上形成有第一连接配线层161、第二连接配线层162和第三连接配线层163。即,能够通过中间绝缘层148以相对于MISFET芯片21、二极管芯片112和IC芯片132沿着基板6的第一基板主面9的法线方向层叠的方式,做成嵌入的第一连接配线层161、第二连接配线层162和第三连接配线层163。
由此,不必将在MISFET芯片21、二极管芯片112和IC芯片132之间连接的配线,在沿着基板6的第一基板主面9的横方向上大幅地引出。由此,能够使MISFET芯片21、二极管芯片112和IC芯片132彼此接近配置。
因此,根据电子元器件131,与分别安装于安装基板等连接对象物的情况下相比,能够使包含MISFET芯片21、二极管芯片112和IC芯片132的电路网在安装基板等连接对象物中所占的专用面积减小。
在电子元器件131中,也可以采用形成有负极外部端子122和正极外部端子123的结构。在电子元器件131中,也可以采用在IC芯片132的输出端子电极层145连接有输出外部端子(未图示)的结构。输出外部端子可以具有与栅极外部端子15等同样的结构。
在电子元器件131中,也可以采用未形成第一连接配线层161、第二连接配线层162和第三连接配线层163的结构。该情况下,可以省略中间绝缘层148。
在电子元器件131中,也可以取代MISFET芯片21而设置第二的二极管芯片112。在电子元器件131中,可以设置多个(两个以上)的二极管芯片112。在电子元器件131中,可以省略MISFET芯片21。
在电子元器件131中,也可以取代二极管芯片112而设置第二MISFET芯片21。在电子元器件131中,可以设置多个(两个以上)的MISFET芯片21。在电子元器件131中,可以省略二极管芯片112。
在电子元器件131中,也可以将栅极驱动器IC以外的任意的IC芯片用作IC芯片132。在电子元器件131中,可以省略IC芯片132。
在电子元器件131中,也可以取代IC芯片132而设置无源元件芯片,或者是除了IC芯片132之外还设置无源元件芯片。无源元件芯片可以包含电容器、电阻和电感器中的至少一种。
无源元件芯片的连接对象是任意的。无源元件芯片可以与MISFET芯片21的栅极、源极或者漏极电连接。无源元件芯片可以与二极管芯片112的负极或者正极电连接。
也可以将第二实施方式的结构、第三实施方式的结构、第四实施方式的结构、第五实施方式的结构或者第六实施方式的结构、或者是这些之中的任意的两个、三个、四个或者五个的结构组合而成的结构适用于电子元器件131。
图18是与图3对应的部分的剖视图,是用于对本发明的第八实施方式的电子元器件181的结构进行说明的图。以下对于与针对电子元器件1进行了说明的结构对应的结构标记同一参照符号而省略说明。
在电子元器件181中,MISFET芯片21不经由导电性接合材32而是直接与配线层20接合。具体而言,MISFET芯片21的漏极端子电极层31直接与配线层20的第一连接区域22接合。
配线层20利用烧制工艺而形成。在配线层20的烧制工艺中,首先,在主面绝缘层7上涂布成为配线层20的基底的导电性膏体。导电性膏体可以是铜膏体。
接下来,以导电性膏体与漏极端子电极层31连接的方式,在导电性膏体上配置MISFET芯片21。之后,对导电性膏体进行烧制。由此,使漏极端子电极层31与配线层20接合。
以上采用电子元器件181也能够获得与针对电子元器件1进行了说明的效果同样的效果。
也可以将MISFET芯片21不经由导电性接合材32而直接与配线层20接合的方式,适用于第二实施方式的结构、第三实施方式的结构、第四实施方式的结构、第五实施方式的结构、第六实施方式的结构和第七实施方式的结构。
例如,在第六实施方式中,二极管芯片112可以与MISFET芯片21同样地,不经由导电性接合材119而是直接与配线层20接合。另外,在第七实施方式中,二极管芯片112和IC芯片132可以与MISFET芯片21同样地,不经由导电性接合材147而是直接与第三配线层135接合。
以上对本发明的实施方式进行了说明,但是本发明也可以通过其它方式来实施。
也可以在前述的各实施方式中采用不具备源极取样端子电极层30的MISFET芯片21。该情况下,可以省略因源极取样端子电极层30而形成的结构、例如源极取样外部端子17等。
也可以在前述的各实施方式中采用不具备电感比源极端子电极层29的大的源极取样端子电极层30的MISFET芯片21。
在前述的各实施方式中,基板6也可以取代半导体基板而包含金属基板。金属基板可以包含铜基板、金基板或者铝基板。当然,金属基板也可以由这些金属材料以外的其它金属材料形成。
在前述的各实施方式中,基板6也可以取代半导体基板而包含绝缘基板。绝缘基板可以包含玻璃基板、陶瓷基板、或者树脂基板。当然,绝缘基板也可以由这些绝缘材料以外的其它绝缘材料形成。
在前述的各实施方式中,可以省略主面绝缘层7。在前述的各实施方式中,在基板6为绝缘体的情况下,可以省略主面绝缘层7。
在前述的各实施方式中,对由所谓的纵型器件构成的MISFET芯片21进行了说明。但是,MISFET芯片21也可以是横型器件。即,MISFET芯片21可以构成为,在芯片主体24的第一芯片主面25上形成有:栅极端子电极层28、源极端子电极层29、源极取样端子电极层30和漏极端子电极层31。该情况下,漏极外部端子18在芯片主体24的第一芯片主面25上形成。
在前述的各实施方式中,对由所谓的纵型器件构成的二极管芯片112进行了说明。但是,二极管芯片112也可以是横型器件。即,二极管芯片112可以构成为,在芯片主体113的第一芯片主面114上形成有:负极端子电极层117和正极端子电极层118。该情况下,正极外部端子123在芯片主体113的第一芯片主面114上形成。
在前述的各实施方式中,也可以采用取代MISFET芯片21而包含作为半导体开关元件的一例的IGBT(Insulated Gate Bipolar Transistor:绝缘栅双极型晶体管)的IGBT芯片。该情况下,将MISFET的“源极”替换为IGBT的“发射极”。另外,将MISFET的“漏极”替换为IGBT的“集电极”。
本申请与2017年4月24日向日本国特许厅提出特愿2017-085614对应,并将其引用在此。
虽然对本发明的实施方式进行了具体说明,但是以上仅是为了容易理解本发明的技术内容而使用的具体例,本发明不限于这些具体例,本发明的范围仅由权利要求书限定。
符号说明
1—电子元器件;6—基板(半导体基板);7—主面绝缘层;8—封固绝缘层;9—基板的第一基板主面;10—基板的第二基板主面;12—封固绝缘层的第一封固主面;14—封固绝缘层的封固侧面;15—栅极外部端子;16—源极外部端子;17—源极取样外部端子;18—漏极外部端子;20—配线层;21—MISFET芯片;24—MISFET芯片的芯片主体;25—MISFET芯片的第一芯片主面;26—MISFET芯片的第二芯片主面;28—MISFET芯片的栅极端子电极层;29—MISFET芯片的源极端子电极层;30—MISFET芯片的源极取样端子电极层;31—MISFET芯片的漏极端子电极层;33—栅极焊垫开口;34—源极焊垫开口;35—源极取样焊垫开口;36—漏极焊垫开口;40—栅极外部端子的栅极柱状电极层;41—栅极外部端子的栅极连接部;42—源极外部端子的源极柱状电极层;43—源极外部端子的源极连接部;44—源极取样外部端子的源极取样柱状电极层;45—源极取样外部端子的源极取样连接部;46—漏极外部端子的漏极柱状电极层;47—漏极外部端子的漏极连接部;61—电子元器件;62—栅极外部端子的栅极导电接合层;63—源极外部端子的源极导电接合层;64—源极取样外部端子的源极取样导电接合层;65—漏极外部端子的漏极导电接合层;71—电子元器件;72—栅极外部端子的栅极电极膜;73—栅极外部端子的栅极导电接合层;74—栅极外部端子的覆盖部;75—源极外部端子的源极电极膜;76—源极外部端子的源极导电接合层;77—源极外部端子的覆盖部;78—源极取样外部端子的源极取样电极膜;79—源极取样外部端子的源极取样导电接合层;80—源极取样外部端子的覆盖部;81—漏极外部端子的漏极电极膜;82—漏极外部端子的漏极导电接合层;83—漏极外部端子的覆盖部;91—电子元器件;92—散热结构;93—翼片结构;101—电子元器件;102—散热结构;103—散热部件;111—电子元器件;112—二极管芯片;113—二极管芯片的芯片主体;114—二极管芯片的第一芯片主面;115—二极管芯片的第二芯片主面;117—二极管芯片的负极端子电极层;118—二极管芯片的正极端子电极层;120—负极焊垫开口;121—正极焊垫开口;122—负极外部端子;123—正极外部端子;124—负极外部端子的负极柱状电极层;125—负极外部端子的负极连接部;126—正极外部端子的正极柱状电极层;127—正极外部端子的正极连接部;131—电子元器件;132—IC芯片;133—第一配线层;134—第二配线层;135—第三配线层;136—输入外部端子;141—IC芯片的芯片主体;142—IC芯片的第一芯片主面;143—IC芯片的第二芯片主面;145—IC芯片的输出端子电极层;146—IC芯片的输入端子电极层;148—中间绝缘层;161—第一连接配线层;162—第二连接配线层;163—第三连接配线层;181—电子元器件。

Claims (30)

1.一种半导体装置,其特征在于,包括:
半导体基板,其具有一侧的第一主面和另一侧的第二主面;
主面绝缘层,其形成于所述第一主面侧;
第一半导体芯片,其具有一侧的第一表面和另一侧的第一背面,且包含形成于所述第一表面侧的表面电极,并配置在所述主面绝缘层上;
第二半导体芯片,其具有一侧的第二表面和另一侧的第二背面,且包含形成于所述第二背面侧的背面电极,并配置在所述主面绝缘层上;
连接配线,其与所述第一半导体芯片的所述表面电极以及所述第二半导体芯片的所述背面电极电连接;以及
封固绝缘层,其封固所述第一半导体芯片、所述第二半导体芯片以及所述连接配线,且具有沿着所述第一主面延伸的封固主面。
2.根据权利要求1所述的半导体装置,其特征在于,
所述半导体基板具有连接所述第一主面和所述第二主面的基板侧面,
由所述第一半导体芯片产生的热以及由所述第二半导体芯片产生的热经由所述半导体基板的所述第二主面以及所述基板侧面向外部散放。
3.根据权利要求1所述的半导体装置,其特征在于,
所述半导体基板是硅基板、碳化硅基板、蓝宝石基板或氮化物半导体基板。
4.根据权利要求1所述的半导体装置,其特征在于,
所述半导体基板具有比所述封固绝缘层的厚度大的厚度。
5.根据权利要求4所述的半导体装置,其特征在于,
所述半导体基板具有50μm以上且1000μm以下的厚度,
所述封固绝缘层具有10μm以上且小于所述半导体基板的厚度的厚度。
6.根据权利要求1所述的半导体装置,其特征在于,
所述主面绝缘层包含氧化硅、氮化硅、氮氧化硅、氧化铝、氮化铝和氮氧化铝中的至少一种。
7.根据权利要求1所述的半导体装置,其特征在于,
所述主面绝缘层具有1MV/cm以上的绝缘破坏电场强度。
8.根据权利要求1所述的半导体装置,其特征在于,
所述主表面绝缘层具有比所述第一半导体芯片的厚度和所述第二半导体芯片的厚度双方小的厚度。
9.根据权利要求1所述的半导体装置,其特征在于,
所述主面绝缘层具有0.1μm以上且100μm以下的厚度。
10.根据权利要求1所述的半导体装置,其特征在于,
所述封固绝缘层使所述半导体基板的所述第二主面露出。
11.根据权利要求1所述的半导体装置,其特征在于,
所述半导体基板具有连接所述第一主面和所述第二主面的基板侧面,
所述封固绝缘层使所述基板侧面露出。
12.根据权利要求11所述的半导体装置,其特征在于,
所述封固绝缘层具有封固侧面,该封固侧面形成为与所述基板侧面表面一致。
13.根据权利要求1所述的半导体装置,其特征在于,
所述第一半导体芯片具有芯片主体,该芯片主体包含硅、碳化硅或氮化物半导体。
14.根据权利要求1所述的半导体装置,其特征在于,
所述第一半导体芯片具有600V以上的耐压。
15.根据权利要求1至14中任一项所述的半导体装置,其特征在于,
还包括配置在所述主面绝缘层上的配线,
所述第一半导体芯片配置在所述配线上,
所述第二半导体芯片配置在所述配线上。
16.根据权利要求15所述的半导体装置,其特征在于,
所述第一半导体芯片包含背面电极,该背面电极形成于所述第一背面侧且与所述配线电连接,
所述第二半导体芯片的所述背面电极与所述配线电连接。
17.根据权利要求15所述的半导体装置,其特征在于,
所述配线包括隔开间隔地配置在所述主面绝缘层上的第一配线以及第二配线,
所述第一半导体芯片配置在所述第一配线上,
所述第二半导体芯片配置在所述第二配线上。
18.根据权利要求1至14中任一项所述的半导体装置,其特征在于,
还包括中间绝缘层,该中间绝缘层在所述主面绝缘层上选择性地覆盖所述第一半导体芯片以及所述第二半导体芯片,
所述封固绝缘层封固所述中间绝缘层。
19.根据权利要求18所述的半导体装置,其特征在于,
沿着所述中间绝缘层的外表面形成有所述连接配线。
20.根据权利要求18所述的半导体装置,其特征在于,
所述第一半导体芯片具有第一侧面,
所述第二半导体芯片具有第二侧面,
所述中间绝缘层覆盖所述第一半导体芯片的所述第一表面以及所述第一侧面,并覆盖所述第二半导体芯片的所述第二表面以及所述第二侧面。
21.根据权利要求1至14中任一项所述的半导体装置,其特征在于,
还包括至少一个外部端子,该外部端子以从所述封固主面露出的方式配置在所述封固绝缘层内,并与所述第一半导体芯片电连接。
22.根据权利要求21所述的半导体装置,其特征在于,
所述外部端子包含芯片侧外部端子,该芯片侧外部端子在所述第一半导体芯片上与所述表面电极电连接。
23.根据权利要求21所述的半导体装置,其特征在于,
所述外部端子包含配线侧外部端子,该配线侧外部端子与所述连接配线电连接。
24.根据权利要求23所述的半导体装置,其特征在于,
所述连接配线在所述第一半导体芯片上与所述表面电极连接,
所述配线侧外部端子在所述第一半导体芯片上与所述连接配线连接,且经由所述连接配线与所述表面电极电连接。
25.根据权利要求21所述的半导体装置,其特征在于,
所述第一半导体芯片包含多个所述表面电极,
多个所述外部端子在所述第一半导体芯片上与多个所述表面电极电连接。
26.根据权利要求1至14中任一项所述的半导体装置,其特征在于,
还包括散热结构,该散热结构设置于所述半导体基板的所述第二主面侧。
27.一种半导体模块,其特征在于,包括:
半导体基板,其具有主面;以及
电子电路,其包含隔开间隔地配置在所述主面上的多个芯片,且由多个所述芯片构成。
28.根据权利要求27所述的半导体模块,其特征在于,
多个所述芯片包括:
第一芯片,其包含开关元件;
第二芯片,其与所述第一芯片电连接,且包含二极管;以及
第三芯片,其与所述第一芯片电连接,且控制所述开关元件的驱动。
29.一种电子元器件,其特征在于,包括:
第一芯片,其具有第一电极;
第二芯片,其具有第二电极;
连接配线,其与所述第一电极和所述第二电极双方电连接;以及
外部端子,其与所述连接配线连接,且经由所述连接配线与所述第一芯片的所述第一电极和所述第二芯片的所述第二电极双方电连接。
30.一种SiC半导体装置,其特征在于,包括:
SiC基板,其具有主面;
氮化硅膜,其覆盖所述主面;以及
芯片,其配置在所述氮化硅膜上。
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