CN1156002C - 半导体芯片载体元件制作方法 - Google Patents

半导体芯片载体元件制作方法 Download PDF

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Publication number
CN1156002C
CN1156002C CNB971955042A CN97195504A CN1156002C CN 1156002 C CN1156002 C CN 1156002C CN B971955042 A CNB971955042 A CN B971955042A CN 97195504 A CN97195504 A CN 97195504A CN 1156002 C CN1156002 C CN 1156002C
Authority
CN
China
Prior art keywords
carrier
film
carrier element
chip
strengthening membrane
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB971955042A
Other languages
English (en)
Chinese (zh)
Other versions
CN1222253A (zh
Inventor
M
M·胡伯
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P·斯塔姆卡
°
D·豪德奥
J·菲舍
J·海策尔
H·格拉夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Corp
Original Assignee
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19623826A external-priority patent/DE19623826C2/de
Priority claimed from DE29621837U external-priority patent/DE29621837U1/de
Application filed by Siemens Corp filed Critical Siemens Corp
Publication of CN1222253A publication Critical patent/CN1222253A/zh
Application granted granted Critical
Publication of CN1156002C publication Critical patent/CN1156002C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745Mounting details of integrated circuit chips
    • H10W70/688
    • H10W70/699
    • H10W76/40
    • H10W76/47
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19042Component type being an inductor
    • H10W72/0198
    • H10W72/07352
    • H10W72/075
    • H10W72/321
    • H10W72/50
    • H10W72/884
    • H10W72/952
    • H10W74/00
    • H10W90/734
    • H10W90/754

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Credit Cards Or The Like (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Die Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Turning (AREA)
  • Light Receiving Elements (AREA)
  • Wire Bonding (AREA)
CNB971955042A 1996-06-14 1997-06-10 半导体芯片载体元件制作方法 Expired - Fee Related CN1156002C (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE19623826A DE19623826C2 (de) 1996-06-14 1996-06-14 Verfahren zur Herstellung eines Trägerelements für Halbleiterchips
DE19623826.9 1996-06-14
DE29621837.5 1996-12-16
DE29621837U DE29621837U1 (de) 1996-12-16 1996-12-16 Trägerelement für Halbleiterchips

Publications (2)

Publication Number Publication Date
CN1222253A CN1222253A (zh) 1999-07-07
CN1156002C true CN1156002C (zh) 2004-06-30

Family

ID=26026591

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB971955042A Expired - Fee Related CN1156002C (zh) 1996-06-14 1997-06-10 半导体芯片载体元件制作方法

Country Status (11)

Country Link
EP (1) EP0904602B1 (enExample)
JP (1) JP3498800B2 (enExample)
CN (1) CN1156002C (enExample)
AT (1) ATE212752T1 (enExample)
BR (1) BR9709717A (enExample)
DE (1) DE59706247D1 (enExample)
ES (1) ES2171948T3 (enExample)
IN (1) IN192422B (enExample)
RU (1) RU2191446C2 (enExample)
UA (1) UA42106C2 (enExample)
WO (1) WO1997048133A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2790850B1 (fr) * 1999-03-12 2004-02-27 Gemplus Card Int Procede de fabrication de dispositif electronique portable de type carte a puce
JP3314304B2 (ja) 1999-06-07 2002-08-12 アムコー テクノロジー コリア インコーポレーティド 半導体パッケージ用の回路基板
ATE388488T1 (de) * 2003-03-07 2008-03-15 Nxp Bv Halbleiterbauelement, halbleiterkörper und verfahren zu seiner herstellung
US8664750B2 (en) * 2008-11-17 2014-03-04 Advanpack Solutions Pte. Ltd. Semiconductor substrate, package and device
US9847268B2 (en) 2008-11-21 2017-12-19 Advanpack Solutions Pte. Ltd. Semiconductor package and manufacturing method thereof
FR2974969B1 (fr) * 2011-05-03 2014-03-14 Alstom Transport Sa Dispositif d'interconnexion electrique d'au moins un composant electronique avec une alimentation electrique comprenant des moyens de diminution d'une inductance de boucle entre des premiere et deuxieme bornes
US20140239428A1 (en) * 2013-02-28 2014-08-28 Infineon Technologies Ag Chip arrangement and a method for manufacturing a chip arrangement

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61204788A (ja) * 1985-03-08 1986-09-10 Dainippon Printing Co Ltd 携持用電子装置
FR2645680B1 (fr) * 1989-04-07 1994-04-29 Thomson Microelectronics Sa Sg Encapsulation de modules electroniques et procede de fabrication
DE3924439A1 (de) * 1989-07-24 1991-04-18 Edgar Schneider Traegerelement mit wenigstens einem integrierten schaltkreis, insbesondere zum einbau in chip-karten, sowie verfahren zur herstellung dieser traegerelemente

Also Published As

Publication number Publication date
CN1222253A (zh) 1999-07-07
ES2171948T3 (es) 2002-09-16
ATE212752T1 (de) 2002-02-15
EP0904602B1 (de) 2002-01-30
JP2000512045A (ja) 2000-09-12
DE59706247D1 (de) 2002-03-14
WO1997048133A1 (de) 1997-12-18
EP0904602A1 (de) 1999-03-31
UA42106C2 (uk) 2001-10-15
IN192422B (enExample) 2004-04-24
JP3498800B2 (ja) 2004-02-16
RU2191446C2 (ru) 2002-10-20
BR9709717A (pt) 1999-08-10

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GR01 Patent grant
C19 Lapse of patent right due to non-payment of the annual fee
CF01 Termination of patent right due to non-payment of annual fee