CN1305618A - 制造集成电路卡的方法和按照这种方法制造的卡 - Google Patents

制造集成电路卡的方法和按照这种方法制造的卡 Download PDF

Info

Publication number
CN1305618A
CN1305618A CN99807290A CN99807290A CN1305618A CN 1305618 A CN1305618 A CN 1305618A CN 99807290 A CN99807290 A CN 99807290A CN 99807290 A CN99807290 A CN 99807290A CN 1305618 A CN1305618 A CN 1305618A
Authority
CN
China
Prior art keywords
adhesive tape
integrated circuit
flat
module
panel component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN99807290A
Other languages
English (en)
Inventor
J·C·菲达尔戈
D·埃尔巴兹
M·扎夫拉尼
P·帕特里斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Gemplus SA
Original Assignee
Gemplus SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gemplus SA filed Critical Gemplus SA
Publication of CN1305618A publication Critical patent/CN1305618A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745Mounting details of integrated circuit chips
    • G06K19/07747Mounting details of integrated circuit chips at least one of the integrated circuit chips being mounted as a module
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07743External electrical contacts
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745Mounting details of integrated circuit chips
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135Double encapsulation or coating and encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01087Francium [Fr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15151Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Credit Cards Or The Like (AREA)

Abstract

本发明涉及到一种制造集成电路卡的方法,它包括制作一个模块(12)的步骤,将模块固定到卡体(20)上,它主要包括集成电路(14)和接触区域(16),其特征在于制造模块(12)的步骤中包括以下步骤,在一个导电材料制成的平板元件(26)内形成缝隙(28),用这些缝隙至少是局部界定平板元件(20)上用来构成接触区域(16)的面积,下一个步骤是用一种胶带(30)至少是局部覆盖平板元件(26)的底面(32),然后利用胶带将模块(12)固定在卡体(20)上。

Description

制造集成电路卡的方法和按照这种方法制造的卡
本发明涉及制造印刷电路卡的方法和按照这种方法制造的卡。
本发明具体涉及制造一种集成电路卡的方法,首先制成一个模块,它主要包括集成电路和用来将集成电路连接到工作电路的接触区域,而工作电路被装在用来插入集成电路卡的装置中。
模块的集成电路例如可以是存储电路或微处理器。
将模块插入通常是用塑性材料制成的卡体,模块的接触区域与卡体顶面的高度齐平。
按照制造模块的常规技术,在一个例如金属的导电材料层的一面上淀积一个介电塑性材料制成的支撑膜。对金属层进行蚀刻,漏出每个模块的接触区域和连接轨迹。
将集成电路附着在支撑膜的底面上,并且用各种公知的方法将集成电路的端子用电路连接到各个接触区域。可以用一种密封树脂覆盖支撑膜的底面,将集成电路及其连接装置嵌入树脂中加以严密的保护。
接着按照预定的轮廓切割支撑膜获得单个的模块,并且插入设在卡体内的空腔中。例如可以用胶将模块固定在空腔中。
本发明的目的是提供一种集成电路卡的新颖结构,可以显著降低集成电路卡的制造成本,特别是限制在制造卡时使用的材料的有关成本以及和装配工作有关的成本。
为了这一目的,本发明提出了一种制造集成电路卡的新颖方法,其特征在于制造模块的步骤中包括以下步骤,在一个导电材料制成的平板元件内形成缝隙,用这些缝隙至少是局部界定平板元件上用来构成接触区域的面积,下一个步骤是用一种胶带至少是局部覆盖平板元件的底面,然后利用胶带将模块固定在卡体内部形成的空腔中。
按照本发明的其他特征:
-该方法包括切断模块的步骤,将模块与平板元件分开;
-该方法包括一个步骤,将集成电路固定在与平板元件的底面相同的一侧;
-固定集成电路的步骤接在装配胶带的步骤之后,并且利用胶带将集成电路固定在模块上;
-该方法包括利用连接装置用电路连接到接触区域的底面上的端子,并且胶带具有至少一个连接窗口,通过窗口可以看见接触区域的底面,以便于连接装置通过;
-胶带的连接窗口是在平板元件上装配胶带的步骤之前形成的;
-在装配胶带的步骤之后将集成电路固定在平板元件上;
-用胶带覆盖集成电路;
-在集成电路的区域内从平板元件的底面上去掉胶带,为集成电路构成一个基本上封闭的外壳;
-用保护树脂填充外壳;
-将一层硬化树脂置于胶带和平板元件的底面之间;
-利用第二胶带形成硬化树脂层,它在装配胶带之前是活性的,用来将模块固定到卡体上;
-通过加热激活胶带(30);
-通过辐射激活胶带。
本发明还涉及到按照具有上述任何一个特征的方法制造的一个集成电路卡。
只要参照附图阅读以下的详细说明就可以清楚地认识到本发明的其他特征和优点,在附图中:
图1,2A,4A,5A,6和7都是沿着一个垂直面的截面示意图,用来说明按照本发明的技术制造集成电路卡的一种方法中的不同步骤;
图3A是对应着图2A所示步骤的一个底面图;
图2B,3B和4B表示在按照本发明的方法的图2A,3A和4A中所示步骤的变更实施例;
图5B和5C表示图5A所示步骤的两个变更实施例;
图8到12都是沿着一个垂直面的截面示意图,表示按照本发明的第二种方法中不同顺序的步骤;
图13到19都是沿着一个垂直面的截面图,表示本发明的第三种方法。
图7表示按照本发明的技术制造集成电路卡10的方法中的一个被称为插入阶段的步骤,在这一步骤中将一个主要包括集成电路14和接触区域16的模块12装入设在卡体20内的一个空腔18中,让同时构成模块12的顶面的接触区域16的顶面22与卡体20的顶面24在同一个水平面上基本齐平。
图1到6表示按照本发明的技术制造模块12的不同步骤。
从图1中可见,接触区域16被形成在导电材料制成的平板元件26中。平板元件26最好采用条带的形状,沿着条带可以形成若干串接触区域16,由每一串接触区域16构成一个模块12的接触区域。
例如可以采用诸如铜,青铜,铜-铁合金或铁-镍合金等金属材料制成平板元件26。平板元件的厚度例如是70微米,但是必要时也可以设想采用厚度为35微米的平板元件26。
为了改善电接触性能,可以通过电镀用一种镍-金或银-钯合金覆盖平板元件26。
从图1特别是图3A和3B中可见,例如每一串有六个接触区域16,并且在第一步骤中至少是局部上被缝隙28相互隔开的。从图中还可以看出,成串的接触区域倾向于以条带的形状和平板元件26的外围部分隔开,在隔开的状态下,它们在电路上是彼此独立的。然而,在通过切割将其隔开之前,接触区域仍然通过其外围部分被固定在平板元件的外围部分上,这样能够确保它们在制造模块的过程中保持固定的位置。
可以通过切割,电化学蚀刻或是任何其他公知的方法形成缝隙28。
在接下来的步骤中,从图2A,3A,2B,3B中可见,将一个胶带30贴在平板元件26的底面32上。
胶带最好采用热活化粘接材料制成,也就是仅仅在受热而发生交联的情况下才完全变成胶。采用这种胶带的优点是,这种材料在活化之前比较柔软,并且尽管粘性比较低仍然能够在受压的情况下粘到平板元件26的底面上。这种胶通常被称为“热熔胶”并且以厚度例如是大约70微米的条带形式存在。
当然也可以使用其他类型的胶,可以用催化剂或是通过紫外线辐射来激活。
在胶带30的底面上还应该有一个保护膜(未示出),例如可以在插入模块时去掉这一保护膜。在执行层叠装配时确保胶不会通过缝隙28漏掉,在平板元件26的顶面22上突出。
在图3A和3B中可以看得更清楚,胶带30对应着每一串接触区域26设有至少一个窗口34,通过窗口仍然可以到达接触区域16的底面。
在图2A和3A所示的实施例中,一串接触区域16仅有一个窗口34,而在图2B和3B的实施例中有两个窗口34,都可以到达三个接触区域16的底面32。
当然也可以让为每一串接触区域26预备的胶带30具有和这一串具有的接触区域16一样多的窗口34,每个窗口34可以到达一个接触区域16的底面。
在这两个实施例中,窗口34是矩形的。然而也可以采用其他的形状,这主要取决于接触区域16的形状和布置。
在图4A和4B所示的步骤中,可以在窗口34的中心用一种胶水(未示出)将集成电路14直接固定到区域16的底面32上。
在图4B所示的例子中,利用处在两个窗口34之间的胶带30的一部分36将集成电路14和平板元件26的底面32固定在同一侧上。这样就能将集成电路14大致固定在一串接触区域16的中心,不需要任何额外的固定装置,而是利用了预先放置到平板元件26的底面32上的胶带30的粘接性质。在这种情况下可以通过局部加热胶带30的一部分36而将集成电路14粘在平板元件26的底面32上,确保在制作模块的后两个步骤中能够可靠地固定集成电路。加热可以通过平板元件26来进行,局部同时加热平板元件和一部分36达到理想的交联。
在图2B,3B,4B所示的各种情况下,图5A,5B,5C,6和7表示本发明的方法的后续步骤,用胶带30确保集成电路14的固定。
图5A,5B,5C表示一个步骤的三个不同实施例,在这一步中完成集成电路14和接触区域16之间的连接。
在图5A的实施例中是让电路14的载有接触端子(未示出)的有效面38朝下对齐。利用连接线40将集成电路14的端子各自连接到一个接触区域16,线的两端分别焊接到集成电路14的端子和接触区域16的底面32上。这样,每个连接线40可通过胶带30中的两个窗口之一延伸。
在图5B的实施例中也是让集成电路14的有效面38朝向底面,但是采用一团用注射器淀积的导电树脂42将集成电路14的每个端子连接到对应的接触区域16。采用的树脂可以是包含导电颗粒的一种胶水,或者是本身导电的树脂。集成电路14和集成区域16的这种电路连接方法是通过分配来连接。
按照图3C的第三实施例,集成电路14和接触区域16的电路连接是按照一种“倒装片”式的方法通过一个芯片来完成的,让集成电路14的有效面38朝上,面对着平板元件26的底面32。这一有效面38在电路14的每个端子的水平上具有凸起44,它可以直接接触到相应的导电区域16的底面32。凸起44是用铅-锡合金制成的并且通过熔化这种凸起而实现电连接。
在本发明的实施例中,值得注意的是,胶带30的柔软性使得胶带上处在集成电路14和平板元件26之间的那一部分36在必要时能够稍微变形,从而将每个凸起44连接到对应的接触区域16。
图6表示制作模块12的后续步骤,在这一步中用一层封装树脂至少是局部覆盖住模块12的底面,用来保护集成电路14以及确保集成电路14和接触区域16的电路连接的连接装置40,42,44。在图6的例子中重复了图5A中所示的实施例,采用连接线40作为连接装置。
封装树脂46可以在交联之前的液体状态下淀积。如果需要还可以通过对封装树脂46的底部进行研磨而校准模块12的总高度。
在这一步中全部完成模块12,通过冲压或是激光束切割将模块从平板元件26的外围部分上分离下来。切割的模块12的轮廓是这样的,接触区域16不再有任何导电材料的桥路连接,它们在电路上是独立的,以免造成集成电路端子之间的短路,除非是集成电路14的功能要求存在这种电路。
从图7中可见,模块12的尺寸比一层封装树脂46的尺寸要大,因此,从模块12的整个外围上面可以看到用来将模块12固定在卡体20中的胶带30的底面。
从图7中可见,设在卡体20中的空腔18具有一个浅的外围部分48和一个比较深的中心部分50。外围部分48的深度基本上等于接触区域16和胶带30的总厚度,因此,在插入操作期间,胶带30的底面可以接触到外围部分30的底壁从而与其粘接,接触区域16的顶面22则在卡体20的顶面的同一水平面上自动对齐。
另一方面,空腔18的中心部分50具有足够的深度用来接收被保护树脂46所覆盖的一部分模块12,这一部分的厚度最大。
当模块12被容在空腔18中时,加热胶带30使粘合剂发生交联,从而将模块12稳定地固定在卡支撑体20上。
图8到12表示按照本发明的集成电路卡的第二种制造方法。在第二种方法中,只有在集成电路14被固定到平板元件26的底面32上之后并且在集成电路14和接触区域16之间完成电连接之后才将胶带30放置到底面32上。
这样,在图8所示的并且类似于图1的在平板元件26中形成缝隙28的步骤之后,如图9所示直接执行集成电路14的固定和电连接。图9表示的情况是按照一种被称作“倒装片”的方法来装配集成电路14,当然也可以采用任何其他方法来完成集成电路14的固定和连接,主要的方法如关于本发明第一种方法的图5A和5B所示。
可以利用一种胶水(未示出)的粘接力来固定集成电路14。
如图10所示,放置在平板元件26的底面32上的胶带30没有窗口。它覆盖了包括集成电路14在内的平板元件26的整个底面32,然而,为了避免损伤后者,最好是采用局部可以变形的胶带34,在集成电路14的水平上形成一个凸起52,这一凸起不能压在接触区域16的底面32上,也不能压住集成电路14或是它的连接装置40,42,44。
这样,凸起52和平板元件26就限定了一个大体上封闭的外壳54,它仅仅有一个通过缝隙28向上的开口,这一开口限定了相互的接触区域。连接点40,42,44被保护在外壳54的内部。
从图11可见,然后可以用封装树脂填充外壳54,和本发明的第一方法中一样,它的作用是确保更加有效的保护。例如可以通过将接触区域16相互分开的一个缝隙28进行填充。
然后将由此形成的部件插入卡体20,利用胶带30将其固定在卡体内,例如可通过接触区域16加热胶带使其产生粘性。
按照图13到19所示的本发明的第三种方法是第二种方法的一种变更,为了提高模块12的机械强度,将一层硬化树脂56置于平板元件26和用来将模块12固定在卡体20内的胶带30之间。
如图14所示,例如是在形成将接触区域16相互隔开的挡块28之后但是在固定和连接集成电路14之前将这一层树脂56放置到平板元件26的底面32上。
如图14所示,这一层硬化树脂56还设有窗口34,与关于本发明第一种方法中所描述情况相似,通过它可以达到接触区域16的底面,以便确保集成电路14的电连接。
例如,作为一层保护树脂46,可以采用类似于上文所述的胶带,并且类似于图17到19所示的用来将模块20固定到卡体20上的那一个胶带。然而,这一层树脂的实际作用是用来硬化平板元件26,从图14所示的步骤可以看出,为了确保通过对热活化粘接剂加热而产生交联,这样做是必要的。
可以采用一种胶水(未示出)来固定集成电路14,如图15所示。
图16的步骤表示实现集成电路14与接触区域16的电路连接的一种可能性,在这种情况下采用参照图6所述的关于本发明第一实施例的分配方法。然而,也可以采用其他方法来制作连接装置。
在完成了集成电路的固定和连接之后,图17,18和19中所示的步骤与参照关于本发明第二种方法的图10,11和12所述的方法相同。
按照本发明的三种制作集成电路卡的方法与现有技术相比具有以下的优点,它能够分配支撑膜,而这种支撑膜在现有技术中仅仅起到支撑接触区域16的作用,不能用来固定或硬化模块12。另外,形成缝隙28的步骤大大便利了在缝隙之间界定接触区域16,特别是在采用冲压的情况下。

Claims (17)

1.一种制造集成电路卡的方法,包括制作一个模块(12)的步骤,将模块固定到卡体(20)上,它主要包括集成电路(14)和用电路将集成电路(14)连接到工作电路的接触区域(16),
其特征在于制造模块(12)的步骤中包括以下步骤,在一个导电材料制成的平板元件(26)内形成缝隙(28),用这些缝隙至少是局部界定平板元件(20)上用来构成接触区域(16)的面积,下一个步骤是用一种胶带(30)至少是局部覆盖平板元件(26)的底面(32),然后利用胶带将模块(12)固定在卡体(20)上。
2.按照权利要求1的方法,其特征是包括切割模块(12)的步骤,将模块与平板元件(26)分开。
3.按照前述权利要求之一的方法,其特征是包括一个步骤,将集成电路(14)固定在与平板元件的底面(12)相同的一侧。
4.按照权利要求3的方法,其特征是固定集成电路(14)的步骤接在装配胶带(30)的步骤之后,并且利用胶带(30)将集成电路(14)固定在模块(12)上。
5.按照权利要求4的方法,其特征是包括利用连接装置(40,42,44)用电路连接到接触区域(16)的底面(32)上的端子,并且胶带(30)具有至少一个连接窗口(34),通过窗口可以看见接触区域(16)的底面(32),以便于连接装置(40,42,44)通过。
6.按照权利要求5的方法,其特征是胶带(30)的连接窗口(34)是在平板元件(26)上装配胶带(30)的步骤之前形成的。
7.按照权利要求3的方法,其特征是在装配胶带(30)的步骤之后将集成电路(14)固定在平板元件(26)上。
8.按照权利要求7的方法,其特征是用胶带(30)覆盖集成电路(14)。
9.按照权利要求8的方法,其特征是在集成电路(14)的区域内从平板元件(26)的底面(32)上去掉(52)胶带(30),为集成电路(14)构成一个基本上封闭的外壳(54)。
10.按照权利要求9的方法,其特征是用一种保护树脂(46)填充外壳(54)。
11.按照权利要求7到10之一的方法,其特征是将一层硬化树脂(56)置于胶带(30)和平板元件(26)的底面(32)之间。
12.按照权利要求11的方法,其特征是利用第二胶带形成硬化树脂(56)层,它在装配胶带(30)之前是活性的,用来将模块(12)固定到卡体(20)上。
13.按照前述任何一项权利要求的方法,其特征是通过加热激活胶带(30)。
14.按照权利要求1到12之一的方法,其特征是通过辐射激活胶带(30)。
15.一种集成电路卡,其特征在于它是按照前述任何一项权利要求的方法来制造的。
17.一种集成电路卡,其特征在于它是根据前述任一权利要求的方法制造的。
18.一种模块,具有在一个导电材料制成的平板元件(26)内形成的缝隙(28),用这些缝隙至少是局部界定平板元件(20)上用来构成接触区域(16)的面积,其特征在于用一种胶带(30)至少局部覆盖平板元件(26)的底面(32),然后利用该胶带将模块(12)固定在卡体(20)上。
CN99807290A 1998-06-12 1999-05-31 制造集成电路卡的方法和按照这种方法制造的卡 Pending CN1305618A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9807602A FR2779851B1 (fr) 1998-06-12 1998-06-12 Procede de fabrication d'une carte a circuit integre et carte obtenue
FR98/07602 1998-06-12

Publications (1)

Publication Number Publication Date
CN1305618A true CN1305618A (zh) 2001-07-25

Family

ID=9527470

Family Applications (1)

Application Number Title Priority Date Filing Date
CN99807290A Pending CN1305618A (zh) 1998-06-12 1999-05-31 制造集成电路卡的方法和按照这种方法制造的卡

Country Status (11)

Country Link
EP (1) EP1084482B1 (zh)
JP (1) JP2002518751A (zh)
CN (1) CN1305618A (zh)
AT (1) ATE259980T1 (zh)
AU (1) AU4043699A (zh)
BR (1) BR9910717A (zh)
CA (1) CA2333790A1 (zh)
DE (1) DE69914902D1 (zh)
FR (1) FR2779851B1 (zh)
MX (1) MXPA00012220A (zh)
WO (1) WO1999066445A1 (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102663474A (zh) * 2010-12-06 2012-09-12 欧贝特科技公司 制造微电路装置的方法
CN104471594A (zh) * 2012-04-03 2015-03-25 X卡控股有限公司 包含交联聚合物组合物的信息承载卡及其制造方法
US9594999B2 (en) 2012-04-03 2017-03-14 X-Card Holdings, Llc Information carrying card comprising crosslinked polymer composition, and method of making the same
US10906287B2 (en) 2013-03-15 2021-02-02 X-Card Holdings, Llc Methods of making a core layer for an information carrying card, and resulting products
US11361204B2 (en) 2018-03-07 2022-06-14 X-Card Holdings, Llc Metal card

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2828333B1 (fr) * 2000-06-23 2003-11-07 Gemplus Card Int Procede d'isolation electrique de puces comportant des circuits integres par le depot d'une couche isolante
FR2816107B1 (fr) * 2000-10-30 2003-11-28 Gemplus Card Int Module de circuit integre sur film et son procede de fabrication
FR2817656B1 (fr) * 2000-12-05 2003-09-26 Gemplus Card Int Isolation electrique de microcircuits regroupes avant collage unitaire
EP3422828A1 (de) * 2017-06-29 2019-01-02 voestalpine Stahl GmbH Verfahren und vorrichtung zur herstellung eines elektrischen anschlusskontakts - kontaktinator

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2120861B (en) * 1982-05-27 1985-10-02 Vladimir Iosifovich Livshits Process for manufacturing panels to be used in microelectronic systems
FR2632100B1 (fr) * 1988-05-25 1992-02-21 Schlumberger Ind Sa Procede de realisation d'une carte a memoire electronique et cartes a memoire electronique obtenue par la mise en oeuvre dudit procede
DE4336501A1 (de) * 1993-10-26 1995-04-27 Giesecke & Devrient Gmbh Verfahren zur Herstellung von Ausweiskarten mit elektronischen Modulen
DE4443767A1 (de) * 1994-12-08 1996-06-13 Giesecke & Devrient Gmbh Elektronisches Modul und Datenträger mit elektrischem Modul
FR2740935B1 (fr) * 1995-11-03 1997-12-05 Schlumberger Ind Sa Procede de fabrication d'un ensemble de modules electroniques pour cartes a memoire electronique

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102663474B (zh) * 2010-12-06 2017-08-22 欧贝特科技公司 制造微电路装置的方法
CN102663474A (zh) * 2010-12-06 2012-09-12 欧贝特科技公司 制造微电路装置的方法
US10570281B2 (en) 2012-04-03 2020-02-25 X-Card Holdings, Llc. Information carrying card comprising a cross-linked polymer composition, and method of making the same
US10611907B2 (en) 2012-04-03 2020-04-07 X-Card Holdings, Llc Information carrying card comprising a cross-linked polymer composition, and method of making the same
US9594999B2 (en) 2012-04-03 2017-03-14 X-Card Holdings, Llc Information carrying card comprising crosslinked polymer composition, and method of making the same
CN104471594B (zh) * 2012-04-03 2017-12-01 X卡控股有限公司 包含交联聚合物组合物的信息承载卡及其制造方法
CN104487988B (zh) * 2012-04-03 2017-12-01 X卡控股有限公司 包含交联聚合物组合物的信息承载卡及其制造方法
US10127489B2 (en) 2012-04-03 2018-11-13 X-Card Holdings, Llc Information carrying card comprising crosslinked polymer composition, and method of making the same
US10255539B2 (en) 2012-04-03 2019-04-09 X-Card Holdings, Llc Information carrying card comprising crosslinked polymer composition, and method of making the same
US10392502B2 (en) 2012-04-03 2019-08-27 X-Card Holdings, Llc Information carrying card comprising a cross-linked polymer composition, and method of making the same
CN104471594A (zh) * 2012-04-03 2015-03-25 X卡控股有限公司 包含交联聚合物组合物的信息承载卡及其制造方法
US9688850B2 (en) 2012-04-03 2017-06-27 X-Card Holdings, Llc Information carrying card comprising a cross-linked polymer composition, and method of making the same
US10836894B2 (en) 2012-04-03 2020-11-17 X-Card Holdings, Llc Information carrying card comprising a cross-linked polymer composition, and method of making the same
US11560474B2 (en) 2012-04-03 2023-01-24 X-Card Holdings, Llc Information carrying card comprising a cross-linked polymer composition, and method of making the same
US11170281B2 (en) 2012-04-03 2021-11-09 Idemia America Corp. Information carrying card comprising crosslinked polymer composition, and method of making the same
US11359085B2 (en) 2012-04-03 2022-06-14 X-Card Holdings, Llc Information carrying card comprising a cross-linked polymer composition, and method of making the same
US11359084B2 (en) 2012-04-03 2022-06-14 X-Card Holdings, Llc Information carrying card comprising a cross-linked polymer composition, and method of making the same
US11555108B2 (en) 2012-04-03 2023-01-17 Idemia America Corp. Information carrying card comprising a cross-linked polymer composition, and method of making the same
US11390737B2 (en) 2012-04-03 2022-07-19 X-Card Holdings, Llc Method of making an information carrying card comprising a cross-linked polymer composition
US10906287B2 (en) 2013-03-15 2021-02-02 X-Card Holdings, Llc Methods of making a core layer for an information carrying card, and resulting products
US11884051B2 (en) 2013-03-15 2024-01-30 X-Card Holdings, Llc Methods of making a core layer for an information carrying card, and resulting products
US11361204B2 (en) 2018-03-07 2022-06-14 X-Card Holdings, Llc Metal card

Also Published As

Publication number Publication date
FR2779851A1 (fr) 1999-12-17
EP1084482B1 (fr) 2004-02-18
CA2333790A1 (fr) 1999-12-23
AU4043699A (en) 2000-01-05
BR9910717A (pt) 2001-01-23
EP1084482A1 (fr) 2001-03-21
FR2779851B1 (fr) 2002-11-29
WO1999066445A8 (fr) 2000-02-10
WO1999066445A1 (fr) 1999-12-23
ATE259980T1 (de) 2004-03-15
JP2002518751A (ja) 2002-06-25
MXPA00012220A (es) 2002-06-04
DE69914902D1 (de) 2004-03-25

Similar Documents

Publication Publication Date Title
CN1265451C (zh) 半导体装置及其制造方法
CN1047470C (zh) 半导体器件
CN1143373C (zh) 半导体装置及其制造方法、电路基板和电子装置
EP0810649B1 (en) Method for coupling substrates and structure
CN1151554C (zh) 半导体器件、其制造方法以及组合型半导体器件
CN1155913C (zh) 生产芯片卡的方法及芯片卡
KR0171438B1 (ko) 반도체 장치를 회로 기판상에 장착하는 방법 및 반도체 장치가 장착된 회로 기판
CN1192041A (zh) 半导体器件的制造方法
JPH0930171A (ja) 電子カードの製造及び組立て方法及び該方法により得られた電子カード
CN1156970C (zh) 电子元件
CN1638120A (zh) 半导体组装体及其制造方法
CN1147930C (zh) 半导体封装结构及其制造方法
CN1575096A (zh) 电子电路装置及其制造方法
CN1305618A (zh) 制造集成电路卡的方法和按照这种方法制造的卡
KR100846032B1 (ko) 듀얼 인터페이스를 갖는 카드의 제조 방법 및 이에 의해획득한 마이크로회로 카드
CN1341963A (zh) 半导体装置及其制造方法
US6940156B2 (en) Electronic module with a semiconductor chip which has flexible chip contacts, and method for producing the electronic module
US6331452B1 (en) Method of fabricating integrated circuit package with opening allowing access to die
CN1387240A (zh) 叠层式半导体器件的制造方法
CN1649140A (zh) 混合集成电路装置及其制造方法
JP2003273160A (ja) 半導体実装モジュール
CN100336209C (zh) 混合集成电路装置的制造方法
JP2581592B2 (ja) フレキシブルピンキャリア及びそれを使用した半導体装置
CN218388141U (zh) 具有经表面组装的电子构件的印刷电路板
CN1481004A (zh) 将集成电路连接到基片上的方法及相应电路配置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication