CN1649140A - 混合集成电路装置及其制造方法 - Google Patents
混合集成电路装置及其制造方法 Download PDFInfo
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- CN1649140A CN1649140A CNA2004100819423A CN200410081942A CN1649140A CN 1649140 A CN1649140 A CN 1649140A CN A2004100819423 A CNA2004100819423 A CN A2004100819423A CN 200410081942 A CN200410081942 A CN 200410081942A CN 1649140 A CN1649140 A CN 1649140A
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- circuitry substrate
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- integrated circuit
- lead
- bonding agent
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- Engineering & Computer Science (AREA)
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
一种混合集成电路装置及其制造方法,使沿衬底的一侧边部将在表面上固定引线的电路衬底的背面露出外部,进行密封。本发明包括:形成电路的工序,该电路由在电路衬底(16)表面上形成的导电图案(18)及与导电图案(18)电连接的电路元件(14)构成;在由沿电路衬底(16)的一侧边配置的导电图案(18)构成的焊盘(18A)上固定引线(11)的工序;将电路衬底(16)收纳入模制模具(30)的模穴(31)内,通过由模制模具(30)夹持引线(11),将引线(11)固定的工序;通过在模穴(31)的内部注入密封树脂(12),使电路衬底(16)的背面接触模具(30)的下面,进行密封的工序。
Description
技术领域
本发明涉及混合集成电路装置及其制造方法,特别是涉及使电路衬底的背面从密封树脂露出的混合集成电路装置及其制造方法。
背景技术
参照图10说明现有混合集成电路装置的结构(例如参照专利文献1)。图10(A)是混合集成电路装置100的立体图,图10(B)是图10(A)X-X’线的剖面图。
参照图10(A)及图10(B),现有的混合集成电路装置100具有如下结构。其包括:矩形衬底106;在设于衬底106表面上的绝缘层107上形成的导电图案108;被固定在导电图案108上的电路元件104;电连接电路元件104和导电图案108的金属线105;与导电图案108电连接的引线101。这样,混合集成电路装置100的整体被密封树脂102密封。由密封树脂102密封的方法有使用热可塑树脂的注入模和使用热硬性树脂的传递模。
参照图11说明使用传递模进行树脂密封的工序。图11是使用模型110进行树脂密封的剖面图。
在衬底106的表面上形成由电路元件104等构成的电路。该衬底106由上模110A及下模110B固定。通过将上模110A与下模110B咬合,形成作为密封树脂空间的模穴。通过从浇口111注入密封树脂将衬底106密封。另外,引线框架101A被上模110A及下模110B夹持。由此,衬底106的平面的位置被固定。另外,设置从上模110A向下方延伸的压销P。通过将该压销P按压衬底106的表面,在密封的工序中,衬底106厚度方向被定位。
在由以上的工序密封后,经由使热硬性树脂的特性稳定化的后处理工序等,完成混合集成电路装置。
专利文献1:特开平6-177295号公报(第四页、第一图)
但是,上述这样的混合集成电路装置的制造方法具有如下问题。
由于必须在衬底106上设置用于与压销P的区域连接,故该区域形成死区(デ一ドスペ一ス),阻碍了衬底的小型化。另外,由于不能在与压销P接触的区域载置晶体管等电路元件,故还有在进行导电图案108的设计时的自由度降低的问题。另外,密封树脂在压销周边的流动性降低,而产生了空隙。
在上述说明中说明了密封包括衬底背面的整体的方法,但由于散热性的提高,也有衬底106的背面从密封树脂102露出的情况。此时,若使用压销P,由于衬底106的厚度具有某些程度的公差,故压销P的前端部与衬底106的表面正确地接触是困难的。因此,由于压销P过度地按压电路装置106,电路衬底106的表面产生了损伤。当在电路衬底106的表面形成的绝缘性树脂损伤时,电路衬底106的耐压性降低。
发明内容
本发明是鉴于上述问题点而开发的。因此,本发明的主要目的在于,提高一种混合集成电路装置及其制造方法,使沿衬底一侧边部在表面上固定了引线的电路衬底的背面露出到外部,而进行密封。
本发明的混合集成电路装置的特征在于包括:电路衬底;在上述电路衬底表面上形成的导电图案;电连接在上述导电图案上的电路元件;固定在由上述导电图案构成的焊盘上的引线;至少覆盖上述电路衬底表面而形成的密封树脂,其中,上述焊盘的背面从上述电路衬底的表面离开。
在本发明的混合集成电路装置中,上述焊盘形成在覆盖上述电路衬底的绝缘层的表面,且从上述绝缘层离开。
另外,在本发明的混合集成电路装置中,所述引线通过由上述密封树脂部分地覆盖而被机械地支承。
本发明的混合集成电路装置的制造方法包括:构成电路的工序,该电路由在电路衬底表面上形成的导电图案及与上述导电图案电连接的电路元件构成;在由上述导电图案构成的焊盘上固定引线的工序;将上述电路衬底收纳入模制模具的模穴内,通过由上述模制模具夹持上述引线,将上述引线固定的工序;通过在上述模穴内部注入密封树脂,使上述电路衬底的背面接触上述模具的下面,进行密封的工序。
另外,本发明的特征在于,在固定上述引线的工序中,通过由上述模具夹持上述引线,上述电路衬底相对于上述模具的底面被倾斜地定位,并通过上述密封树脂的重量,使上述电路衬底的底面接触上述模具的底面。
本发明的特征在于,上述焊盘的背面介由第一粘接剂与上述电路衬底粘接,并介由比上述第一粘接剂的粘接力更大的第二粘接剂将上述引线和上述焊盘的表面粘接,通过上述密封树脂的重量使上述电路衬底的底面接触上述模具的底面,在上述焊盘表面和上述引线粘接的状态下,上述焊盘的背面从上述电路衬底剥离。上述第一粘接剂可采用由树脂构成的树脂层。上述第二粘接剂可采用焊锡等焊剂。
本发明的特征在于,上述第一粘接剂是绝缘性粘接剂,上述第二粘接剂是导电性粘接剂。
本发明的特征在于,上述第一粘接剂是含有树脂的粘接剂,上述第二粘接剂是由金属构成的粘接剂。
本发明的特征在于,将上述焊盘的背面粘接在上述电路衬底上的第一粘接剂由以比进行上述密封时的上述模具的温度低的温度软化的材料构成,由于上述电路衬底被配置在上述模具的内部,上述第一粘接剂被软化,粘接力减小,通过上述密封树脂的重量使上述电路衬底的底面接触上述模具的底面,在上述焊盘的表面和上述引线粘接的状态下,上述焊盘的背面从上述电路衬底剥离。
本发明的特征在于,上述第一粘接剂是含有树脂的粘接剂。
另外,本发明的特征在于,在剥离后的上述焊盘和上述电路衬底之间填充有上述密封树脂。
在本发明中,可达到以下所示的效果。
通过使连接引线的焊盘从电路衬底的背面离开,在引线和电路衬底之间未作用应力的状态下,两者被密封树脂覆盖。因此,提高了引线和焊盘的粘接可靠性。
在树脂密封的工序中,使用被注入模穴的密封树脂本身使电路衬底接触模具下面。因此,可省去现有例所示的压销P这样多余的结构,进行密封的工序。另外,由于不必在电路衬底表面设置压销P的接触区域,故可在电路衬底表面的实际上整个区域上形成导电图案。另外,由于配置晶体管等电路元件的位置也没有限制,故可提高设计导电图案或配置电路元件的位置等时的自由度。
另外,即使在电路衬底的厚度、连接电路衬底与引线的粘接剂的厚度、引线的厚度等有偏差的情况下,也可以缓和作用于引线的应力。这是因为在固定引线的焊盘和电路衬底表面之间形成有间隙,即使上述偏差产生了,也可以被该间隙吸收。
附图说明
图1(A)是本发明混合集成电路装置的立体图;图1(B)是其剖面图;
图2(A)是本发明混合集成电路装置制造方法的平面图;图2(B)是其剖面图;
图3是本发明混合集成电路装置制造方法的平面图;
图4(A)是本发明混合集成电路装置制造方法的平面图;图4(B)是其剖面图;
图5(A)是本发明混合集成电路装置制造方法的剖面图;图5(B)是其剖面图;
图6(A)是本发明混合集成电路装置制造方法的剖面图;图6(B)是其剖面图;
图7是本发明混合集成电路装置制造方法的剖面图;
图8是本发明混合集成电路装置制造方法的平面图;
图9是本发明混合集成电路装置制造方法的平面图;
图10(A)是现有的混合集成电路装置的立体图;图10(B)是其剖面图;
图11是现有的混合集成电路装置制造方法的剖面图。
具体实施方式
参照图1说明本发明混合集成电路装置10的结构。图1(A)是混合集成电路装置10的立体图,图1(B)是图1(A)X-X’线的剖面图。
本发明的混合集成电路装置10具有:在表面上形成由导电图案18和电路元件14构成的电路的电路衬底16;密封电路,并至少覆盖电路衬底16表面的密封树脂12。以下说明这样的各构成要素。
电路衬底16是由铝或铜等金属构成的衬底。作为一例的电路衬底16在采用由铝构成的衬底时,使电路衬底16和在其表面上形成的导电图案18绝缘的方法有两种。一个方法是将铝衬底表明进行氧化铝处理,另一个方法是在铝衬底的表面上形成绝缘层17,在绝缘层17的表面上形成导电图案18。在此,为了使由被载置于电路衬底16表面上的电路元件14产生的热适当地排出外部,而使电路衬底16的背面从密封树脂12露出外部。
电路元件14被固定在导电图案18上,由电路元件14和导电图案18构成规定的电路。电路元件14采用晶体管或二极管等有源元件、电容或电阻等无源元件。另外,也可以介由由金属构成的散热片将功率系半导体元件等发热量大的元件固定在电路衬底16上。在此,面朝上安装的有源元件介由金属线15与导电图案18电连接。
导电图案18由铜等金属构成,且和电路衬底16绝缘。另外,在导出引线11的边上形成由导电图案18构成的焊盘18A。在此,在电路衬底16的一边附近设置多个整列的焊盘18A。另外,导电图案18以绝缘层17作为粘接剂粘接在电路衬底16的表面上。另外,图中表示了单层的导电图案18,但也可以是层积成两层以上的多层导电图案。
引线11被固定在设于电路衬底16周边部的焊盘18A上,具有和例如外部进行输入、输出的作用。在此,一边上设有多条引线11。引线11和焊盘18A的粘接介由焊锡(焊剂)等导电性粘接剂进行。
密封树脂12利用使用热硬性树脂的传递模或使用热可塑树脂的注入模形成。在此,形成密封树脂12,以密封电路衬底16及形成于其表面上的电路,且电路衬底16的背面从密封树脂12露出。
焊盘18A的背面可以从电路衬底16的表面突出。在突出的焊盘18A和电路衬底16之间填充有密封树脂12。另外,焊盘18A和其它部分的导电图案18被电连接。而且,引线11被密封树脂机械地支承。
参照图2及其后面的附图,说明混合集成电路装置10的制造方法。混合集成电路装置10的制造方法包括:构成电路的工序,该电路由在电路衬底16表面上形成的导电图案18及与导电图案18电连接的电路元件14构成;在由沿电路衬底16一侧边配置的导电图案18构成的焊盘18A上固定引线11的工序;将电路衬底16收纳入模制模具30的模穴31内,通过由模制模具30夹持引线11而将引线11固定的工序;通过在模穴31内部注入密封树脂12,使电路衬底16的背面接触模具30的下面而进行密封的工序。以下说明该制造方法。
首先,参照图2(A)及图2(B),在电路衬底16的表面形成由导电图案18及电路元件14构成的电路。作为导电图案18的制造方法,首先,介由绝缘层17将导电箔粘接在电路衬底18的表面上。然后,通过蚀刻该导电箔得到具有所希望图案形状的导电图案18。另外,在导电图案18所希望的位置配置电路元件14,通过使用金属细线15电连接而构成所希望的电路。电路元件14可全面采用半导体元件等有源元件、或者电阻、电容等无源元件。另外,伴随功率系半导体元件这样大的发热的元件也可以介由散热片等固定在安装衬底16上。
在此,绝缘层17具有绝缘导电图案18和电路衬底16的作用,同时,还具有粘接两者的作用。绝缘层17的材料可采用例如在环氧树脂中中混入了氧化铝等无机填料的材料。这样,通过采用填充了无机填料的树脂作为绝缘层17的材料,可减小由电路元件14产生的热在电路衬底16上导电时的热电阻。
其次,参照图3及图4说明将引线11固定在电路衬底16上的工序。首先,参照图3说明引线框架20的结构。在本发明中,引线11在引线框架20的状态下被供给。即本实施例的引线框架20固定形成多个由引线11及电路衬底16的搭载区域构成的单元21。另外,引线框架20具有薄长方形外型,各单元21被以一定的间隔分开配置多个。在各单元21之间设有狭缝25,其吸收由伴随加热模制工序等的工序产生的热应力。另外,在引线框架20纵向的两周边部设置导孔22,用于各工序中的定位。另外,在各单元21内设置的多条引线11通过第一连接部23及第二连接部24连接,其形状及位置被固定。
在各单元21内设有支承部26及突出部25。突出部25是从各单元21的两端向内侧延伸的部位,该平面的形状及位置和图1所示的固定部13相同。支承部26由以后的树脂密封工序埋入密封树脂内,其具有使电路装置和引线框架20一体地连接至最终工序的作用。支承部26形成其内部具有孔部的形状,通过向该孔部内填充密封树脂来提高支承部26和密封树脂的结合力。另外,支承部26在各单元21的相对的边上各形成两个,在以后的工序中强化电路装置和引线框架20的结合。由于通过如此在支承部26上设置孔部来减弱支承部26和引线框架20的机械结合,故可容易地进行以后工序中的电路装置和引线框架20的分割。另外,支承部26形成在除配置电路衬底16的予定区域A1以外的区域的单元21内。这样,通过配置支承部26将支承部26埋入密封树脂内,可防止电路装置的耐湿性降低。
其次,参照图4,在引线框架20的各单元21内固定电路衬底16。图4(A)是表示本工序的平面图,图4(B)是从剖面方向D1看到的剖面图。电路衬底16与引线框架20的固定连接介由焊锡等焊剂固定连接各单元21的引线11的先端部和电路衬底16的焊盘18A来进行。参照图4(B),在焊盘18A上固定的部分引线11是为防止与电路衬底16的短路而弯曲。
其次,参照图5~图8,使电路衬底16的背面露出,利用密封树脂12进行密封。首先,参照图5,将电路衬底16收纳入进行密封的模具30内部。图5(A)及图5(B)是本工序的剖面图,在此说明密封一个电路衬底16的方法,但实际上,也可以在由多个电路衬底16与引线框架20连接的状态下进行本工序。
首先,参照图5(A)说明进行密封的模具30和电路衬底16的关联结构。由本工序进行密封的模具30由上模30A及下模30B构成,通过将两者上下咬合形成作为进行密封空间的模穴31。另外,在上模30A及下模30B内设置接触部32A及接触部32B,通过由这些接触部32夹持引线11,将电路衬底16的平面位置固定。图中表示在将电路衬底16载置到下模30B上后,使上模30A接触下模30B的情况。在此,模穴31的下面与下模接触部32A上端的上下方向距离为D1。并且,电路衬底16的下面与引线11下面的上下方向距离为D2,这样,在本实施例中,D1设置得比D2短。当通过该结构将电路衬底16载置在下模30B的下面时,在引线11与接触部32B之间形成对应D1与D2的差的间隙。
参照图5(B),引线11接触到接触部32B前,将上模30A向按压方向D按压。由此,在模穴31内部,电路衬底16相对于模穴31的下面被倾斜地固定。具体地说,以固定引线11的边为支点,倾斜地固定电路衬底16的位置。其原因在于,由于引线11介由倾斜部延伸设置,引线11的先端部被接触部32A向下方向按压,向下和向前后(图中的左右方向)的力作用到电路衬底16上。在此,模穴31的下面与电路衬底16所构成的角度为α。
其次,参照图6,向模穴31内注入密封树脂12。图6(A)是向模穴31内注入密封树脂12时的剖面图,图6(B)是进行树脂注入后时的剖面图。
参照图6(A),通过由浇口G将密封树脂12注入模穴31内进行模制。另外,在本工序中,通过使密封树脂12位于电路衬底16的上部,使用密封树脂12的重量使电路衬底16的背面接触模穴31的下面。具体地说,随着树脂密封工序的进行,位于电路衬底16上部的密封树脂12的量渐渐增大,模穴31的下面与电路衬底16所构成的角度α变小。并且,电路衬底16的背面接触模穴31的下面。另外,注入模穴31时的注入压力也具有将电路衬底16向下按压的作用。
浇口G被设置在比电路衬底16的上面更位于上方的位置的模具的侧面。在该图中,相对固定引线11的边设置浇口G,但也可以在位于纸面进深方向的模具侧边设置浇口G。
参照图6(B),通过直至将密封树脂12填充入模穴31内进行密封,结束模制的工序。在进行密封的工序时,由于电路衬底16的背面接触模穴的下面,故电路衬底16的背面构成从密封树脂12露出的结构。另外,本工序是通过将模具30整体加热至180度左右进行的。另外,有时在直至使电路衬底16的背面接触模穴下面,焊盘18A的背面从电路衬底16的背面剥离。
其次,参照图7的剖面图说明完成模制工序后的混合集成电路装置10的结构。参照该图,焊盘18A的背面形成部分地从电路衬底16剥离的结构。并且,焊盘18A的表面介由焊剂19和引线11固定。通过剥离焊盘18A的背面,在上述模制工序吸收电路衬底16的角度α变化而产生的应力。在本实施例中,通过将焊盘18A与电路衬底16的粘接强度降得比焊盘18A与引线11的粘接强度低来实现上述结构。另外,在剥离后的焊盘18A与电路衬底16之间填充有密封树脂12。
具体地说,焊盘18A的背面介由绝缘层17与电路衬底16的表面粘接。并且,焊盘18A的表面介由焊剂19与引线11粘接。采用焊剂19的粘接强度比采用绝缘层17的粘接强度大。因此,当在模制工序中施加剥离焊盘18A的外力时,焊盘18A的背面被优先剥离。另外,在模制工序中,模穴31的内部被加热到180度左右。在该状况下,进行焊盘18A与电路衬底16的粘接的绝缘层17被软化,粘接力降低。相反,进行焊盘18A与引线11的粘接的焊剂19在该程度的温度下未被软化。因此,可容易得到如6所示的结构。
通过从电路衬底16将焊盘18A的背面剥离,焊盘18A的背面从电路衬底16剥离。但是,由于与电路衬底16接触的附近的引线11被埋入密封整体的密封树脂12内,故引线11的机械保持通过密封树脂12进行。并且,引线11的电连接介由焊盘18A进行。
利用上述工序在与焊盘18A连接的部分的导电图案18上产生有一些延伸。但是,在使用铜作为导电图案18的材料时,由于铜是延伸性优良的材料,故该延伸不会造成产生断线等。在图7中,从绝缘层17将焊盘18A剥离的背面,但在绝缘层17粘接在焊盘18A的背面的状态下也可以将焊盘18A从电路衬底16剥离。
参照图8说明完成模制工序后的引线框架20的平面状态。该图是放大图3所示的引线框架20之一部分的平面图。
形成密封树脂,使其密封固定于各单元21上的电路衬底16。并且,在对应突出部25的区域的位置未形成密封树脂12。因此,该位置形成图1所示的固定部13。另外,支承部26在模制工序中埋入密封树脂12内。在该图中,虚线表示埋入密封树脂内的部分的支承部26。
其次,参照图9,自各单元2与引线11分离。在此,利用冲孔等除去方法除去虚线所示的第一连接部23,将各引线11机械/电分离。另外,通过切割连接第二连接部24的部分的引线11,使引线11从引线框架20分离。通过机械地分离引线框架20与引线11,树脂密封后的电路衬底16与引线框架20介由支承部26连接。因此,在本实施例中,由于在进行引线11的分离后也可以一体地支承各单元21的混合集成电路装置与引线框架20,故具有工序间的运送等容易进行优点。
完成上述工序后,经由如下工序完成例如图1所示的混合集成电路装置10,即将引线11弯曲成所希望的形状,进行成形的工序;从引线框架20分离各混合集成电路装置的工序;测试各混合集成电路装置电气特性的工序。
Claims (11)
1、一种混合集成电路装置,其特征在于,包括:电路衬底;在所述电路衬底的表面上形成的导电图案;电连接在所述导电图案上的电路元件;固定在由所述导电图案构成的焊盘上的引线;至少覆盖所述电路衬底表面而形成的密封树脂,其中,所述焊盘的背面从上述电路衬底的表面离开。
2、如权利要求1所述的混合集成电路装置,其特征在于,所述焊盘形成在覆盖所述电路衬底的绝缘层的表面,且从所述绝缘层离开。
3、如权利要求1所述的混合集成电路装置,其特征在于,所述引线通过由所述密封树脂部分覆盖而被机械地支承。
4、一种混合集成电路装置的制造方法,其特征在于,包括:构成电路的工序,该电路由在电路衬底表面上形成的导电图案及与所述导电图案电连接的电路元件构成;在由所述导电图案构成的焊盘上固定引线的工序;将所述电路衬底收纳入模制模具的模穴内,通过由所述模制模具夹持所述引线,将所述引线固定的工序;通过在所述模穴内部注入密封树脂,使所述电路衬底的背面接触所述模具的下面,进行密封的工序。
5、如权利要求4所述的混合集成电路装置的制造方法,其特征在于,在固定所述引线的工序中,通过由所述模具夹持所述引线,所述电路衬底相对于所述模具的底面被倾斜地定位,并通过所述密封树脂的重量及压力,使所述电路衬底的底面接触所述模具的底面。
6、如权利要求5所述的混合集成电路装置的制造方法,其特征在于,所述焊盘的背面介由第一粘接剂与所述电路衬底粘接,并介由比所述第一粘接剂的粘接力大的第二粘接剂将所述引线与所述焊盘的表面粘接,通过所述密封树脂的重量及压力使所述电路衬底的底面接触所述模具的底面,在所述焊盘表面与所述引线粘接的状态下,所述焊盘的背面从所述电路衬底剥离。
7、如权利要求6所述的混合集成电路装置的制造方法,其特征在于,所述第一粘接剂是绝缘性粘接剂,所述第二粘接剂是导电性粘接剂。
8、如权利要求6所述的混合集成电路装置的制造方法,其特征在于,所述第一粘接剂是含有树脂的粘接剂,所述第二粘接剂是由金属构成的粘接剂。
9、如权利要求5所述的混合集成电路装置的制造方法,其特征在于,将所述焊盘的背面粘接在所述电路衬底上的第一粘接剂由以比进行所述密封时的所述模具的温度低的温度软化的材料构成,由于所述电路衬底被配置在所述模具的内部,所述第一粘接剂被软化,粘接力减小,通过所述密封树脂的重量及压力使所述电路衬底的底面接触所述模具的底面,在所述焊盘的表面与所述引线粘接的状态下,所述焊盘的背面从所述电路衬底剥离。
10、如权利要求9所述的混合集成电路装置的制造方法,其特征在于,所述第一粘接剂是含有树脂的粘接剂。
11、如权利要求6所述的混合集成电路装置的制造方法,其特征在于,在剥离后的所述焊盘与所述电路衬底之间填充所述密封树脂。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102090156A (zh) * | 2008-07-17 | 2011-06-08 | 罗伯特·博世有限公司 | 电子组件以及其制造方法 |
CN103715106A (zh) * | 2012-09-29 | 2014-04-09 | 广东美的制冷设备有限公司 | 一种智能功率模块的制造方法及智能功率模块 |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101542723A (zh) * | 2006-10-06 | 2009-09-23 | 美高森美公司 | 高温、高压SiC无空隙电子封装 |
DE102007009671A1 (de) * | 2007-02-28 | 2008-09-04 | Hirschmann Automotive Gmbh | Verfahren zum Ummanteln von mehreren Stanzgittern |
JP5749468B2 (ja) * | 2010-09-24 | 2015-07-15 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 回路装置およびその製造方法 |
US9219029B2 (en) * | 2011-12-15 | 2015-12-22 | Stats Chippac Ltd. | Integrated circuit packaging system with terminals and method of manufacture thereof |
US8623711B2 (en) | 2011-12-15 | 2014-01-07 | Stats Chippac Ltd. | Integrated circuit packaging system with package-on-package and method of manufacture thereof |
US8629567B2 (en) | 2011-12-15 | 2014-01-14 | Stats Chippac Ltd. | Integrated circuit packaging system with contacts and method of manufacture thereof |
JP6210818B2 (ja) * | 2013-09-30 | 2017-10-11 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
WO2015178296A1 (ja) * | 2014-05-20 | 2015-11-26 | 三菱電機株式会社 | 電力用半導体装置 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4079511A (en) * | 1976-07-30 | 1978-03-21 | Amp Incorporated | Method for packaging hermetically sealed integrated circuit chips on lead frames |
US4300153A (en) * | 1977-09-22 | 1981-11-10 | Sharp Kabushiki Kaisha | Flat shaped semiconductor encapsulation |
US4330790A (en) * | 1980-03-24 | 1982-05-18 | National Semiconductor Corporation | Tape operated semiconductor device packaging |
DE3019207A1 (de) * | 1980-05-20 | 1981-11-26 | GAO Gesellschaft für Automation und Organisation mbH, 8000 München | Traegerelement fuer einen ic-chip |
DE3248385A1 (de) * | 1982-12-28 | 1984-06-28 | GAO Gesellschaft für Automation und Organisation mbH, 8000 München | Ausweiskarte mit integriertem schaltkreis |
US4701999A (en) * | 1985-12-17 | 1987-10-27 | Pnc, Inc. | Method of making sealed housings containing delicate structures |
DE3639630A1 (de) * | 1986-11-20 | 1988-06-01 | Gao Ges Automation Org | Datentraeger mit integriertem schaltkreis und verfahren zur herstellung desselben |
US4855868A (en) * | 1987-01-20 | 1989-08-08 | Harding Ade Yemi S K | Preformed packaging arrangement for energy dissipating devices |
JPH047866A (ja) | 1990-04-25 | 1992-01-13 | Nec Corp | 混成集積回路装置 |
JP2698278B2 (ja) | 1992-01-31 | 1998-01-19 | 三洋電機株式会社 | 混成集積回路装置 |
US5945130A (en) * | 1994-11-15 | 1999-08-31 | Vlt Corporation | Apparatus for circuit encapsulation |
JPH09327990A (ja) * | 1996-06-11 | 1997-12-22 | Toshiba Corp | カード型記憶装置 |
US6214640B1 (en) * | 1999-02-10 | 2001-04-10 | Tessera, Inc. | Method of manufacturing a plurality of semiconductor packages |
JP4614584B2 (ja) | 2001-06-28 | 2011-01-19 | 三洋電機株式会社 | 混成集積回路装置およびその製造方法 |
-
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2004
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CN102090156A (zh) * | 2008-07-17 | 2011-06-08 | 罗伯特·博世有限公司 | 电子组件以及其制造方法 |
CN102090156B (zh) * | 2008-07-17 | 2014-07-16 | 罗伯特·博世有限公司 | 电子组件以及其制造方法 |
CN103715106A (zh) * | 2012-09-29 | 2014-04-09 | 广东美的制冷设备有限公司 | 一种智能功率模块的制造方法及智能功率模块 |
CN103715106B (zh) * | 2012-09-29 | 2016-08-17 | 广东美的制冷设备有限公司 | 一种智能功率模块的制造方法及智能功率模块 |
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