CN102090156A - 电子组件以及其制造方法 - Google Patents
电子组件以及其制造方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title description 6
- 239000000758 substrate Substances 0.000 claims abstract description 91
- 239000004020 conductor Substances 0.000 claims abstract description 62
- 238000000465 moulding Methods 0.000 claims abstract description 38
- 239000000463 material Substances 0.000 claims description 35
- 239000011469 building brick Substances 0.000 claims description 28
- 238000005245 sintering Methods 0.000 claims description 20
- 239000011159 matrix material Substances 0.000 claims description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 8
- 238000009766 low-temperature sintering Methods 0.000 claims description 7
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 229910052763 palladium Inorganic materials 0.000 claims description 4
- 238000007789 sealing Methods 0.000 claims description 2
- 239000002585 base Substances 0.000 claims 1
- 150000001875 compounds Chemical class 0.000 abstract description 3
- 230000005855 radiation Effects 0.000 description 9
- 238000003466 welding Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000004080 punching Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 235000008331 Pinus X rigitaeda Nutrition 0.000 description 1
- 235000011613 Pinus brutia Nutrition 0.000 description 1
- 241000018646 Pinus brutia Species 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000011900 installation process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
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Abstract
本发明涉及一种电子组件,所述电子组件带有至少一个用于支撑组件的、被机械保护件(13)所包围的导体衬底(2)。规定所述导体衬底(2)被作为机械保护件(13)的模制材料(12)包围并且借助于至少一个固有刚性的、弹性的电连接导体(7)被接触,其中所述连接导体(7)还至少部分地嵌入所述模制材料(12)中。此外本发明涉及一种目标在于此的制造方法。
Description
技术领域
本发明涉及一种电子组件,所述电子组件带有至少一个用于支撑组件的、被机械保护件包围的导体衬底。此外本发明还涉及一种目标在于所述电子组件的制造方法。
背景技术
为了保护电子组件,该电子组件被封装在壳体中。特别是在混合技术中,通过昂贵的安装过程将装配的和压焊的衬底衬板安装在预先制造的壳体中,为此通常的步骤顺序是将衬底粘贴在底板上、安装壳体、压焊衬底、铺设衬底、装配盖板以及壳体完整性安装。对此,一方面,相对高的制造费用和高的加工深度是不利的,其分别与极高的成本相联系。另一方面,由于给定的壳体形式而可能导致的尺寸很大,这是不利的。
发明内容
本发明的任务是,提供一种电子组件,该电子组件在小空间上提供在给予保护的壳体中尽可能大的线路密度,并且能简单地且低成本地制造。特别是在此还会实现所述电路元件良好的散热。
对此提出了一种电子组件,所述电子组件带有至少一个用于支撑组件的、被机械保护件包围的导体衬底。规定,所述导体衬底被作为机械保护件的模制材料包围并且借助于至少一个固有刚性的、弹性的电连接导体被接触,其中所述连接导体还至少部分地嵌入模制材料中。通过将所述连接导体(例如冲压栅格)嵌入模制材料中,实现了其就位正确的、不能移动的布置。所述导体衬底本身被作为机械保护件的模制材料包围,从而将如由现有技术已知的、单独的壳体完全地取消。
在一种实施方式中规定,为了散热,使所述导体衬底的外侧至少部分地从所述模制材料中伸出。通过外侧从模制材料中伸出,可以以非常简单的方式实现电路布置的散热。在此通过在伸出的外侧的区域包围所述电子组件的空气进行散热,并且穿过所述导体衬底。如在现有技术中已知的用于散热的特殊壳体可以被取消。
在另一实施方式中,所述导体衬底的外侧或者侧面设置在基体上,特别是在底板上,该底板至少部分地从模制材料中伸出,用于散热。通过在底板或者基体上的设置,可以将热量大面积地散发到基体中或者经过基体散发,特别是当所述基体由导热性非常好的材料,例如由金属制成时。如果将所述基体设置为从模制材料中伸出,则能实现电子组件特别好的散热,而为此不需要特别的制造费用。
在另一实施方式中,将至少两个导体衬底设置为互相间隔,其中所述连接导体被设置在所述导体衬底之间并且与两个导体衬底电连接。如此实现了电子组件特别高的封装密度,其中通过将所述连接导体设置在所述导体衬底之间以及两个导体衬底的同时接触确保了非常简单的、成本非常低的多倍接触。优选地将所述两个导体衬底设置为互相平行或者几乎互相平行,其中将所述连接导体设置为大致在导体衬底中间,互相间隔开。尽管如此,通过这个设置,可以实现非常好的散热。
优选的是,所述连接导体的至少一段从模制材料中伸出,作为电接口。通过这种方式不仅能实现非常简单的多倍接触,而且同时集成了用于所述电子组件的插接器功能。对此不需要附加的部件,例如刀形开关。
在另一种实施方式中,所述导体衬底是电路板。所述电路板在现有技术中是充分地已知的。这些电路板可以用特别简单的方法安装并集成到所述组件中。
在另一种实施方式中规定,所述连接导体通过偏压贴靠在所述导体衬底上。所述连接导体为了接触的目的通过偏压贴靠在所述导体衬底上,从而可以通过连接导体的弹性结构实现与所述导体衬底的接触。偏压可通过导体衬底和连接导体相对彼此的空间布置以非常简单的方式产生。
在一种优选的实施方式中,通过烧结连接使所述连接导体与导体衬底烧结并且由此电连接以及机械连接。特别地,在可靠性和在极端条件下的使用方面,通过烧结材料的内扩散实现的烧结连接特别有利于连接导体和导体衬底的机械固定以及电接触。在少数要求高的应用中可以如上面所描述的、通过纯机械的弹簧接触进行接触,而对于温度经常变化和大温度范围以及例如在机械负载下(振动等)的应用,用于实现更高的工作可靠性的烧结连接是极其有利的。
特别优选的是,所述烧结连接为低温烧结连接。在此低温烧结连接是一种可以通过在低温时烧结的金属例如银-纳米粉引起的烧结连接,该金属在典型地大约200℃的温度下通过需接触的烧结位置之间的内扩散产生机械连接。理想的是,在此,为插入件,也就是连接导体和/或导体衬底,在其各接触位置上镀上镍和/或金,用于促进银的内扩散并由此加强机械固定。还可以选择性地为所述接触位置镀上镍和/或钯和/或金和/或这些金属的合金。
在一种优选的实施方式中,所述导体衬底为低温共烧陶瓷(LTCC)。低温共烧陶瓷是这样一种陶瓷,其中所述导体衬底构造为多层,所述多层与在所谓的厚膜工艺中不同,可以以单一的过程产生(共烧)。在现有技术中,这种混合模块的封装与极高的费用和相对大的壳体构造形式相关联,其中仅通过设计复杂的壳体实现散热。这个缺点可以通过依据本发明的这种实施方式得以解决。
此外提出了一种用于制造电子组件的方法,该电子组件具有至少一个用于支撑组件的、被机械保护体包围的导体衬底,其中实施下列步骤:
a)将所述导体衬底布置在模具中,
b)将固有刚性的、弹性的电连接导体布置在所述导体衬底的对面位置,其中所述连接导体至少部分地与所述导体衬底预紧地接触,
c)用模制材料模注前面所获得的布置结构,用于构成机械保护体。
因此将所述导体衬底布置在模具中,随后在该模具中实现模制。与此相对地,所述连接导体被布置在所述导体衬底的对面位置,其中所述连接导体与导体衬底相接触,但在连接导体和导体衬底之间的接触应在的位置处。如果这种布置存在,那么将模制材料放入所述模具中,对这样获得的导体衬底和连接导体的布置结构进行模注构成机械保护件。与在现有技术中不同的是,也就是不在现成的作为单独零件的壳体中插入任何部件。在对所描述的布置结构用模制材料模注时产生所述机械保护件(在最广泛的意义上也就是需新建立的壳体)。
优选地提供一种方法,在此方法中,在前面所描述的方法顺序之前,借助于在低温下烧结的用于在连接导体的区域中烧结的金属,特别是银-纳米粉和/或镍和/或钯和/或金以及金属的化合物,在所述导体衬底上形成接触位置。
优选的是,在用模制材料压力注塑包封时和/或在模制材料散热时,进行所述区域的烧结。不需要特殊的方法步骤用于烧结,这里即涉及低温烧结,该低温烧结是在模注的温度范围内进行。所述模制材料具有例如大约为300℃的温度,其中烧结在温度大约为200℃已经开始。
在一种优选的方法方案中,所述导体衬底在模制之前与基体,特别是能导热的底板连接或者设置在其上面和/或旁边。由此实现轻微的散热。在一种特别优选的方法方案中,为了实现高封装密度,在模注之前各在相对的位置设置两个导体衬底,其中为了使两个导体衬底至少部分地同时接触,将所述连接导体设置在两个导体衬底之间。当然也可以将所述连接导体设置为至少部分性地从所述模制材料伸出,用于构成插接器。
当然在此这种方法方案也是可能的,在此方法中,分别在相对位置设置多于两个(例如三个、四个或者更多)的导体衬底,并且其中可以在这些导体衬底之间分别设置用于使相对的导体衬底至少部分地同时接触的连接导体,其中还可以同时将相应的连接导体设置为从模制材料中伸出用于外部接触。为了尽可能好的散热,分别在这种堆叠的上侧和下侧设置需要最大温度散发的导体衬底,因此,该导体衬底可以至少部分地从模制材料中伸出或者通过底板被构造为至少部分地从模制材料中伸出。
在另一特别优选的方法方案中,在关闭模具时偏压所述连接导体使其贴靠在至少一个导体衬底上。这意思是,所述连接导体松松地放置在或者贴靠在所述至少一个导体衬底上,并且通过下列方式产生偏压用于在连接导体和导体衬底之间建立可靠接触:将所述模具关闭而且通过模具的关闭改变连接导体和导体衬底之间的相对位置,即距离缩短;这样产生所期望的偏压。
其它有利的实施方式由从属权利要求和它们的组合产生。
附图说明
下面将借助于实施例对本发明进行详细地阐述,但不限于此。
附图中示出了带有两个导体衬底和布置在其间的连接导体的电子组件,该连接导体还被构成为插接器。
具体实施方式
附图示出了电子组件1,所述电子组件带有两个大致上平行对置地设置的导体衬底2,即低温共烧陶瓷(LCTT)3。电子模块4例如半导体5设置在所述导体衬底上。这些电子模块例如通过压焊丝6钎焊或压焊在所述导体衬底2上。在此所述导体衬底2这样平面平行地且互相间隔地设置,从而在所述导体衬底之间设置连接导体7,该连接导体例如至少部分地被构造成冲压栅格8的形式。这个连接导体7具有弹性的接触弹簧9,用于接触所述导体衬底2,所述接触弹簧优选地例如通过冲压和成型与所述连接导体7构成为一体。以所述导体衬底2彼此间的间隔为条件,所述接触弹簧9通过偏压贴靠在各所述导体衬底2的接触位置10上。在所述接触位置10的区域中在所述导体衬底2上涂覆在低温下烧结的金属,特别是银-纳米粉和/或镍和/或钯和/或金。优选地也在接触弹簧9的与所述接触位置10处于接触的端部11上涂覆这种金属。通过模制材料12将之前所描述的由导体衬底2和连接导体7所组成的布置结构模注,其中将用于导体衬底2和嵌入的连接导体7的机械保护件13构造为通过模注所产生的壳体14的形式,由此构成所述电子组件1。因此不需要作为独立零件的单独的壳体。通过用模制材料12模注,在所述接触弹簧9和所述接触位置10的区域内实现热导入,从而在那里使在低温下烧结的金属形成烧结连接15。优选的是低温烧结连接16。由此不仅在所述接触弹簧9之间产生非常好的电连接并且由此通过所述接触位置10产生与所述连接导体7的非常好的电连接,而且还产生所述连接导体7的机械固定,即通过所述接触弹簧9与各导体衬底2的机械固定。这种结构特别是在有机械负载如振动时工作非常可靠。所述导体衬底2以其背面17平放在基体18上,即在由导热材料20制成的底板19上。在模制材料冷却后,这些基体超过模制材料伸出,而且更确切地说,其背向所安装的导体衬底2的侧面21伸出。由此实现所述电子组件1非常好的散热,而不需要附加的冷却体或者特别设置的且为相应的应用情况设计的、单独的壳体,从而以有利的方式提高了工作可靠性。在此通过模具(未示出)实现了所示电子组件1的特别简单且成本低的制造,特别是在模注时或者更确切地说在关闭模具时产生所提及的偏压,通过该偏压连接导体7或者更确切地说其接触弹簧9贴靠在所述导体衬底2或者更确切地说其接触位置10上。此外通过所述连接导体7可以产生所述电子组件1的电接口22,其中,即所述连接导体7被设置为至少部分从所述模制材料12伸出。由此以非常有利和低成本的方式省去附加的接触装置,例如由现有技术已知的刀形开关。特别是在微混合电路技术领域能制造这样成本低且运行十分可靠的电子组件。
Claims (16)
1.一种电子组件,所述电子组件带有至少一个用于支撑组件的、被机械保护件包围的导体衬底,其特征在于,所述导体衬底(2)被作为机械保护件(13)的模制材料(12)所包围并且借助于至少一个固有刚性的、弹性的电连接导体(7)被接触,其中所述连接导体(7)至少部分地嵌入到所述模制材料(12)中。
2.按照权利要求1所述的组件,其特征在于,为了散热,所述导体衬底(2)的外侧至少部分地从所述模制材料(12)中伸出。
3.按照上述权利要求中任意一项所述的组件,其特征在于,所述导体衬底(2)的外侧或者侧面设置在基体(18)上,特别是底板(19)上,该底板为了散热至少部分地从所述模制材料(12)中伸出。
4.按照上述权利要求中任意一项所述的组件,其特征在于,具有至少两个被设置为彼此间隔的导体衬底(2),其中所述连接导体(7)设置在所述导体衬底(2)之间并且与两个导体衬底(2)电连接。
5.按照上述权利要求中任意一项所述的组件,其特征在于,所述连接导体(7)的至少一段从所述模制材料(12)中伸出作为电接口。
6.按照上述权利要求中任意一项所述的组件,其特征在于,所述导体衬底(2)是电路板。
7.按照上述权利要求中任意一项所述的组件,其特征在于,所述连接导体(7)通过偏压贴靠在所述导体衬底(2)上。
8.按照上述权利要求中任意一项所述的组件,其特征在于,所述连接导体(7)与所述导体衬底(2)通过烧结连接(15)烧结。
9.按照上述权利要求中任意一项所述的组件,其特征在于,所述烧结连接(15)是低温烧结连接(16)。
10.按照上述权利要求中任意一项所述的组件,其特征在于,所述导体衬底(2)是低温共烧陶瓷(LTCC)(3)。
11.一种用于制造电子组件的方法,该电子组件具有至少一个用于支撑组件的、被机械保护件包围的导体衬底,所述方法包括以下步骤:
a)将所述导体衬底布置在模具中,
b)将固有刚性的、弹性的电子连接导体布置在所述导体衬底的对面位置,其中所述连接导体至少部分地与所述导体衬底预紧地接触,
c)用模制材料模注前面所获得的布置结构,用于形成机械保护件。
12.按照权利要求11所述的方法,其特征在于,在步骤a)之前,借助于在低温下烧结的用于与所述连接导体的区域烧结的金属,特别是银-纳米粉和/或镍和/或钯和/或金,在所述导体衬底上构成接触位置。
13.按照上述权利要求中任意一项所述的方法,其特征在于,在用模制材料压力注塑包封时和/或在所述模制材料散热时实现所述烧结。
14.按照上述权利要求中任意一项所述的方法,其特征在于,在模制之前,将所述导体衬底与基体,特别是能导热的底板相连接或设置在基体上面和/或基体旁边。
15.按照上述权利要求中任意一项所述的方法,其特征在于,在模注之前,将两个导体衬底分别设置在对面位置,其中将用于使两个导体衬底至少部分地同时接触的所述连接导体设置在所述两个导体衬底之间。
16.按照上述权利要求中任意一项所述的方法,其特征在于,在关闭模具时偏压所述连接导体使其贴靠在至少一个导体衬底上。
Applications Claiming Priority (3)
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DE102008040488.8 | 2008-07-17 | ||
DE102008040488A DE102008040488A1 (de) | 2008-07-17 | 2008-07-17 | Elektronische Baueinheit und Verfahren zu deren Herstellung |
PCT/EP2009/057409 WO2010006864A1 (de) | 2008-07-17 | 2009-06-16 | Elektronische baueinheit und verfahren zu deren herstellung |
Publications (2)
Publication Number | Publication Date |
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CN102090156A true CN102090156A (zh) | 2011-06-08 |
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Application Number | Title | Priority Date | Filing Date |
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Country | Link |
---|---|
US (1) | US20110182048A1 (zh) |
EP (1) | EP2305013B1 (zh) |
JP (1) | JP2011528176A (zh) |
CN (1) | CN102090156B (zh) |
AT (1) | ATE546033T1 (zh) |
DE (1) | DE102008040488A1 (zh) |
WO (1) | WO2010006864A1 (zh) |
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JP2007103948A (ja) * | 2005-10-05 | 2007-04-19 | Semikron Elektronik Gmbh & Co Kg | 絶縁中間層を備えたパワー半導体モジュール及びその製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111799581A (zh) * | 2019-04-05 | 2020-10-20 | 罗伯特·博世有限公司 | 电子电路单元 |
CN111799581B (zh) * | 2019-04-05 | 2024-03-22 | 罗伯特·博世有限公司 | 电子电路单元 |
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EP2305013A1 (de) | 2011-04-06 |
CN102090156B (zh) | 2014-07-16 |
DE102008040488A1 (de) | 2010-01-21 |
JP2011528176A (ja) | 2011-11-10 |
ATE546033T1 (de) | 2012-03-15 |
EP2305013B1 (de) | 2012-02-15 |
WO2010006864A1 (de) | 2010-01-21 |
US20110182048A1 (en) | 2011-07-28 |
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