CN114999944A - 半导体装置和其制造方法 - Google Patents

半导体装置和其制造方法 Download PDF

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Publication number
CN114999944A
CN114999944A CN202210587193.XA CN202210587193A CN114999944A CN 114999944 A CN114999944 A CN 114999944A CN 202210587193 A CN202210587193 A CN 202210587193A CN 114999944 A CN114999944 A CN 114999944A
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China
Prior art keywords
layer
conductive
dielectric layer
dielectric
conductive layer
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Pending
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CN202210587193.XA
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English (en)
Chinese (zh)
Inventor
金东吉
金吉翰
杜文秋
贝杰翰
其王门
翰东和
金杜浑
李吉和
朴金文
孙山南
邱翰
可提斯·斯文格
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Amkor Technology Inc
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Amkor Technology Inc
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Application filed by Amkor Technology Inc filed Critical Amkor Technology Inc
Priority claimed from PCT/US2016/022746 external-priority patent/WO2016149441A1/en
Publication of CN114999944A publication Critical patent/CN114999944A/zh
Pending legal-status Critical Current

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    • H01L2924/141—Analog devices
    • H01L2924/142—HF devices
    • H01L2924/1421—RF devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/14335—Digital signal processor [DSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
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Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101676916B1 (ko) 2014-08-20 2016-11-16 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
US20170287838A1 (en) 2016-04-02 2017-10-05 Intel Corporation Electrical interconnect bridge
US20170338128A1 (en) * 2016-05-17 2017-11-23 Powertech Technology Inc. Manufacturing method of package structure
KR20170143129A (ko) * 2016-06-20 2017-12-29 삼성디스플레이 주식회사 전자 장치 및 이의 제조 방법
US10141198B2 (en) * 2016-07-08 2018-11-27 Dyi-chung Hu Electronic package and manufacturing method thereof
US9960328B2 (en) 2016-09-06 2018-05-01 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US9865570B1 (en) 2017-02-14 2018-01-09 Globalfoundries Inc. Integrated circuit package with thermally conductive pillar
US10037949B1 (en) * 2017-03-02 2018-07-31 Amkor Technology, Inc. Semiconductor package and fabricating method thereof
US10177011B2 (en) * 2017-04-13 2019-01-08 Powertech Technology Inc. Chip packaging method by using a temporary carrier for flattening a multi-layer structure
US11699651B2 (en) 2017-10-23 2023-07-11 Applied Materials, Inc. Fan-out interconnect integration processes and structures
CN109727944B (zh) * 2017-10-31 2021-02-05 长鑫存储技术有限公司 一种集成封装半导体器件
KR102055595B1 (ko) * 2017-12-15 2019-12-16 삼성전자주식회사 반도체 패키지
US10410999B2 (en) 2017-12-19 2019-09-10 Amkor Technology, Inc. Semiconductor device with integrated heat distribution and manufacturing method thereof
JP7100980B2 (ja) 2018-01-22 2022-07-14 ローム株式会社 Ｌｅｄパッケージ
KR102450570B1 (ko) 2018-10-02 2022-10-07 삼성전자주식회사 반도체 패키지
KR102530322B1 (ko) 2018-12-18 2023-05-10 삼성전자주식회사 반도체 패키지
KR102208065B1 (ko) * 2019-01-04 2021-01-27 주식회사 프로텍 플립칩 레이저 본딩 시스템
KR20200113069A (ko) * 2019-03-20 2020-10-06 삼성전자주식회사 반도체 소자 제조 방법
DE102019107760A1 (de) * 2019-03-26 2020-10-01 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zur herstellung einer verbindungsstruktur und halbleiterbauelement
DE102019115369A1 (de) * 2019-06-06 2020-12-10 Infineon Technologies Ag Verfahren zur herstellung eines halbleiter-flip-chip-package
US10770424B1 (en) * 2019-08-13 2020-09-08 Nanya Technology Corporation Semiconductor structure and method of manufacturing thereof
KR20210028398A (ko) 2019-09-04 2021-03-12 삼성전자주식회사 재배선 패턴을 가지는 집적회로 소자
US11721603B2 (en) * 2020-10-15 2023-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan out method utilizing a filler-free insulating material
US11784114B2 (en) * 2020-12-08 2023-10-10 Texas Instruments Incorporated Plated metal layer in power packages
TWI799238B (zh) * 2022-04-22 2023-04-11 宏齊科技股份有限公司 封裝方法及封裝結構
TWI809966B (zh) * 2022-05-17 2023-07-21 南亞科技股份有限公司 具有氟捕捉層的半導體元件結構

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2199462C (en) 1996-03-14 2006-01-03 Charles J. Winslow Method and instrumentation for implant insertion
SG106054A1 (en) 2001-04-17 2004-09-30 Micron Technology Inc Method and apparatus for package reduction in stacked chip and board assemblies
SG115456A1 (en) * 2002-03-04 2005-10-28 Micron Technology Inc Semiconductor die packages with recessed interconnecting structures and methods for assembling the same
EP1527480A2 (en) 2002-08-09 2005-05-04 Casio Computer Co., Ltd. Semiconductor device and method of manufacturing the same
JP4565861B2 (ja) * 2004-02-27 2010-10-20 日本特殊陶業株式会社 配線基板の製造方法
US9460951B2 (en) * 2007-12-03 2016-10-04 STATS ChipPAC Pte. Ltd. Semiconductor device and method of wafer level package integration
JP5577760B2 (ja) 2009-03-09 2014-08-27 新光電気工業株式会社 パッケージ基板および半導体装置の製造方法
US8383457B2 (en) 2010-09-03 2013-02-26 Stats Chippac, Ltd. Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect
US8008121B2 (en) 2009-11-04 2011-08-30 Stats Chippac, Ltd. Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate
US9385095B2 (en) 2010-02-26 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
KR101121827B1 (ko) 2010-04-13 2012-03-21 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
US8581418B2 (en) * 2010-07-21 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-die stacking using bumps with different sizes
JP2012069734A (ja) * 2010-09-24 2012-04-05 Toshiba Corp 半導体装置の製造方法
US9224647B2 (en) 2010-09-24 2015-12-29 Stats Chippac, Ltd. Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer
KR101767108B1 (ko) * 2010-12-15 2017-08-11 삼성전자주식회사 하이브리드 기판을 구비하는 반도체 패키지 및 그 제조방법
JP6028449B2 (ja) * 2011-10-05 2016-11-16 富士通株式会社 半導体装置、電子装置、半導体装置の製造方法
US8686570B2 (en) 2012-01-20 2014-04-01 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-dimensional integrated circuit structures and methods of forming the same
US8741691B2 (en) 2012-04-20 2014-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating three dimensional integrated circuit
US20130337648A1 (en) 2012-06-14 2013-12-19 Bridge Semiconductor Corporation Method of making cavity substrate with built-in stiffener and cavity
US8618648B1 (en) 2012-07-12 2013-12-31 Xilinx, Inc. Methods for flip chip stacking
US8872326B2 (en) 2012-08-29 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Three dimensional (3D) fan-out packaging mechanisms
US9209156B2 (en) 2012-09-28 2015-12-08 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional integrated circuits stacking approach
KR101366461B1 (ko) 2012-11-20 2014-02-26 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
KR101419601B1 (ko) 2012-11-20 2014-07-16 앰코 테크놀로지 코리아 주식회사 Emc 웨이퍼 서포트 시스템을 이용한 반도체 디바이스 및 이의 제조방법
US8946884B2 (en) * 2013-03-08 2015-02-03 Xilinx, Inc. Substrate-less interposer technology for a stacked silicon interconnect technology (SSIT) product
US8951838B2 (en) * 2013-03-14 2015-02-10 Taiwan Semiconductor Manufacturing Company, Ltd. Low cost and ultra-thin chip on wafer on substrate (CoWoS) formation
US8941244B1 (en) * 2013-07-03 2015-01-27 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US9159678B2 (en) * 2013-11-18 2015-10-13 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US9524942B2 (en) * 2013-12-18 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-substrate packaging on carrier
US9793243B2 (en) * 2014-08-13 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Buffer layer(s) on a stacked structure having a via
KR101676916B1 (ko) * 2014-08-20 2016-11-16 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
US9502321B2 (en) * 2014-10-24 2016-11-22 Dyi-chung Hu Thin film RDL for IC package
US9818684B2 (en) * 2016-03-10 2017-11-14 Amkor Technology, Inc. Electronic device with a plurality of redistribution structures having different respective sizes
US10032756B2 (en) * 2015-05-21 2018-07-24 Mediatek Inc. Semiconductor package assembly with facing active surfaces of first and second semiconductor die and method for forming the same
US10103125B2 (en) * 2016-11-28 2018-10-16 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same

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US11948808B2 (en) 2024-04-02
KR101731700B1 (ko) 2017-04-28
US20220165582A1 (en) 2022-05-26
KR20160112210A (ko) 2016-09-28
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US20160276174A1 (en) 2016-09-22
US10553451B2 (en) 2020-02-04
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TW202305958A (zh) 2023-02-01
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US20180308712A1 (en) 2018-10-25

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