CN1143830A - 制造ldd结构的mos晶体管的方法 - Google Patents
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- 238000005468 ion implantation Methods 0.000 claims description 21
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H—ELECTRICITY
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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Abstract
本发明的MOS晶体管具有LDD结构,其特征是,漏是由N-型杂质区或N-/N+杂质区构成,源是由N+型杂质区构成,所以源和漏间的寄生效应是相同的。
Description
本发明涉及一种制造LDD结构的MOS晶体管的方法,尤其涉及一种制造不对称LDD(轻掺杂漏)结构的MOS晶体管的方法。
通常,在NMOS晶体管的源和漏之间存在着很大差别的寄生效应。源一侧的寄生电阻使有效栅电压有很大程度地减小,但对漏一侧的漏电流却只有很小的影响。因此,由于源和漏间的寄生效应的差别便产生了使VLSI半导体器件的驱动力减弱和热载流子效应增加的问题。
因此,本发明的目的是提供一种制造不对称LDD结构的MOS晶体管的方法,以增加半导体器件的驱动力,减小热载流子效应。
为实现上述目的,制造LDD结构的MOS晶体管的方法包括以下步骤:
通过第一离子注入工艺,将N-型杂质离子注入到在其上形成栅极的半导体基片内;
通过第二离子注入工艺,将N+型杂质离子注入到在其上形成源极的半导体基片区域内;
进行退火工艺,激活已注入到半导体基片内的N+和N-型杂质离子,由此形成由N-型杂质区构成的漏和由N+型杂质区构成的源。
制造LDD结构的MOS晶体管的方法包括以下步骤:
通过第一离子注入工艺,将N-型杂质离子注入到在其上形成栅极的半导体基片内;
通过第二离子注入工艺,将N+型杂质离子注入到在其上形成漏极的半导体基片区域之外的区域内;和
进行退火工艺,激活已注入到半导体基片内的N+和N-型杂质离子,由此形成由N-型杂质区及N+杂质区构成的漏和由N+型杂质区构成的源。
为了充分理解本发明的性质和目的,下面将参照附图对本发明进行详细描述。
图1A~1C是用来解释根据本发明的第一个实施例制造LDD结构的MOS晶体管方法的器件剖面图。
图2A~2C是用来解释根据本发明的第二个实施例制造LDD结构的MOS晶体管方法的器件剖面图。
在各附图中,相同的参考标记代表相同的部件。
下面将参照附图对本发明进行详细描述。
图1A~1C是用来解释根据本发明的第一个实施例制造LDD结构MOS晶体管方法的器件剖面图。
图1A是一器件的剖面图,它表示的是:在半导体基片1上形成场氧化膜2,由常规工艺在半导体基片上形成栅氧化膜3和栅极4,用栅极4作掩膜,由第一离子注入工艺,将N-型杂质离子注入到半导体基片1内。
第一离子注入工艺所用N-型杂质离子是P31,所用P31剂量是1.5E13,所用能量为60KeV。
图1B是一器件的剖面图,它表示的是:形成光刻胶图形5,以在将要形成源的半导体基片1区域上开口,然后,用光刻胶图形5作掩膜,由第二离子注入工艺,将N+型杂质离子注入到半导体基片1内。
第二离子注入工艺所用N+型杂质离子是As75,所用As75剂量为6.0E15,所用能量为60KeV。
图1C是一器件的剖面图,它表示的是:在除去光刻胶图形5后,进行退火工艺,激活已注入到半导体基片1内的N-和N+杂质离子,由此形成由N-型杂质区构成的漏6A和由N+型杂质区构成的源6B。
图2A~2C是用来解释根据本发明的第二个实施例制造LDD结构MOS晶体管方法的器件剖面图。
图2A是一器件的剖面图,它表示的是:在半导体基片1上形成场氧化膜2,由常规工艺在半导体基片上形成栅氧化膜3和栅极4,用栅极4作掩膜,由第一离子注入工艺,将N-型杂质离子注入到半导体基片1内。
第一离子注入工艺所用N-型杂质离子是P31,所用P31剂量为1.5E13,所用能量为60KeV。并且,最好是将具有约为5~10度斜度的N-型杂质离子投射到将要形成LDD的一侧。
图2B是一器件的剖面图,它表示的是:形成光刻胶图形5以覆盖从栅极4到0.1~0.3微米范围的将要形成漏的半导体基片1的区域,用光刻胶图形5作掩膜,由第二离子注入工艺,将N+型杂质离子注入到半导体基片1内。
第二离子注入工艺所用N+型杂质离子是As75,所用As75剂量为6.0E15,所用能量为60KeV。
图2C是一器件的剖面图,它表示的是:在除去光刻胶图形5后,进行退火工艺,激活已注入到半导体基片1内的N-和N+杂质离子,由此形成由N-型杂质区及N+型杂质区构成的漏6A和由N+型杂质区构成的源6B。
N-型杂质区处于栅极4和N+型杂质区之间,其长度为0.1~0.3微米。
如上所述,发明的MOS晶体管具有不对称结构,其中,漏是由N-型杂质区或N-/N+型杂质区构成,源是由N+型杂质区构成。
因此,由于在源和漏间具有相同的寄生效应,不对称结构的MOS晶体管能改善驱动力,并能减小热载流子效应。
尽管上面参照实施例对本发明作了一定程度地说明,但上述说明只是对本发明原理的说明。应该理解到,发明并不限于这里所公开和说明的优选实施例。所以,根据本发明的精神和实质所作的任何变型皆包含在本发明进一步的实施例中。
Claims (9)
1 一种制造LDD结构MOS晶体管的方法,包括以下步骤:
通过第一离子注入工艺,将N-型杂质离子注入到在其上形成栅极的半导体基片内;
通过第二离子注入工艺,将N+型杂质离子注入到在其上将要形成源的半导体基片内;和
进行退火工艺,激活已注入到半导体基片内的N+和N-型杂质离子,由此形成由N-型杂质区构成的漏和由N+型杂质区构成的源。
2 根据权利要求1的制造LDD结构MOS晶体管的方法,其特征是所说第一离子注入工艺所用N-型杂质离子是P31,所用P31剂量为1.5E13,所用能量为60KeV。
3 根据权利要求1的制造LDD结构MOS晶体管的方法,其特征是所说第二离子注入工艺所用N+型杂质离子是As75,所用As75剂量为6.0E15,所用能量为60KeV。
4 一种制造LDD结构MOS晶体管的方法,包括以下步骤:
通过第一离子注入工艺,将N-型杂质离子注入到在其上形成栅极的半导体基片内;
通过第二离子注入工艺,将N+型杂质离子注入到在其上将要形成源极的半导体基片区域内;和
进行退火工艺,激活已注入到半导体基片内的N+和N-型杂质离子,由此形成由N-型杂质区及N+型杂质区构成的漏,和由N+型杂质区构成的源。
5 根据权利要求4的制造LDD结构MOS晶体管的方法,其特征是所说第一离子注入工艺所用N-型杂质离子是P31,所用P31剂量是1.5E13,所用能量为60KeV。
6 根据权利要求4的制造LDD结构MOS晶体管的方法,其特征是所说第一离子注入工艺是将具有5~10度斜度的N-型杂质离子投射到将要形成LDD的一侧。
7 根据权利要求4的制造LDD结构MOS晶体管的方法,其特征是所说第二离子注入工艺所用N+型杂质离子是As75,所用As75剂量为6.0E15,所用能量为60KeV。
8 根据权利要求4的制造LDD结构MOS晶体管的方法,其特征是所说N-型杂质区处于栅极和N+型杂质区之间。
9 根据权利要求4的制造LDD结构MOS晶体管的方法,其特征是在栅和和N+型杂区之间以0.1~0.3微米的长度形成所说N-型杂区。
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KR6094/1995 | 1995-03-22 | ||
KR6094/95 | 1995-03-22 | ||
KR1019950006094A KR100187673B1 (ko) | 1995-03-22 | 1995-03-22 | 반도체 소자의 제조방법 |
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CN1143830A true CN1143830A (zh) | 1997-02-26 |
CN1073280C CN1073280C (zh) | 2001-10-17 |
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101414554B (zh) * | 2007-10-17 | 2010-04-14 | 中芯国际集成电路制造(上海)有限公司 | 离子注入方法 |
CN101452853B (zh) * | 2007-12-07 | 2010-09-29 | 中芯国际集成电路制造(上海)有限公司 | Mos晶体管的形成方法 |
CN101621006B (zh) * | 2008-07-03 | 2011-01-12 | 中芯国际集成电路制造(上海)有限公司 | 利用锗预非晶处理来形成p-型轻度掺杂的漏极区的方法 |
CN101989551B (zh) * | 2009-08-06 | 2012-01-25 | 中芯国际集成电路制造(上海)有限公司 | 不对称晶体管的形成方法 |
CN103247528A (zh) * | 2012-02-03 | 2013-08-14 | 中芯国际集成电路制造(上海)有限公司 | 金属氧化物半导体场效应管的制造方法 |
CN107134409A (zh) * | 2016-02-26 | 2017-09-05 | 北大方正集团有限公司 | 晶体管的离子注入方法和晶体管 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5061975A (en) * | 1988-02-19 | 1991-10-29 | Mitsubishi Denki Kabushiki Kaisha | MOS type field effect transistor having LDD structure |
JPH0320081A (ja) * | 1989-06-16 | 1991-01-29 | Matsushita Electron Corp | 半導体集積回路 |
-
1995
- 1995-03-22 KR KR1019950006094A patent/KR100187673B1/ko not_active IP Right Cessation
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1996
- 1996-03-22 CN CN96105548A patent/CN1073280C/zh not_active Expired - Fee Related
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101414554B (zh) * | 2007-10-17 | 2010-04-14 | 中芯国际集成电路制造(上海)有限公司 | 离子注入方法 |
CN101452853B (zh) * | 2007-12-07 | 2010-09-29 | 中芯国际集成电路制造(上海)有限公司 | Mos晶体管的形成方法 |
CN101621006B (zh) * | 2008-07-03 | 2011-01-12 | 中芯国际集成电路制造(上海)有限公司 | 利用锗预非晶处理来形成p-型轻度掺杂的漏极区的方法 |
CN101989551B (zh) * | 2009-08-06 | 2012-01-25 | 中芯国际集成电路制造(上海)有限公司 | 不对称晶体管的形成方法 |
CN103247528A (zh) * | 2012-02-03 | 2013-08-14 | 中芯国际集成电路制造(上海)有限公司 | 金属氧化物半导体场效应管的制造方法 |
CN103247528B (zh) * | 2012-02-03 | 2015-09-02 | 中芯国际集成电路制造(上海)有限公司 | 金属氧化物半导体场效应管的制造方法 |
CN107134409A (zh) * | 2016-02-26 | 2017-09-05 | 北大方正集团有限公司 | 晶体管的离子注入方法和晶体管 |
CN107134409B (zh) * | 2016-02-26 | 2020-07-14 | 北大方正集团有限公司 | 晶体管的离子注入方法和晶体管 |
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Publication number | Publication date |
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KR100187673B1 (ko) | 1999-06-01 |
CN1073280C (zh) | 2001-10-17 |
KR960035914A (ko) | 1996-10-28 |
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