CN1176493A - 半导体集成电路装置及其制造方法 - Google Patents

半导体集成电路装置及其制造方法 Download PDF

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CN1176493A
CN1176493A CN97103426A CN97103426A CN1176493A CN 1176493 A CN1176493 A CN 1176493A CN 97103426 A CN97103426 A CN 97103426A CN 97103426 A CN97103426 A CN 97103426A CN 1176493 A CN1176493 A CN 1176493A
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山冈徹
本田浩嗣
樱井浩司
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Abstract

一种半导体集成电路装置及其制造方法,其特征在于,在设有P阱区和分离元件用硅氧化膜的P型电阻率为10～20Ωcm的单晶硅衬底上,分别构成绝缘栅型场效应晶体管A及B的各自的沟道掺杂区,一沟道掺杂区的杂质浓度为另一沟道掺杂区杂质浓度的2倍至10倍。因此。能独立控制两种绝缘栅型场效应晶体管的特性,抑制了高耐压CMOS晶体管电特性的离散性,并能缩小该晶体管的占有面积。

Description

半导体集成电路装置及其制造方法
本发明涉及将常用电源电压下工作的绝缘栅型场效应晶体管及高耐压绝缘栅型场效应晶体管集成化的半导体集成电路装置及其制造方法。这种常用电源电压下工作的绝缘栅型场效应晶体管如逻辑电路用的CMOS晶体管；高耐压绝缘栅型场效应晶体管如对可编程(programmable)元件进行写入用的高耐压CMOS晶体管等。
近来年，人们越来越关注于一种由电子装置的用户可改写从而实现所希望电路的门阵列(gate array)，即现场可编程门阵列(Field Programmable GateArray)，缩称为FPGA。在用于FPGA的可编程元件中，不久可见到一种防熔断(antifuse)元件。这种防熔断元件的写入电压Vpp，其Vpp/2必须设定得比逻辑电路用电源电压要高。因而，防熔断写入时，漏极耐压比逻辑电路用电源电压高，也即必须要高耐压晶体管。
下面，用图3(a)～(d)为例说明已有半导体集成电路装置的制造方法。
图3为FPGA所使用的元件中，构成逻辑电路的标准N沟道型MOS晶体管(下面称为：“N沟道标准晶体管”，或简称为“标准晶体管”)和防熔断写入时使用的N沟道型高耐压MOS晶体管(下面称为“N沟道高耐压晶体管”或简称为“高耐压晶体管”)在工艺流程中的元件剖面构造图。
图3(a)表示氧化膜刻蚀工艺，用于对N沟道标准晶体管和N沟道高耐压晶体管分别形成所需厚度的栅(gate)绝缘膜，在P型单晶硅衬底1上设有较厚的硅氧化膜3及沟道渗杂区4，用以将P阱区2及各元件分开。在形成第一栅绝缘膜5之后，至少用第一保护膜6覆盖高耐压晶体管形成区，再用缓冲氟酸等有选择地除去N沟道标准晶体管形成区上的栅绝缘膜(未图示)。
然后，如图3(b)所示，在除去第一保护膜6之后，形成第二栅绝缘膜7，再掺入磷等N型杂质，生成构成栅电极的多晶硅8。
接着，如图3(c)所示，在有选择地刻蚀除去多晶硅膜8形成高耐压晶体管用第一栅(gate)电极9及标准晶体管用第二栅电极10之后，用栅电极9及栅电极10作为掩膜，自对准离子注入如磷等N型杂质11，分别形成作为补偿(offset)扩散层的N-型扩散层区12及作为LDD的N-型扩散层区13。
进而如图3(d)所示，在第一栅电极9及第二栅电极10上分别设置第一侧壁隔层(spacer)14及第二侧壁隔层15之后，将第二保护膜16作为掩膜，离子注入如砷等N型杂质17，对高耐压晶体管形成N-型补偿(off-see)扩散层18、N+型源极区19及N+型漏极区20。同时对标准晶体管形成N-型LDD扩散层21、N+型源极区22及N+型漏极区23。
但是，在上述已有技术半导体集成电路装置中存在如下问题。由于标准晶体管和高耐压晶体管共用沟道渗杂(dope)区4，故如果为了抑制标准晶体管的短沟道效应而要提高沟道杂质区4的杂质浓度时，就会降低高耐压晶体管的漏极耐压。
再有，由于第二保护膜16的尺寸离散或掩膜偏离(不吻合)等，会引起N-型补偿扩散层18尺寸的离散，因此，使高耐压晶体管的电特性，尤其是漏极耐压及饱和电流发生离散。另一方面，若为了改善这种电特性，考虑到加工的离散性而设计晶体管单元的布局，就会出现元件占有面积变大的新问题。
本发明目的在于提供一种同时改善标准晶体管的短沟道特性及高耐压晶体管的漏极耐压特性、能控制高耐压晶体管电特性的离散性、并能缩小高耐压晶体管占有面积的半导体集成电路装置及其制造方法。
本发明的半导体集成电路装置，在将多种场效应晶体管集成化的半导体集成电路装置中，对各种场效应晶体管的沟道渗杂区掺有不同浓度的杂质，尤其是在将两种绝缘栅型场效应晶体管集成化的半导体集成电路装置中，取第二绝缘栅型场效应晶体管的沟道掺杂区中的杂质浓度为第一绝缘栅型场效应晶体管的沟道掺杂区中杂质浓度的2至10倍。
本发明的半导体集成电路装置的制造方法，包含：在形成第一绝缘栅型场效应晶体管和第二绝缘栅型场效应晶体管的区域上形成栅绝缘膜的工艺；对形成第二绝缘栅型场效应晶体管区域上的沟道掺杂区有选择地进行掺杂的工艺；通过有选择地除去形成第二绝缘栅型场效应晶体管区域上的栅绝缘膜，在第一绝缘栅型场效应晶体管的形成区上形成第一栅绝缘膜的工艺；在第二绝缘栅型场效应晶体管的形成区上形成第二栅绝缘膜的工艺；分别形成由半导体或金属等导电性膜构成的第一及第二绝缘栅型场效应晶体管的第一及第二栅电极的工艺；将第一及第二栅电极作为掩膜，自对准地以40～50度的注入角度离子注入N型杂质的工艺；在第一及第二栅电极的侧壁形成隔层的工艺；取第一及第二栅电极和侧壁隔层作为掩膜，自对准地离子注入N型杂质的工艺。
因此，按照本发明，能按所需厚度形成各栅绝缘膜，用于多种场效应晶体管，并使多种场效应晶体管的沟道掺杂区生成各自必须的不同的杂质浓度，故能同时改善标准晶体管的短沟道特性及高耐压晶体管的漏极耐压特性。而且能对高耐压晶体管电特性的离散性进行控制，并能缩小高耐压晶体管的占有面积。
本发明权利要求1所记载的发明，在将多种场效应晶体管集成化的半导体集成电路装置中，使各场效应晶体管的沟道掺杂区中有不同的杂质浓度，能同时改善多种场效应晶体管的电特性。
权利要求2所记载的发明，在将两种绝缘栅型场效应晶体管集成化的半导体集成电路装置中，取第二绝缘栅型场效应晶体管沟道掺杂区中的杂质浓度为第一绝缘栅型场效应晶体管沟道掺杂区中杂质浓度的2至10倍，能提高第一绝缘栅型场效应晶体管的漏极耐压。
权利要求3所记载的发明，取第一绝缘栅型场效应晶体管为N沟道型高耐压MOS晶体管，取第二绝缘栅型场效应晶体管为N沟道型MOS晶体管，能提高N沟道型高耐压MOS晶体管的漏极耐压。
权利要求4所记载的发明，是一种将第一和第二绝缘栅型场效应晶体管集成化的半导体集成电路装置的制造方法，包含：在半导体衬底上形成第一和第二绝缘栅型场效应晶体管的区域上形成栅绝缘膜的工艺；对形成第二绝缘栅型场效应晶体管区域上的沟道掺杂区有选择地进行掺杂的工艺；通过有选择地除去形成第二绝缘栅型场效应晶体管区域上的栅绝缘膜，在第一绝缘栅型场效应晶体管的形成区上形成第一栅绝缘膜的工艺；在第二绝缘栅型场效应晶体管的形成区上形成第二栅绝缘膜的工艺；分别形成由半导体或金属等导电性膜构成的第一及第二绝缘栅型场效应晶体管的第一和第二栅电极的工艺，能按所需厚度形成第一和第二绝缘栅型场效应晶体管使用的第一和第二栅绝缘膜，并能使第一及第二绝缘栅型场效应晶体管的沟道掺杂区生成各自必须的不同的杂质浓度。
权利要求5所记载的发明，是一种将第一绝缘栅型场效应晶体管和第二绝缘栅型场效应晶体管集成化的半导体集成电路装置的制造方法，其形成源极和漏极扩散区的工艺包含：将第一栅电极及第二栅电极作为掩膜，边旋转半导体衬底，边以40～50度仰角自对准离子注入N型杂质的工艺；对第一及第二栅电极的侧壁形成隔层的工艺；将第一及第二栅电极和侧壁隔层作为掩膜自对准离子注入N型杂质的工艺。由于能自对准形成第二绝缘栅型场效应晶体管的补偿扩散层，能抑制补偿扩散层尺寸离散，故能改善第二绝缘栅型场效应晶体管的电特性，尤其能抑制漏极耐压及饱和电流的离散。而且，在形成补偿扩散层中，可以不考虑保护膜尺寸离散和掩膜对准余量，从而能缩小第二绝缘栅型场效应晶体管的占有面积。
附图说明
图1为本发明一实施例的半导体集成电路装置剖面图；
图2(a)～(d)为表示图1半导体集成电路装置制造工艺的半导体集成电路装置剖面图；
图3为已有技术制造方法工艺的半导体集成电路装置剖面图。
下面，就本发明最佳实施例，一面参照图1、图2，一面对比图3，将其相同部分赋以同一标号并省略其详细说明，而着重说明其不同点。
(实施例1)
图1所示为本发明第一实施例，图1中标号A表示N沟道高耐压晶体管的第一绝缘栅型场效应晶体管；B表示N沟道标准晶体管的第二绝缘栅型场效应晶体管。
本发明的半导体集成电路装置与图3所示已有技术半导体集成电路装置在结构上的不同点是，沟道掺杂区分别由第一绝缘栅型场效应晶体管的第一沟道掺杂区4a和第二绝缘栅型场效应晶体管的第二沟道掺杂区4b构成；第二沟道掺杂区4b的杂质浓度是第一沟道掺杂区4a杂质浓度的2至10倍。
(实施例2)
下面说明本发明第二实施例中半导体集成电路装置的制造方法。
图2(a)～(d)表示FPGA所使用的元件中N沟道标准晶体管和N沟道高耐压晶体管在工艺流程中的剖面结构。
图2(a)表示分别对N沟道标准晶体管B和N沟道高耐压晶体管A形成所需厚度的栅氧化膜的氧化膜刻蚀工艺，和将杂质掺入N沟道标准晶体管B的沟道区的掺杂工艺。在P型电阻率为10～20Ωcm的单晶硅衬底1上设置P阱区2之后，再设置用于分离元件的厚度为300～500nm的硅氧化膜3和第一沟道掺杂区4a。在形成厚15～30nm的第一栅氧化膜5之后，用第一保护膜6覆盖图1所示N沟道高耐压晶体管A的形成区，按照掺杂量为5×1011～5×1012cm-2有选择地将如硼等P型杂质24离子注入N沟道标准晶体管B的沟道区中，形成第二沟道掺杂区4b。
然后，用缓冲氟酸等有选择地除去N沟道标准晶体管B形成区上的第一栅氧化膜5。第二沟道掺杂区4b的杂质浓度是第一沟道掺杂区4a杂质浓度的2～10倍。
接着，如图2(b)所示，除去保护膜6之后，在N沟道标准晶体管B的上面形成厚为5～15nm的第二栅氧化膜7，其上生长构成栅电极的掺有如磷等N型杂质、厚为300～500nm的多晶硅8。
再接下来，如图2(c)所示，在有选择地刻蚀多晶硅膜8形成N沟道高耐压晶体管用第一栅电极9及N沟道标准晶体管用第二栅电极10之后，以第一及第二栅电极9及10作为掩膜，自对准离子注入如磷等N型杂质11，形成作为补偿扩散层的N-型扩散层区12及作为LDD的N-型扩散层区13。再一边使半导体衬底1旋转，一边以40～50度仰角进行离子注入，在掺磷的情况下，加速能量为80KeV以上，总掺杂量为2×1013～2×1014cm-2。
最后，如图2(d)所示，将第一及第二栅电极9、10作为掩膜有选择地刻蚀除去第一及第二栅氧化膜5及7之后，分别在第一及第二栅电极9及10上形成第一及第二侧壁隔层14及15。
再接着通过离子注入如砷等N型杂质17，对高耐压晶体管分别形成N-型补偿扩散层18、N+型源极区19及N+型漏极区20，同时对标准晶体管分别形成N-型LDD扩散层21、N+型源极区22及N+型漏极区23。
如上所述，按照上述实施例，分别对N沟道标准晶体管B及N沟道高耐压晶体管A形成所需厚度的栅氧化膜5及7，并分别形成具有所需的不同杂质浓度的沟道掺杂区4a及4b。因此，可分别独立地对N沟道标准晶体管B和N沟道高耐压晶体管A的特性进行控制。
按照本实施例，可自对准形成N沟道高耐压晶体管A的补偿扩散层18。也即，像已有技术那样的掩膜工艺中保护膜尺寸的离散或掩膜对准差给与补偿扩散层18尺寸的影响，或其加工误差引起的N沟道高耐压晶体管A的电特性、尤其是漏极耐压及饱和电流等方面出现大的离散，将不复存在。并能抑制N沟道高耐压晶体管A电特性的离散性。
再有，对N沟道高耐压晶体管A布局时，无需考虑像已有技术那样的形成N-型补偿扩散层18中产生的保护膜尺寸离散或掩膜对准裕量，故能缩小N沟道高耐压晶体管A的占有面积。
综上所述，本发明对半导体集成电路装置中的渗道掺杂区分别由设于第一绝缘栅型场效应晶体管的第一沟道掺杂区和设于第二绝缘栅型场效应晶体管的第二沟道掺杂区构成，且第二沟道掺杂区的杂质浓度是第一沟道掺杂区杂质浓度的2至10倍，故能独立控制两种绝缘栅型场效应晶体管的特性，因此，能提高高耐压绝缘栅型场效应晶体管的漏极耐压。另外，还能抑制高耐压绝缘栅型场效应晶体管中补偿扩散层尺寸加工的误差，从而能抑制电特性的离散。进而还可缩小高耐压绝缘栅型场效应晶体管的占有面积。

Claims (5)

1.一种半导体集成电路装置，其特征在于，在将多种场效应晶体管集成化的半导体集成电路装置中，对各种场效应晶体管的沟道渗杂区掺有不同浓度的杂质。
2.一种半导体集成电路装置，其特征在于，在将两种绝缘栅型场效应晶体管集成化的半导体集成电路装置中，取第二绝缘栅型场效应晶体管的沟道掺杂区中的杂质浓度为第一绝缘栅型场效应晶体管的沟道掺杂区中杂质浓度的2至10倍。
3.如权利要求2所述的半导体集成电路装置，其特征在于，所述第一绝缘栅型场效应晶体管是N沟道高耐压MOS晶体管；所述第二绝缘栅型场效应晶体管是N沟道型MOS晶体管。
4.一种半导体集成电路装置的制造方法，是一种将第一和第二绝缘栅型场效应晶体管集成化的半导体集成电路装置的制造方法，其特征在于，包含：在半导体衬底上形成所述第一绝缘栅型场效应晶体管和第二绝缘栅型场效应晶体管的区域形成栅绝缘膜的工艺；对形成所述第二绝缘栅型场效应晶体管区域上的沟道掺杂区有选择地进行掺杂的工艺；通过有选择地除去形成所述第二绝缘栅型场效应晶体管区域上的所述栅绝缘膜，在所述第一绝缘栅型场效应晶体管的形成区上形成第一栅绝缘膜的工艺；在所述第二绝缘栅型场效应晶体管的形成区上形成第二栅绝缘膜的工艺；分别形成由半导体或金属等导电性膜构成的所述第一绝缘栅型场效应晶体管的第一栅电极及第二绝缘栅型场效应晶体管的第二栅电极的工艺。
5.一种半导体集成电路装置的制造方法，是一种将第一绝缘栅型场效应晶体管和第二绝缘栅型场效应晶体管集成化的半导体集成电路装置的制造方法，其特征在于，形成源极和漏极的扩散区的工艺包含：将第一及第二栅电极作为掩膜边使半导体衬底旋转边自对准地以40～50度的仰角离子注入N型杂质的工艺；在所述第一及第二栅电极的侧壁形成隔层的工艺；取所述第一及第二栅电极和所述侧壁隔层作为掩膜，自对准地离子注入N型杂质的工艺。
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