CN1050700C - 半导体器件中的晶体管及其制造方法 - Google Patents

半导体器件中的晶体管及其制造方法 Download PDF

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CN1050700C
CN1050700C CN96108209A CN96108209A CN1050700C CN 1050700 C CN1050700 C CN 1050700C CN 96108209 A CN96108209 A CN 96108209A CN 96108209 A CN96108209 A CN 96108209A CN 1050700 C CN1050700 C CN 1050700C
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黄儁
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SK Hynix Inc
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile

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Abstract

一种半导体器件中的晶体管及其制造方法，能提高其激励速度，通过形成较沟道和LDD区(轻掺染漏区)更厚的结区，可降低结区本身的电阻。

Description

半导体器件中的晶体管及其制造方法
本发明涉及半导体器件中的晶体管及其制造方法，特别是涉及制造半导体器件中的晶体管的一种方法，该方法通过在SOI(绝缘体上的硅)层上形成一多晶硅层，然后在其中注入杂质离子，以形成较沟道和LDD区(轻掺杂漏区)更厚的结区，来改善激励速度。
目前，随着半导体器件的集成度越来越高，SOI晶体管能用作下一代的晶体管。SOI晶体管作为一种器件，其电性能，例如击穿特性和阈值电压，与通常的MOS(金属氧化物半导体)晶体管相比，有了明显的改进。这种SOI晶体管是在SOI晶片上形成的。就SOI晶片的结构看，其中的SOI层(例如下面的硅层)、绝缘层和上面的硅层，其叠置情况是与通常所用的体型(bulk-type)晶片不同的。制造半导体器件中的晶体管的一般方法可参看图1A和图1B来说明。
如图1A所示，SOI晶片20的场区处形成有场氧化膜4。晶片20中以叠层结构形成有一硅层1、一绝缘层2和一SOI层3。在形成场氧化膜4以后，在所形成的构件上相继形成栅氧化膜5和多晶硅层6。然后，使栅氧化膜5和多晶硅膜6成型而形成栅极6A。在栅极6A的两侧，通过注入低浓度的杂质离子在SOI层3中形成LDD区7。接着，如图1B所示，在栅极6A的两侧壁处形成氧化膜衬垫8，然后通过注入高浓度的杂质离子在暴露的SOI层3中形成结区9。在以上述方法制成的SOI晶体管中，所形成的SOI层3较薄，只有500到1500(埃)。因此，由于结区9的深度较浅，其本身内的电阻将增大。结果，晶体管的激励速度减小，于是造成激励特性变坏。
本发明的目的是提供一种半导体器件中的晶体管及其制造方法，其能通过在SOI层中的结区上部上形成一多晶硅层，然后注入杂质离子而形成较沟道和LDD区更厚的结区，来解决上述问题。
按照本发明的晶体管，其结构包括：一场氧化层，形成在SOI晶片的场区上，所述晶片中以叠层结构形成有一硅层、一绝缘层和一SOI层；一栅氧化层，形成在SOI晶片的有源区的选择部分上；一栅极，形成在栅氧化层上；一氧化衬垫，形成在栅极的两侧壁上；和一多晶硅层，形成在场氧化层及SOI层的暴露部分上，其中多晶硅层和多晶硅层下面的SOI层通过注入杂质离子成为第一结区，而氧化衬垫下面的SOI层通过注入杂质离子成为第二结区。
按照本发明制造这种晶体管的方法，包括以下步骤：在一SOI晶片的场区上形成场氧化层，所述晶片中以叠层结构形成有一硅层、一绝缘层和一SOI层；在形成场氧化层后所成的构件上形成第一多晶硅层；使该第一多晶硅层成型而暴露SOI层的一部分；在使第一多晶硅层成型后所成的构件上相继形成一氧化层和第二多晶硅层；通过蚀刻第二多晶硅层的选择部分和氧化层而形成一栅极；在SOI层中形成一LDD区；在栅极的两侧壁上形成一氧化衬垫；以及在第一多晶硅层和第一多晶硅层下面的SOI层中注入杂质离子。
为了更充分了解本发明的特点和目的，以下结合附图更详细地加以说明。附图中：
图1A和图1B是为说明制造半导体器件中晶体管的一般方法的器件剖面图；
图2A至图2E是为说明制造半导体器件中晶体管的本发明方法的器件剖面图。
全部附图中同样的标号表示相同的部分。
以下参看附图详细地说明本发明。
图2A至图2E为器件剖面图，用以说明本发明的制造半导体器件中的晶体管的方法。
图2A为器件的一个剖面图，其中，在一SOI晶片20A的场区形成场氧化膜14之后，在其整个上部相继形成第一多晶硅层15和第一光阻材料16。其中所述SOI晶片20A中以叠层结构形成有硅层10、绝缘层12和SOI层13。第一光阻材料16一侧的将要通过使其成型而形成一个结区的部分保持不变。第一多晶硅层15形成为3000至4000的厚度，而绝缘层12形成有氧化膜。
参看图2B，用第一光阻材料16作为蚀刻掩膜而对第一多晶硅层15进行蚀刻。去除第一光阻材料16，此后在所形成的构件上相继形成门氧化层17、第二多晶硅层18和第二光阻材料19。用一掩膜而使第二光阻材料19成型以供形成栅极之用。由于与SOI层13连接的第一多晶硅层15形成为覆盖了场氧化膜14的一部分，因此有源区的面积增大了。
图2C为器件的一个剖面图，其中，在以成型的第二光阻材料19作为掩膜而相继蚀刻第二多晶硅层18和栅氧化膜17之后，除去第二光阻材料19，于是形成栅极18A。
图2D为器件的一个剖面图，其中，在图2C的状态下，通过第一多晶硅层15与栅极18A之间的缺口注入低浓度的杂质离子而在SOI层13中形成LDD区20。
参看图2E，在形成LDD区20之后所成的构件上形成一氧化膜。通过覆盖-蚀刻该氧化膜而使栅极18A的表面曝光，从而在栅极18A的两侧壁和LDD区20的上部上形成氧化膜衬垫22。然后通过注入高浓度的杂质离子，在第一多晶硅层15和其下面的SOI层13中形成结区21。
因为结区包括了SOI层和多晶硅层，因此按照上述方法制成的SOI晶体管能降低结区的电阻。
按照本发明，如上所述，通过在SOI层上形成多晶硅层和注入杂质离子，从而使形成的结区比沟道和LDD区更厚并使结区的深度加大，因此可降低结区的电阻。另外，本发明有突出的效果，通过增加结区的结的深度和降低结区自身的电阻，可提高晶体管的激励速度。
尽管以上仅描述了具有本发明原理的带有特殊性的一个较佳实施例，但是应当了解，本发明并不限于这一实施例。在本发明的精神和范围内可以作出各种适当的变化，以进一步实施本发明。

Claims (9)

1.一种半导体器件中的晶体管，包括：一场氧化层，形成在SOI晶片的场区上，所述晶片中以叠层结构形成有一硅层、一绝缘层和一SOI层；一栅氧化层，形成在所述SOI晶片的有源区的选择部分上；以及一栅极，形成在所述栅氧化层上；其特征在于还包括：
一氧化衬垫，形成在所述栅极的两侧壁上；和
一多晶硅层，形成在所述场氧化层及所述场氧化层与所述氧化衬垫之间的所述SOI层部分上，其中所述多晶硅层和该多晶硅层下面的SOI层通过注入杂质离子成为第一结区，而所述氧化衬垫下面的所述SOI层通过注入杂质离子成为第二结区。
2.如权利要求1所述的晶体管，其特征在于，所述多晶硅层成型为暴露出所述场氧化层的一部分。
3.如权利要求1所述的晶体管，其特征在于，所述第一结区是通过注入高浓度杂质离子而形成的。
4.如权利要求1所述的晶体管，其特征在于，所述第二结区是通过注入低浓度杂质离子而形成的。
5.一种制造半导体器件中晶体管的方法，其特征在于包括下列步骤：
在一SOI晶片的场区上形成场氧化层，所述晶片中以叠层结构形成有一硅层、一绝缘层和一SOI层；
在形成所述场氧化层后所成的构件上形成第一多晶硅层；
使所述第一多晶硅层成型，从而使该第一多晶硅层处在所述SOI层的至少一部分上且暴露所述SOI层的一部分；
在使所述第一多晶硅层成型后所成的构件上相继形成一氧化层和第二多晶硅层；
通过蚀刻所述第二多晶硅层的选择部分和所述氧化层而形成一栅极；
在所述SOI层中形成一LDD区；
在所述栅极的两侧壁上形成一氧化衬垫；以及
在所述第一多晶硅层和该第一多晶硅层下面的所述SOI层中注入杂质离子。
6.如权利要求5所述的方法，其特征在于，使所述绝缘层形成为一氧化层。
7.如权利要求5所述的方法，其特征在于，使所述SOI层形成有500至1500的厚度。
8.如权利要求5所述的方法，其特征在于，使所述栅极形成有3000至4000的厚度。
9.如权利要求5所述的方法，其特征在于，使所述第一多晶硅层成型以暴露所述SOI层的一部分和所述场氧化层的一部分。
CN96108209A 1995-06-20 1996-06-19 半导体器件中的晶体管及其制造方法 Expired - Fee Related CN1050700C (zh)

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KR970003688A (ko) 1997-01-28
TW302517B (zh) 1997-04-11
JP2951893B2 (ja) 1999-09-20
KR0150105B1 (ko) 1998-12-01
CN1148272A (zh) 1997-04-23
JPH098321A (ja) 1997-01-10

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