CN1146048C - Cmos器件及其制造方法 - Google Patents
Cmos器件及其制造方法 Download PDFInfo
- Publication number
- CN1146048C CN1146048C CNB981239552A CN98123955A CN1146048C CN 1146048 C CN1146048 C CN 1146048C CN B981239552 A CNB981239552 A CN B981239552A CN 98123955 A CN98123955 A CN 98123955A CN 1146048 C CN1146048 C CN 1146048C
- Authority
- CN
- China
- Prior art keywords
- forms
- film
- semiconductor layer
- type impurity
- cmos device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 claims abstract description 74
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 239000012535 impurity Substances 0.000 claims abstract description 34
- 229910052594 sapphire Inorganic materials 0.000 claims abstract description 32
- 239000010980 sapphire Substances 0.000 claims abstract description 32
- 125000006850 spacer group Chemical group 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 20
- 229920005591 polysilicon Polymers 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 230000003647 oxidation Effects 0.000 claims description 14
- 238000007254 oxidation reaction Methods 0.000 claims description 14
- 230000004888 barrier function Effects 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims 4
- 229920002120 photoresistant polymer Polymers 0.000 description 43
- 239000000203 mixture Substances 0.000 description 19
- 239000011248 coating agent Substances 0.000 description 10
- 238000000576 coating method Methods 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 8
- 238000002955 isolation Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000007634 remodeling Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
- H01L21/86—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (20)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR4190/1998 | 1998-02-12 | ||
KR4190/98 | 1998-02-12 | ||
KR1019980004190A KR100331844B1 (ko) | 1998-02-12 | 1998-02-12 | 씨모스소자 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1226085A CN1226085A (zh) | 1999-08-18 |
CN1146048C true CN1146048C (zh) | 2004-04-14 |
Family
ID=19532937
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB981239552A Expired - Fee Related CN1146048C (zh) | 1998-02-12 | 1998-11-06 | Cmos器件及其制造方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US6204100B1 (zh) |
KR (1) | KR100331844B1 (zh) |
CN (1) | CN1146048C (zh) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060105533A1 (en) * | 2004-11-16 | 2006-05-18 | Chong Yung F | Method for engineering hybrid orientation/material semiconductor substrate |
US7999251B2 (en) * | 2006-09-11 | 2011-08-16 | International Business Machines Corporation | Nanowire MOSFET with doped epitaxial contacts for source and drain |
JP5086625B2 (ja) * | 2006-12-15 | 2012-11-28 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
KR100832718B1 (ko) * | 2006-12-27 | 2008-05-28 | 동부일렉트로닉스 주식회사 | 트랜치 게이트 모스 소자 및 그 제조 방법 |
US7598142B2 (en) * | 2007-03-15 | 2009-10-06 | Pushkar Ranade | CMOS device with dual-epi channels and self-aligned contacts |
KR100884450B1 (ko) * | 2007-11-08 | 2009-02-19 | 삼성모바일디스플레이주식회사 | 유기전계발광 표시장치 |
US8872225B2 (en) | 2012-12-20 | 2014-10-28 | Intel Corporation | Defect transferred and lattice mismatched epitaxial film |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4649626A (en) * | 1985-07-24 | 1987-03-17 | Hughes Aircraft Company | Semiconductor on insulator edge doping process using an expanded mask |
US4755481A (en) * | 1986-05-15 | 1988-07-05 | General Electric Company | Method of making a silicon-on-insulator transistor |
US4816893A (en) * | 1987-02-24 | 1989-03-28 | Hughes Aircraft Company | Low leakage CMOS/insulator substrate devices and method of forming the same |
US5116771A (en) * | 1989-03-20 | 1992-05-26 | Massachusetts Institute Of Technology | Thick contacts for ultra-thin silicon on insulator films |
JPH02257668A (ja) * | 1989-03-30 | 1990-10-18 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
US5066613A (en) * | 1989-07-13 | 1991-11-19 | The United States Of America As Represented By The Secretary Of The Navy | Process for making semiconductor-on-insulator device interconnects |
US5362667A (en) * | 1992-07-28 | 1994-11-08 | Harris Corporation | Bonded wafer processing |
US5024965A (en) * | 1990-02-16 | 1991-06-18 | Chang Chen Chi P | Manufacturing high speed low leakage radiation hardened CMOS/SOI devices |
US5416043A (en) * | 1993-07-12 | 1995-05-16 | Peregrine Semiconductor Corporation | Minimum charge FET fabricated on an ultrathin silicon on sapphire wafer |
US5512517A (en) * | 1995-04-25 | 1996-04-30 | International Business Machines Corporation | Self-aligned gate sidewall spacer in a corrugated FET and method of making same |
US5591650A (en) | 1995-06-08 | 1997-01-07 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of making a body contacted SOI MOSFET |
JP3762002B2 (ja) * | 1996-11-29 | 2006-03-29 | 株式会社東芝 | 薄膜トランジスタ、及び液晶表示装置 |
US5864158A (en) * | 1997-04-04 | 1999-01-26 | Advanced Micro Devices, Inc. | Trench-gated vertical CMOS device |
-
1998
- 1998-02-12 KR KR1019980004190A patent/KR100331844B1/ko not_active IP Right Cessation
- 1998-11-06 CN CNB981239552A patent/CN1146048C/zh not_active Expired - Fee Related
-
1999
- 1999-02-12 US US09/249,314 patent/US6204100B1/en not_active Expired - Lifetime
-
2000
- 2000-12-26 US US09/745,555 patent/US6531742B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR100331844B1 (ko) | 2002-05-10 |
US6204100B1 (en) | 2001-03-20 |
KR19990069745A (ko) | 1999-09-06 |
US6531742B2 (en) | 2003-03-11 |
CN1226085A (zh) | 1999-08-18 |
US20010038130A1 (en) | 2001-11-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7384836B2 (en) | Integrated circuit transistor insulating region fabrication method | |
US5523603A (en) | Semiconductor device with reduced time-dependent dielectric failures | |
US5073519A (en) | Method of fabricating a vertical FET device with low gate to drain overlap capacitance | |
US20050227448A1 (en) | High voltage double diffused drain MOS transistor with medium operation voltage | |
US8889518B2 (en) | LDMOS transistor with asymmetric spacer as gate | |
CN1926693A (zh) | 具有多种隔离体绝缘区宽度的集成电路 | |
JPH08222645A (ja) | 軽くドープしたドレイン領域を形成する方法 | |
CN103904116A (zh) | 金属氧化物半导体器件和制作方法 | |
CN100351994C (zh) | 使用反向FinFET薄膜晶体管的FinFET SRAM单元 | |
CN1146048C (zh) | Cmos器件及其制造方法 | |
CN1050700C (zh) | 半导体器件中的晶体管及其制造方法 | |
CN1096114C (zh) | 具有双栅极半导体器件的制造方法 | |
CN1152436C (zh) | 绝缘体基硅场效应晶体管及其形成工艺和绝缘体基硅网络 | |
CN1090383C (zh) | 半导体器件及其制造方法 | |
CN101393893B (zh) | 具有不同侧壁层宽度的cmos器件及其制造方法 | |
CN1091948C (zh) | Mos器件及其制造方法 | |
KR100366829B1 (ko) | 반도체 장치 | |
KR100547400B1 (ko) | 4개이상의트랜지스터를가진회로장치및그제조방법 | |
CN1905212A (zh) | 晶体管及其形成方法 | |
JP4534500B2 (ja) | 半導体装置の製造方法 | |
CN1050701C (zh) | 半导体器件中的晶体管及其制造方法 | |
JP2002305299A (ja) | 半導体装置及びその製造方法 | |
KR100321754B1 (ko) | 모스트랜지스터제조방법 | |
KR100407981B1 (ko) | 반도체소자의구조및제조방법 | |
CN1240122C (zh) | 应用于系统芯片的半导体器件的制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C06 | Publication | ||
PB01 | Publication | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C56 | Change in the name or address of the patentee |
Owner name: HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. Free format text: FORMER NAME OR ADDRESS: LG SEMICON CO., LTD. Owner name: HYNIX SEMICONDUCTOR INC. Free format text: FORMER NAME OR ADDRESS: HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. |
|
CP03 | Change of name, title or address |
Address after: Gyeonggi Do, South Korea Patentee after: HYNIX SEMICONDUCTOR Inc. Address before: Gyeonggi Do, South Korea Patentee before: Hyundai Electronics Industries Co.,Ltd. Address after: Gyeonggi Do, South Korea Patentee after: Hyundai Electronics Industries Co.,Ltd. Address before: North Chungcheong Province Patentee before: LG Semicon Co.,Ltd. |
|
ASS | Succession or assignment of patent right |
Owner name: MAGNACHIP CO., LTD. Free format text: FORMER OWNER: HYNIX SEMICONDUCTOR INC. Effective date: 20070518 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20070518 Address after: North Chungcheong Province Patentee after: Magnachip Semiconductor, Ltd. Address before: Gyeonggi Do, South Korea Patentee before: HYNIX SEMICONDUCTOR Inc. |
|
C19 | Lapse of patent right due to non-payment of the annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |