CN1073280C - 制造ldd结构的mos晶体管的方法 - Google Patents

制造ldd结构的mos晶体管的方法 Download PDF

Info

Publication number
CN1073280C
CN1073280C CN96105548A CN96105548A CN1073280C CN 1073280 C CN1073280 C CN 1073280C CN 96105548 A CN96105548 A CN 96105548A CN 96105548 A CN96105548 A CN 96105548A CN 1073280 C CN1073280 C CN 1073280C
Authority
CN
China
Prior art keywords
foreign ion
type foreign
mos transistor
semiconductor substrate
ion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN96105548A
Other languages
English (en)
Other versions
CN1143830A (zh
Inventor
黄儁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hyundai Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Publication of CN1143830A publication Critical patent/CN1143830A/zh
Application granted granted Critical
Publication of CN1073280C publication Critical patent/CN1073280C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本发明的MOS晶体管具有LDD结构，其特征是，漏是由N-型杂质区或N-/N+杂质区构成，源是由N+型杂质区构成，所以源和漏间的寄生效应是相同的。

Description

制造LDD结构的MOS晶体管的方法
本发明涉及一种制造LDD结构的MOS晶体管的方法，尤其涉及一种制造不对称LDD(轻掺杂漏)结构的MOS晶体管的方法。
通常，在NMOS晶体管的源和漏之间存在着很大差别的寄生效应。源一侧的寄生电阻使有效栅电压有很大程度地减小，但对漏一侧的漏电流却只有很小的影响。因此，由于源和漏间的寄生效应的差别便产生了使VLSI半导体器件的驱动力减弱和热载流子效应增加的问题。
因此，本发明的目的是提供一种制造不对称LDD结构的MOS晶体管的方法，以增加半导体器件的驱动力，减小热载流子效应。
为实现上述目的，制造LDD结构的MOS晶体管的方法包括以下步骤：
通过第一离子注入工艺，将N-型杂质离子注入到在其上形成栅极的半导体基片内；
通过第二离子注入工艺，将N+型杂质离子注入到在其上形成源极的半导体基片区域内；
进行退火工艺，激活已注入到半导体基片内的N+和N-型杂质离子，由此形成由N-型杂质区构成的漏和由N+型杂质区构成的源。
制造LDD结构的MOS晶体管的方法包括以下步骤：
通过第一离子注人工艺，将N-型杂质离子注入到在其上形成栅极的半导体基片内；
通过第二离子注入工艺，将N+型杂质离子注入到在其上形成漏极的半导体基片区域之外的区域内；和
进行退火工艺，激活已注入到半导体基片内的N+和N-型杂质离子，由此形成由N-型杂质区及N+杂质区构成的漏和由N+型杂质区构成的源。
为了充分理解本发明的性质和目的，下面将参照附图对本发明进行详细描述。
图1A～1C是用来解释根据本发明的第一个实施例制造LDD结构的MOS晶体管方法的器件剖面图。
图2A～2C是用来解释根据本发明的第二个实施例制造LDD结构的MOS晶体管方法的器件剖面图。
在各附图中，相同的参考标记代表相同的部件。
下面将参照附图对本发明进行详细描述。
图1A～1C是用来解释根据本发明的第一个实施例制造LDD结构MOS晶体管方法的器件剖面图。
图1A是一器件的剖面图，它表示的是：在半导体基片1上形成场氧化膜2，由常规工艺在半导体基片上形成栅氧化膜3和栅极4，用栅极4作掩膜，由第一离子注入工艺，将N-型杂质离子注入到半导体基片1内。
第一离子注人工艺所用N-型杂质离子是P31，所用P31剂量是1.5E13，所用能量为60KeV。
图1B是一器件的剖面图，它表示的是：形成光刻胶图形5，以在将要形成源的半导体基片1区域上开口，然后，用光刻胶图形5作掩膜，由第二离子注入工艺，将N+型杂质离子注入到半导体基片1内。
第二离子注入工艺所用N+型杂质离子是As75，所用As75剂量为6.0E15，所用能量为60KeV。
图1C是一器件的剖面图，它表示的是：在除去光刻胶图形5后，进行退火工艺，激活已注入到半导体基片1内的N-和N+杂质离子，由此形成由N-型杂质区构成的漏6A和由N+型杂质区构成的源6B。
图2A～2C是用来解释根据本发明的第二个实施例制造LDD结构MOS晶体管方法的器件剖面图。
图2A是一器件的剖面图，它表示的是：在半导体基片1上形成场氧化膜2，由常规工艺在半导体基片上形成栅氧化膜3和栅极4，用栅极4作掩膜，由第一离子注入工艺，将N-型杂质离子注入到半导体基片1内。
第一离子注入工艺所用N-型杂质离子是P31，所用P31剂量为1.5E13，所用能量为60KeV。并且，最好是将具有约为5～10度斜度的N-型杂质离子投射到将要形成LDD的一侧。
图2B是一器件的剖面图，它表示的是：形成光刻胶图形5以覆盖从栅极4到0.1～0.3微米范围的将要形成漏的半导体基片1的区域，用光刻胶图形5作掩膜，由第二离子注入工艺，将N+型杂质离子注入到半导体基片1内。
第二离子注入工艺所用N+型杂质离子是As75，所用As75剂量为6.0E15，所用能量为60KeV。
图2C是一器件的剖面图，它表示的是：在除去光刻胶图形5后，进行退火工艺，激活已注入到半导体基片1内的N-和N+杂质离子，由此形成由N-型杂质区及N+型杂质区构成的漏6A和由N+型杂质区构成的源6B。
N-型杂质区处于栅极4和N+型杂质区之间，其长度为0.1～0.3微米。
如上所述，发明的MOS晶体管具有不对称结构，其中，漏是由N-型杂质区或N-/N+型杂质区构成，源是由N+型杂质区构成。
因此，由于在源和漏间具有相同的寄生效应，不对称结构的MOS晶体管能改善驱动力，并能减小热载流子效应。
尽管上面参照实施例对本发明作了一定程度地说明，但上述说明只是对本发明原理的说明。应该理解到，发明并不限于这里所公开和说明的优选实施例。所以，根据本发明的精神和实质所作的任何变型皆包含在本发明进一步的实施例中。

Claims (2)

1．制造具有LDD结构的MOS晶体管的方法，包括步骤：
通过第一离子注入工艺，向在其上形成有栅电极的半导体衬底注入N型杂质离子；
形成光刻胶图形，以在将要形成源的半导体衬底区域开窗口；
通过第二注入工艺，采用光刻胶图形作为掩膜，向半导体衬底的区域注入N+型杂质离子；和
进行退火处理，以激活注入到半导体衬底中的N+和N-型杂质离子，从而形成由N-型杂质离子组成的漏和由N+型杂质离子组成的源。
2．制造具有LDD结构的MOS晶体管的方法，包括步骤：
通过第一离子注入工艺，向在其上形成有栅电极的半导体衬底注入N-型杂质离子；
形成光刻胶图形，以在将要形成漏的半导体衬底部分开窗口；
通过第二注入工艺，采用光刻胶图形作为掩膜，向半导体衬底的区域注入N+型杂质离子；和
进行退火处理，以激活注入到半导体衬底中的N+和N-型杂质离子，从而形成由N-型杂质离子组成的漏和由N+型杂质离子组成的源。
CN96105548A 1995-03-22 1996-03-22 制造ldd结构的mos晶体管的方法 Expired - Fee Related CN1073280C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR6094/1995 1995-03-22
KR1019950006094A KR100187673B1 (ko) 1995-03-22 1995-03-22 반도체 소자의 제조방법
KR6094/95 1995-03-22

Publications (2)

Publication Number Publication Date
CN1143830A CN1143830A (zh) 1997-02-26
CN1073280C true CN1073280C (zh) 2001-10-17

Family

ID=19410352

Family Applications (1)

Application Number Title Priority Date Filing Date
CN96105548A Expired - Fee Related CN1073280C (zh) 1995-03-22 1996-03-22 制造ldd结构的mos晶体管的方法

Country Status (2)

Country Link
KR (1) KR100187673B1 (zh)
CN (1) CN1073280C (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101414554B (zh) * 2007-10-17 2010-04-14 中芯国际集成电路制造(上海)有限公司 离子注入方法
CN101452853B (zh) * 2007-12-07 2010-09-29 中芯国际集成电路制造(上海)有限公司 Mos晶体管的形成方法
CN101621006B (zh) * 2008-07-03 2011-01-12 中芯国际集成电路制造(上海)有限公司 利用锗预非晶处理来形成p-型轻度掺杂的漏极区的方法
CN101989551B (zh) * 2009-08-06 2012-01-25 中芯国际集成电路制造(上海)有限公司 不对称晶体管的形成方法
CN103247528B (zh) * 2012-02-03 2015-09-02 中芯国际集成电路制造(上海)有限公司 金属氧化物半导体场效应管的制造方法
CN107134409B (zh) * 2016-02-26 2020-07-14 北大方正集团有限公司 晶体管的离子注入方法和晶体管

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0320081A (ja) * 1989-06-16 1991-01-29 Matsushita Electron Corp 半導体集積回路
US5061975A (en) * 1988-02-19 1991-10-29 Mitsubishi Denki Kabushiki Kaisha MOS type field effect transistor having LDD structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5061975A (en) * 1988-02-19 1991-10-29 Mitsubishi Denki Kabushiki Kaisha MOS type field effect transistor having LDD structure
JPH0320081A (ja) * 1989-06-16 1991-01-29 Matsushita Electron Corp 半導体集積回路

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
集成电路制造技术一原理与室践第一版 1987.10.1 庄同曾主编 电子工业出版社 *

Also Published As

Publication number Publication date
KR960035914A (ko) 1996-10-28
CN1143830A (zh) 1997-02-26
KR100187673B1 (ko) 1999-06-01

Similar Documents

Publication Publication Date Title
US6503801B1 (en) Non-uniform channel profile via enhanced diffusion
CN1141509A (zh) 阈值电压稳定的场效应晶体管及其制造方法
CN1073280C (zh) 制造ldd结构的mos晶体管的方法
CN1050700C (zh) 半导体器件中的晶体管及其制造方法
CN1176493A (zh) 半导体集成电路装置及其制造方法
CN1096114C (zh) 具有双栅极半导体器件的制造方法
KR960009229A (ko) 고내압용 모스 트랜지스터 및 그 제조방법
EP0130508A1 (en) Field effect transistor of the vertical MOS type
CN1130806A (zh) 制造具有各种金属氧化物半导体场效应晶体管的半导体器件的方法
US6238975B1 (en) Method for improving electrostatic discharge (ESD) robustness
KR950021537A (ko) 서브 미크론 cmos 프로세스를 위한 고 전압 트랜지스터
CN1527380A (zh) 制造合并逻辑器件的方法
CN1146048C (zh) Cmos器件及其制造方法
CN1050691C (zh) 制造半导体器件的晶体管的方法
CN1309031C (zh) 抑制半导体器件的短沟道效应的方法
JP3030183B2 (ja) 半導体装置及びその製造方法
CN1122315C (zh) 金属氧化物半导体场效应晶体管制造方法
KR940004854A (ko) Ldd mosfet 제조방법
CN1260787C (zh) 高压元件的制造方法
KR940008132A (ko) 접합 캐패시턴스를 줄이는 반도체 소자의 제조방법
KR950004606A (ko) 반도체 장치 및 그 제조방법
KR940004855A (ko) Ldd mosfet 제조방법
KR950012717A (ko) 반도체 소자 제조 방법
KR950026031A (ko) 전력용 반도체 장치 및 그 제조방법
KR970054381A (ko) 반도체 소자의 트랜지스터 제조방법

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20011017

Termination date: 20100322