CN1122315C - 金属氧化物半导体场效应晶体管制造方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 239000012535 impurity Substances 0.000 claims abstract description 20
- 230000005669 field effect Effects 0.000 claims abstract description 4
- 230000003647 oxidation Effects 0.000 claims description 8
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- 230000000694 effects Effects 0.000 description 6
- 230000005684 electric field Effects 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
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- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
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- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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Abstract
一种MOSFET结构及其制造方法，其中不用任何掩模而是用自对准栅掩模，不在源附近形成轻掺杂区。该结构包括：半导体衬底；形成于半导体衬底上的栅氧化膜和栅极；形成于半导体衬底中的第一高浓度杂质区，该区与栅极一侧相邻；形成于半导体衬底中的轻掺杂区，该区与栅极的另一侧相邻，及与轻掺杂区相邻形成的第二高浓度杂质区。
Description
技术领域
本发明涉及一种MOSFET(金属氧化物半导体场效应晶体管)结构及其制造方法，特别涉及一种改进的MOSFET结构及其制造方法，其能够只在漏区形成轻掺杂漏(LDD)。
背景技术
图1示出了常规MOSFET。
如图所示，常规MOSFET包括形成于p型半导体衬底1上表面上的栅氧化膜4和栅极5。此外，n型第一高浓度杂质区3a和n型第二高浓度杂质区3b相对于栅对称地形成。n型第一轻掺杂区2a和n型第二轻掺杂区2b形成于n型第一和第二高浓度杂质区3a和3b区之间，并与n型第一和第二高浓度杂质区3a和3b相邻。这里，n型第一轻掺杂区2a和n型第二轻掺杂区2b由p型半导体衬底1隔开。
下面结合图2A-2E说明常规LDD MOSFET的制造工艺。
首先，如图2a所示，在p型半导体衬底1的上表面上形成栅氧化膜4，并在栅化膜4上形成栅极5。此后，利用栅极5作自对准掩模，在栅极5的左右侧，向半导体衬底1离子注入如1-2×1013原子/cm2的磷等n型杂质，从而形成第一和第二轻掺杂区2a和2b，如图2b所示。然后，如图2C所示，分别在栅极5和p型半导体衬底1的上表面上形成绝缘膜6，并均匀地刻蚀绝缘膜6的整个表面，从而形成侧壁间隔层7，如图2D所示。此后，利用侧壁间隔层7和栅极5作自对准掩模，以约1×1015原子/cm2的剂量，向半导体衬底1中离子注入如As(砷)等n型杂质，从而形成第一高浓度杂质区3a和第二高浓度杂质区3b。
上述LDD结构基本上可以防止MOSFET中的热载流子现象。即，如果MOSFET沟道中形成的电场加速的电子的能量超过禁带能量(1.1eV)，则电子与半导体衬底中的硅晶格碰撞，从而通过上述的碰撞电离过程产生电子空穴对。这里，空穴主要传输到硅衬底中，可以观察到衬底电流。另外，甚至在不超过硅半导体衬底和SiO2栅氧化膜间静电势垒电压的栅电压能量(约3.1eV)时，电子也能传输到栅氧化膜。由于电位的作用一部分电子保留在氧化膜内，这可以增大晶体管的阈值电压Vth，这样便降低了界面部分质量和跨导，上述现象称作热载流子效应。另外，如果器件中的电场高，则沟道中的电子可以直接传输到栅氧化膜。由于高电场会形成热载流子，所以可以通过在具有最高电场的漏附近形成高浓度杂质区来防止热载流子的发生。上述结构称作LDD结构。因此，为防止热载流子效应构成的LDD结构是在漏附近形成轻掺杂区。然而，轻掺杂区最好通过自对准形成。因此，常规LDD结构中，在栅极上形成侧壁间隔层，并分别在源和漏附近形成轻掺杂区。另外，由于在源和漏附近形成轻掺杂区所以形成了浅结，并且该浅结并不能通过延长沟道来防止因沟道缩短造成的短沟道效应，这是因为常规深结会把杂质引入到栅的下表面。但是，形成于源和漏附近的轻掺杂区，可以防止热载流子现象和短沟道效应。然而，与非LDD结构晶体管相比，由于沟道电阻，漏电流和跨导会减小约10-20％。
发明内容
因此，本发明的目的是提供一种MOSFET结构及其制造方法，其克服了现有技术中的上述问题。
本发明另一目的是提供一种改进的MOSFET结构及其制造方法，能够在发生热载流子效应的漏区附近形成轻掺杂区，但不在源区附近形成轻掺杂区。
本发明还有一个目的是提供一种改进的MOSFET结构及其制造方法，其中不另外使用单独的掩模，而利用栅作自对准掩模，在源区附近不形成轻掺杂区。
为了实现上述目的，提供一种MOSFET结构的制造方法，该方法包括以下步骤：依次在半导体衬底上形成栅氧化膜和栅极多晶硅膜；利用栅极掩模构图多晶硅膜，以形成栅极；向栅极两侧的半导体衬底中离子注入轻掺杂杂质，在半导体衬底中形成第一轻掺杂区和第二轻掺杂区；在栅极和半导体衬底的整个表面上形成掩蔽层；构图该掩蔽层，形成局部掩模，覆盖栅极和第二轻掺杂区的一部分；及向掩模两侧的半导体衬底中注入高浓度杂质。
通过以下的说明会更清楚本发明的其它优点、目的和特征。
附图说明
通过以下的详细说明及只是说明性的附图会更充分的理解本发明，但这一切并不是对本发明的限制，其中：
图1是展示常规MOSFET的剖面图；
图2A-2E是展示常规MOSFET制造方法的剖面图；
图3是展示本发明的MOSFET的剖面图；及
图4A-4E是展示本发明的MOSFET制造方法的剖面图。
图3示出了本发明的MOSFET。
具体实施方式
在本发明的MOSFET，栅氧化膜4和栅极5形成于p型半导体衬底上。
源区3a为n型第一高浓度杂质区，漏区3b为第二高浓度杂质区，它们皆形成于半导体衬底中，并相对于栅极5对称，轻掺杂区2b即LDD形成于漏区3b和栅极5之间，与漏区3b相邻。
下面结合图4A-4E说明本发明的MOSFET制造方法。
首先，利用栅极5作自对准掩模，向栅极5两侧的p型半导体衬底1中离子注入如1-2×1013原子/cm2的磷等n型杂质，从而形成轻掺杂区2a和2b。
此后，如图4C所示，在栅极5和p型半导体衬底1的上表面上形成光刻胶膜6。
接着，如图4D所示，通过对光刻胶膜6向着轻掺杂区2b偏移栅极掩模(未示出)，对光刻胶膜6曝光，构图光刻胶膜6，由保留于栅极5和轻掺杂区2b的一部分上的光刻胶膜形成局部掩模7。此后，利用光刻胶膜6的局部掩模7作自对准掩模，以约1×1015原子/cm2的剂量，向半导体衬底1中离子注入As(砷)，从而形成第一高浓度杂质区即源区3a，和第二高浓度杂质区漏区3b，如图4E所示。
如上所述，本发明的MOSFET中，由于只在漏附近形成LDD，所以沟道电阻减小，从而可以增大MOSFET的驱动能力。另外，比起利用侧壁间隔层形成的常规LDD结构，可以简化制造工艺，提高生产率。
尽管为了说明公开了本发明的优选实施例，但本领域的普通技术人员很清楚，本发明可以有各种改型、附加和替换，这些皆不脱离所附权利要求书所限定的范围和精神。
Claims (2)
1.一种金属氧化物半导体场效应晶体管制造方法，包括以下步骤：
在半导体衬底上形成栅氧化膜和多晶硅膜；
利用栅极掩模构图多晶硅膜，以形成栅极；
向栅极两侧的半导体衬底中离子注入轻掺杂杂质，在半导体衬底中形成第一轻掺杂区和第二轻掺杂区；
在栅极和半导体衬底的整个表面上形成掩蔽层；
通过向第二轻掺杂区偏移栅极掩模，构图掩蔽层，形成局部掩模，覆盖栅极和第二轻掺杂区的一部分；及
向局部掩模两侧的半导体衬底中注入高浓度杂质。
2.如权利要求1的方法，其特征在于，掩蔽层是光刻胶膜。
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970009088A KR19980073667A (ko) | 1997-03-18 | 1997-03-18 | 모스 전계효과 트랜지스터(mos fet)구조 및 제조방법 |
| KR9088/1997 | 1997-03-18 | ||
| KR9088/97 | 1997-03-18 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1193817A CN1193817A (zh) | 1998-09-23 |
| CN1122315C true CN1122315C (zh) | 2003-09-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN97116248A Expired - Lifetime CN1122315C (zh) | 1997-03-18 | 1997-08-22 | 金属氧化物半导体场效应晶体管制造方法 |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPH10270695A (zh) |
| KR (1) | KR19980073667A (zh) |
| CN (1) | CN1122315C (zh) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006202810A (ja) * | 2005-01-18 | 2006-08-03 | Sharp Corp | 横型二重拡散型ｍｏｓトランジスタおよびその製造方法 |
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1997
- 1997-03-18 KR KR1019970009088A patent/KR19980073667A/ko not_active Application Discontinuation
- 1997-08-22 CN CN97116248A patent/CN1122315C/zh not_active Expired - Lifetime
- 1997-11-04 JP JP9301441A patent/JPH10270695A/ja active Pending
Also Published As
| Publication number | Publication date |
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| JPH10270695A (ja) | 1998-10-09 |
| KR19980073667A (ko) | 1998-11-05 |
| CN1193817A (zh) | 1998-09-23 |
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