CN1139016C - 用于双数据率定时的时钟等待时间补偿电路 - Google Patents

用于双数据率定时的时钟等待时间补偿电路 Download PDF

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CN1139016C
CN1139016C CNB99107193XA CN99107193A CN1139016C CN 1139016 C CN1139016 C CN 1139016C CN B99107193X A CNB99107193X A CN B99107193XA CN 99107193 A CN99107193 A CN 99107193A CN 1139016 C CN1139016 C CN 1139016C
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circuit
clock
delay
clock signal
lag line
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CN1238485A (zh
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J・-M・多尔图
J·-M·多尔图
楚
A·M·楚
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Siemens AG
International Business Machines Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input

Abstract

提供一种时钟等待时间电路、方法和系统，它使数据按照系统时钟的上升沿和下降沿同步。

Description

用于双数据率定时的时钟等待时间补偿电路
与集成电路有关的数据输出转移以与到该集成电路的系统时钟同步的方式发生，这点是很重要的。所说的集成电路例如存储器(动态随机存取存储器(DRAM)或静态随机存取存储器(SRAM))或者其他定时要求严格的器件。经常用时钟对数据等待时间描述数据输出与系统时钟缺乏同步。
在过去通过应用延迟锁相环(DLL)，已提出等待时间问题，DLL用图1的原理图说明。在DLL中，相位比较器2控制延迟线4，从而使时钟信号CKin和CKout之间的相位差为零。当信号CKin和CKout之间的延迟是K*T时，由延迟线4提供的时间延迟得以稳定，此处T是时钟信号CKin的周期，K是自然数。为清除时钟对数据等待时间，早先的技术方案中通常参考时钟的上升沿操作。对于时钟下降沿的等待时间问题未被提出。因而，这种方案不适宜于双数据率的应用，例如，有关双数据率同步动态随机存取存储器(DDR SDRAM)的应用。存在为双数据率应用固有的时钟对数据等待时间进行补偿的需要。
图1为常规延迟锁相环路(DLL)的原理图。
图2为本发明最佳实施例的原理图的说明。
图3为图2电路工作时的时序图的说明。
参考号数和符号已预先附带。
本发明通过实施两个时钟解决双数据率时钟对数据等待时间问题。两个时钟中，一个由系统时钟的上升边沿触发，另一个由系统时钟下降沿触发。所说的被生成的两个时钟通过共用控制器的延迟线调节相位。
图2是本发明的最佳实施例的原理图的说明，其可由集成电路构成。图2中的电路使来自集成电路的数据输出同输入到集成电路的系统时钟的上升和下降沿同步。这种电路适宜与双数据率一起应用。接收机6接收系统时钟信号CLK，产生两个时钟信号分别为CLK1和CLK2，CLK1和CLK2给入到各自的延迟线4和延迟线5，延迟线4同相位比较器2一起构成延迟锁相环(DLL)。延迟线4可以由有源的或无源的可变阻抗电路构成，或者它能由微型电子计算机、微型控制器或数字信号处理器派生得到。在其最佳实施例中，接收机6包含两个常规的单稳态多谐振荡器电路或单触发电路，一个电路由系统时钟上升沿触发，另一个电路由系统时钟下降沿触发。单稳多谐振荡器电路或单触发电路可如同具有一个稳态的触发器那样来实现。延迟R是滤及接收机6的传播延迟。延迟D是涉及包含驱动器8和或门10的驱动器电路7的传播延迟。延迟元件12经一DLL环(它包括经过元件2、4和12的路径)。通过在环中引入相位延迟τ＝R+D提供补偿。当同步被达到时，输出信号相对于给入时钟的延迟是K*T。于是，进入驱动器电路7的信号相对于输入时钟的延迟是K*T-D，此处D是驱动器电路7的传播延迟。相位比较器2不需要输出相位补偿产生的数据到延迟线4和5，那时由相位比较器2比较输入的相位引起相位比较器2的输入端14上的信息相对于相位比较器2输入端16的信息有K*T的延迟。(在输入端16上的R延迟以及在输入端14上τ+K*T-D＝R+D+K*T-D＝R+K*T)假如这个关系不存在，经来自相位比较器2输出端18的控制信号的作用相位比较器2使延迟线4增加或减小与延迟线4有关的延迟，以便达到在输入端14和16上上述的R延迟条件。延迟线4和5输出在延迟线4和5的输入端上的各自的时移型式的时钟信号(例如CLK1′是CLK1的时移型式，CLK2′是CLK2的时移型式)。包含时钟信号CLK1′和CLK2′相或的逻辑电路产生一个对驱动器8的输入，驱动器8亦接收来输出端数据9的输入，产生数据信号DQ。
图2电路工作时的时序图示于图3。图3中，前述的整数K被假定为1。因为来自输出端18的同样的控制信号被用来控制延迟线4和5(并因为延迟线4和5的各自的结构基本上是相同的)时钟信号CLK1和CLK2之间的延迟保持恒定。此外，假定涉及时钟CLK1和CLK2的伪时钟占空度(按从时钟CLK1的上升沿到时钟CLK2上升沿的时间除以CLK1或CLK2的周期来定义)，由图2电路而被保持等于系统时钟CLK的占空度。该时钟占空度被定义为时钟信号上升时间除以时钟周期。如图3所示，时钟信号CLK1被跟随一个时钟延迟R的系统时钟CLK上升沿所触发，而时钟信号CLK2被系统时钟CLK的下降沿触发。时钟信号CLK1′以这样方式被触发，即使CLK1′上升沿和紧随的系统时钟的上升沿之间的延迟精确地为输出驱动器的延迟D。如从CLK1波形到CLK1′波形的因果关系箭头所示，信号CLK1触发跟随一个延迟时间的信号CLK1′，该延迟时间等于由延迟线4所贡献的时钟延迟。同样，从时钟信号CLK2到时钟信号CLK2′的因果关系箭头说明信号CLK2触发跟随一个延迟时间的信号CLK2′，该延迟时间也等于延迟线5贡献的时间延迟。数据信号DQ包含与此有关的应用数据输出，例如来自DRAM的数据。如图3中的因果关系箭头所示，信号DQ上的数据变化分别由时钟信号CLK1′和CLK2′的上升沿触发。时钟CLK1′和时钟CLK2′的上升沿之间的距离与时钟CLK1的上升沿和时钟CLK2的上升沿之间的距离是相同的。于是，关于时钟CLK1′和CLK2′的伪时钟占空度(定义为从时钟CLK1′的上升沿到时钟CLK2′的上升沿的时间除以CLK1′或CLK2′的周期)由图2的电路保持，使得等于系统时钟CLK的时钟占空度。如此，上述发明能用于使输出数据的传输同步于给定集成电路上系统时钟CLK的上升沿或下降沿。例如，DQ上的变化与系统时钟CLK的上升沿和下降沿同步。该变化定时清楚地由数据选通信号DQS说明，DQS代表如由信号CLK1′和CLK2′引起的那样的在信号DQ上的定时变化的波形。数据选通信号DQS的产生对应于，例如，数据在DDR SDRAM的集成电路引脚上成为有效的时刻。因此，该DQS信号(一个这样的信号涉及多个输出，例如16个输出)能够被控制器用于更准确地设置数据有效窗口，和再同步来自多个集成电路，例如双联机存储器模块的数据。
虽然在此参考最佳实施例以及某些已描述的比较方案对本发明已进行了详细描述，但是要理解到，它仅作为举例说明，不被认为是有局限的意思。还要理解到，本发明的实施例和另外的实施例的许多细节变化对于本专业技术人员来说是明显的，并且可参考本说明书由他们做出。还要预料的是，所有这些变化和另外的实施例都包含在下面权利要求的本发明的精神和真实范围之内。

Claims (5)

1.用于与至少一个集成电路相关联的系统的时钟对数据等待时间补偿电路，包括：
一个接收机，所说的接收机可用来接收系统时钟信号和输出第一时钟信号和第二时钟信号；
延迟电路，包括：用来接收所说第二时钟信号的第一延迟线，用来接收所说第一时钟信号的第二延迟线，和用于从所说第二延迟线引入相位延迟的延迟元件，所说延迟电路从所说第一延迟线、第二延迟线和延迟元件输出时移时钟信号；和
一相位比较器，可用来与在所说的第一和第二时钟信号以及与所说的第一和第二时钟信号相对应的所说的时移信号之间的相移的检测有关地控制所说延迟线电路；
具有一个输出和至少一个输入的逻辑电路，所说的逻辑电路可用来接收来自所说的延迟电路的所说的时移信号；和
一驱动器，该驱动器有连接到所说逻辑电路输出端的第一输入端和可接收数据的第二输入端，所说的驱动器可用来输出所说数据，以使它可与所说的系统时钟的上升沿和下降沿同步。
2.按权利要求1的时钟对数据等待时间补偿电路，其特征在于，所说的接收机包含至少一个单稳态多谐振荡器电路。
3.按权利要求1的数据对时钟等待时间补偿电路，其特征在于，所说延迟电路的所说第一延迟线、第二延迟线和延迟元件由以下电路组成：
可变无源阻抗电路；可变有源阻抗电路；微控制器电路；微型电子计算机电路；数字信号处理电路；或者它们的组合。
4.一种同步的随机存取存储器集成电路芯片，包括时钟等待时间补偿电路，所说时钟等待时间补偿电路包括：
一个接收机，所说的接收机可用来接收一系统时钟信号和输出第一时钟信号和第二时钟信号；
延迟电路，包括：用来接收所说第二时钟信号的第一延迟线，用来接收所说第一时钟信号的第二延迟线，和用于从所说第二延迟线引入相位延迟的延迟元件，所说延迟电路从所说第一延迟线、第二延迟线和延迟元件输出时移时钟信号；和
一相位比较器，可用来与在所说的第一和第二时钟信号以及与所说的第一和第二时钟信号相对应的所说的时移信号之间的相移的检测有关地控制所说延迟线电路；
具有一个输出和至少一个输入的逻辑电路，所说的逻辑电路可用来接收来自所说的延迟电路的所说的时移信号；和
一驱动器，该驱动器有连接到所说逻辑电路输出端的第一输入端和可接收数据的第二输入端，所说的驱动器可用来输出所说数据，以致它可被与所说的系统时钟的上升沿和下降沿同步。
5.一种同步的随机存取存储器系统，包括多个存储器集成电路芯片，所说的多个存储器集成电路芯片包括时钟等待时间补偿电路，所说时钟等待时间补偿电路包括：
一个接收机，所说的接收机可用来接收系统时钟信号和输出第一时钟信号和第二时钟信号；
延迟电路，包括：用来接收所说第二时钟信号的第一延迟线，用来接收所说第一时钟信号的第二延迟线，和用于从所说第二延迟线引入相位延迟的延迟元件，所说延迟电路从所说第一延迟线、第二延迟线和延迟元件输出时移时钟信号；和
一相位比较器，可用来控制所说延迟线电路，与在所说的第一和第二时钟信号以及与所说的第一和第二时钟信号相对应的所说的时移信号之间的相移的检测有关地控制所说延迟线电路；
具有一个输出和至少一个输入的逻辑电路，所说的逻辑电路可用来接收来自所说的延迟电路的所说的时移信号；
一驱动器，该驱动器有连接到所说逻辑电路输出端的第一输入端和可接收数据的第二输入端，所说的驱动器可用来输出所说数据，以致它与所说的系统时钟的上升沿和下降沿同步；并且
包括在每个所说集成电路芯片上的每个补偿电路，可用于产生数据选通信号，所说的存储器系统包括一个控制器，用在同步来自所说的多个集成电路芯片的数据方面。
CNB99107193XA 1998-06-09 1999-06-09 用于双数据率定时的时钟等待时间补偿电路 Expired - Fee Related CN1139016C (zh)

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US09/093,802 US6100733A (en) 1998-06-09 1998-06-09 Clock latency compensation circuit for DDR timing
US09/093802 1998-06-09

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CN1238485A (zh) 1999-12-15
EP0964517B1 (en) 2003-08-27
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EP0964517A3 (en) 2000-04-05
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TW483256B (en) 2002-04-11
US6100733A (en) 2000-08-08

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