CN113574797A - 高频半导体放大器 - Google Patents

高频半导体放大器 Download PDF

Info

Publication number
CN113574797A
CN113574797A CN201980094252.6A CN201980094252A CN113574797A CN 113574797 A CN113574797 A CN 113574797A CN 201980094252 A CN201980094252 A CN 201980094252A CN 113574797 A CN113574797 A CN 113574797A
Authority
CN
China
Prior art keywords
inductor
frequency
matching
transistor
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201980094252.6A
Other languages
English (en)
Other versions
CN113574797B (zh
Inventor
佐佐木善伸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of CN113574797A publication Critical patent/CN113574797A/zh
Application granted granted Critical
Publication of CN113574797B publication Critical patent/CN113574797B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/047—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/60—Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/60—Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
    • H03F3/602—Combinations of several amplifiers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6644—Packaging aspects of high-frequency amplifiers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6644—Packaging aspects of high-frequency amplifiers
    • H01L2223/6655—Matching arrangements, e.g. arrangement of inductive and capacitive components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/1033—Gallium nitride [GaN]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13064—High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Amplifiers (AREA)
  • Microwave Amplifiers (AREA)

Abstract

本发明所涉及的高频半导体放大器具备：晶体管，其形成于半导体基板上，具有栅极电极、源极电极以及漏极电极；晶体管的输入侧基波匹配用的匹配电路；第一电感器，其形成于半导体基板上，一端与晶体管的栅极电极连接，另一端与匹配电路连接；电容，其形成于半导体基板上，一端短路；以及第二电感器，其形成于半导体基板上，一端与晶体管的栅极电极连接，另一端与电容的另一端连接。第二电感器在二倍波的频率下与电容串联谐振，且与第一电感器呈现减极性的互感，并与第一电感器形成输入侧二倍波匹配用互感电路。

Description

高频半导体放大器
技术领域
本发明涉及高频半导体放大器。
背景技术
动作时的低功耗化即高效率化是半导体放大器中的基本课题。作为以超过微波的高频对电力进行放大的高频半导体放大器中的针对该课题的来自电路面的方法之一，有在与半导体所放大的信号的频率(以下，称为基波)的倍数相当的频率(以下，称为高次谐波)下，通过从半导体预估的外围电路的阻抗的控制，来实现高效率动作的方法即所谓的高次谐波处理。这里，在高次谐波中，与基波的二倍的频率相当的二倍波的控制尤为重要。
例如，在专利文献1中公开有如下方法：例如，在半导体芯片上的晶体管的栅极附近，连接由MIM(Metal Insulator Metal)电容器、和由传送线路构成的电感器构成的二倍波谐振电路来控制输入二倍波，由此实现高频半导体放大器的高效率化。
在由传送线路构成电感器的情况下，在晶体管的电极附近占据大的面积。为此，在非专利文献1中公开了如下事例：在实际的半导体制品中，通过由螺旋电感器构成电感器，从而以更小的面积实现所希望的电感，减少半导体芯片的面积，降低成本。
专利文献1：日本特开2013-118329号公报
非专利文献1：2011IEEE MTT-S International Microwave Symposium，”A 67％PAE，100W GaN Power Amplifier with On-Chip Harmonic Tuning Circuits for C-bandSpace Applications”
在图9至图14中示出了应用上述的输入二倍波的控制技术的以往的高频半导体放大器的例子。以往的高频半导体放大器是密封于封装12的移动电话基站用的1级放大器。
此外，在附图中，标注相同附图标记的部分是相同的或与其相当的部分，这在说明书的全文中是通用的。
在图9和图10中示出了以往的高频半导体放大器的剖视图和俯视图。图9是从图10的箭头A观察的以往的高频半导体放大器的剖视图。图10是以往的高频半导体放大器的俯视图。为了表示以往的高频半导体放大器的封装内的安装状况，而在图10中未示出图9中的盖12c。
如图9所示，封装12由金属板12a、绝缘体12b、盖12c以及引线10、14构成。
绝缘体12b是由陶瓷构成的框体，通过钎焊而与金属板12a的上表面接触固定。
引线10以及14由铜合金等薄板形成，通过钎焊而固定于绝缘体12b的上表面。由绝缘体12b以及金属板12a形成的封装的内部，使用粘合剂(未图示)由盖12c密封。盖12c的材料是陶瓷。
引线10是向以往的高频半导体放大器输入高频电力的输入用引线，且兼作栅极偏置端子。引线14是由以往的高频半导体放大器放大的高频电力的输出用引线，且兼作漏极偏置端子。
芯片T1是在SiC(Silicon Carbide)基板的上表面使以GaN(Gallium Nitride)为主材料的半导体层外延生长而成的半导体基板的小片，在芯片T1的上表面形成有具有栅极电极、源极电极以及漏极电极的晶体管(在图9、10中未图示)。该晶体管是高频特性优异的HEMT(High Electron Mobility Transistor)。
芯片P1是形成匹配电路(预匹配用电路)的一部分的以GaAs为主材料的半导体基板的小片，该匹配电路匹配形成于芯片T1的晶体管的输入侧的基波。芯片T1以及芯片P1通过焊锡、导电性粘合剂等接合材料(未图示)固定于金属板12a的上表面，并电连接。
金属板12a起到将搭载于其上表面的芯片T1所产生的热传递至金属板12a的背面的散热板的作用。金属板12a的背面起到以往的高频半导体放大器的接地端子的作用，对芯片T1以及芯片P1施加接地电位。
引线10以及芯片P1通过金属线W11～W15连接。P1以及芯片T1通过金属线W21～W25连接。芯片T1以及引线14通过金属线W31～W35连接。
如图10所示，将输入用的引线10与芯片P1连接的金属线W11至W15，配置为在从上表面观察时大致平行。将芯片P1与芯片T1连接的金属线W21至W25，配置为在从上表面观察时大致平行。将芯片T1与输出用的引线14连接的金属线W31至W35，配置为在从上表面观察时大致平行。
图11是以往的高频半导体放大器的内部的从上表面观察的详细图。在芯片P1的上表面配置有输入侧基波匹配用的匹配电路MC1～MC5。基波匹配电路MC1～MC5具有分别独立的输出侧的接合焊盘，在输入侧具有通用的信号输入用的金属线接合焊盘PP。
晶体管Tr1～Tr5形成于芯片T1的上表面，并形成HEMT单元。此外，本说明书中的HEMT单元是指：表示在晶体管附近将栅极电极相互连接的单位Tr的组。晶体管Tr1～Tr5具有与分别独立的栅极电极相连的接合焊盘、和与漏极电极相连的通用的信号输出用的金属线接合焊盘TT。
在芯片T1的上表面配置有由二倍波匹配用电感器L1～L5、和二倍波匹配用电容C1～C5构成的二倍波短路电路。二倍波匹配用电感器L1～L5的一端与晶体管Tr1～Tr5的栅极连接，另一端与二倍波匹配用电容C1～C5的一端连接。二倍波匹配用电容C1～C5的另一端经由形成于芯片T1的向背面连接的通孔(VIA)而接地。二倍波匹配用电感器L1～L5以及二倍波匹配用电容C1～C5串联连接。
图12是从图11的连接点IN1到OUT1的路径的等效电路。形成于芯片T1上的二倍波匹配用电感器L1和二倍波匹配用电容C1，形成以接近二倍波的频率谐振的二倍波短路电路。上述的高效率化通过将从晶体管的栅极预估的二倍波的阻抗的反射系数的大小大致设为1(全反射)，适当地设定反射系数的相位来实现。
这里，虽然全反射仅在二倍波短路电路因谐振而理想地成为0Ω的情况下实现，但需要备注的是，在实际应用中，若与基波的阻抗相比较，二倍波短路电路的阻抗为1/5以下，则对高效率化具有一定以上的效果。
图13是表示漏极效率的输入二倍波反射相位依赖性的图。在将从晶体管Tr1的栅极电极观察连接点IN1方向的二倍波阻抗的反射系数的大小大致设为1(全反射)的状态下改变反射相位，来模拟图12中的从路径IN1到OUT1的电力放大器的漏极效率。但是，在该模拟中，使从栅极电极观察到的该反射系数的大小和相位理想地变化，不包含图12的二倍波匹配用电感器L1和二倍波匹配用电容C1。
图13的纵轴表示放大器的漏极效率，横轴表示从栅极电极观察信号源侧即连接点IN1方向的二倍波阻抗的反射相位。如图13所示，放大器的漏极效率根据从栅极观察的二倍波反射相位而变化。通常在180°附近表示最大值，在本模拟中，也在170°～190°得到最大效率。
另一方面，实际电路的阻抗具有频率特性。图14是表示以往的高频半导体放大器中的输入侧阻抗的轨迹的图。具体而言，是表示在图12的等效电路中从晶体管Tr1的栅极电极观察连接点IN1的方向的阻抗的频率依赖性的矢量轨迹。
这里，将通过高频半导体放大器要进行电力放大的基波的频带的下限频率设为fl，将上限频率设为fh，将它们的中心频率设为fc。另外，将二倍波频带的下限频率设为2fl(fl的二倍的频率)，将上限频率设为2fh(fh的二倍的频率)，将它们的中心频率设为2fc。在本模拟中，为fl＝3.4GHz、fh＝3.6GHz。
在图14中，虽然以标识符表示基波频带的频率fl、fc、fh下的阻抗，但这些阻抗大致集中在一点。即，表示频率特性小。另一方面，虽然二倍波频带的频率2fl、2fc、2f下的阻抗也用标识符示出，但二倍波的阻抗的轨迹与基波频带相比较，标识符的间隔相当宽。
即，可以知道高次谐波下的阻抗的频率依赖性比基波下的阻抗的频率依赖性大。该扩展脱离了图13所示的能够获得最大效率的范围。
因此，存在不能在作为目标的整个频带内进行高效率动作的课题。
发明内容
本发明所涉及的高频半导体装置具备：晶体管，其形成于半导体基板，具有栅极电极、源极电极以及漏极电极；晶体管的输入侧基波匹配用的匹配电路；第一电感器，其形成于半导体基板上，一端与上述晶体管的栅极电极连接，另一端与上述匹配电路连接；电容，其形成于半导体基板上，一端短路；以及第二电感器，其形成于半导体基板上，一端与晶体管的栅极电极连接，另一端与电容的另一端连接。
第二电感器在二倍波的频率下与电容串联谐振，且与第一电感器呈现减极性的互感，并与第一电感器形成输入侧二倍波匹配用互感电路。
本发明是为了消除上述问题点而做出的，其目的在于提供一种能够以宽的频带进行高效率的电力放大的高频半导体放大器。
附图说明
图1是本发明的实施方式1所涉及的高频半导体放大器的内部的从上表面观察的详细图。
图2是图1的连接点IN1到OUT1的路径的等效电路的图。
图3是用于对本发明的动作进行说明的等效电路图。
图4是表示图2中的基波电路以及二倍波短路电路的阻抗的频率依赖性的图。
图5是表示n的频率依赖性的图。
图6是表示本发明的实施方式1所涉及的高频半导体放大器中的输入侧阻抗的轨迹的图。
图7是本发明的实施方式2所涉及的高频半导体放大器的内部的从上表面观察的详细图。
图8是图7的Tr2附近的放大图。
图9是以往的高频半导体放大器的剖视图。
图10是以往的高频半导体放大器的俯视图。
图11是以往的高频半导体放大器的内部的从上表面观察的详细图。
图12是图11的连接点IN1到OUT1的路径的等效电路。
图13是表示漏极效率的输入二倍波反射相位依赖性的图。
图14是表示以往的高频半导体放大器中的输入侧阻抗的轨迹的图。
具体实施方式
实施方式1
使用图1至图6对本发明的实施方式1所涉及的高频半导体放大器进行说明。以下，参照附图，对本发明的实施方式进行说明。
图1是本发明的实施方式1所涉及的高频半导体放大器的内部的从上表面观察的详细图。与使用图11在先说明的以往的高频半导体放大器的较大的不同在于，具有在芯片T1上呈现相互减极性的互感，并形成输入侧二倍波匹配用互感电路的二倍波匹配用电感器L11～L15、以及基波电路用电感器L21～L25。
与以往的高频半导体放大器相同，芯片T1是在SiC(Silicon Carbide)基板的上表面使以GaN(Gallium Nitride)作为主材料的半导体层外延生长而成的半导体基板的小片。
在芯片T1的上表面形成有具有栅极电极、源极电极以及漏极电极的晶体管Tr1～Tr5。该晶体管是高频特性优异的HEMT(High Electron Mobility Transistor)。即，晶体管Tr1～Tr5是GaN系HEMT。
芯片P1是在GaAs基板上形成有对晶体管Tr1～Tr5的输入侧基波进行匹配的匹配电路(预匹配用电路)的芯片。
基波电路用电感器L21～L25形成于芯片T1上，一端与晶体管Tr1～Tr5的栅极电极连接，另一端经由金属线W21～W25与形成于芯片P1的输入侧基波匹配用的匹配电路MC1～MC5连接。
二倍波匹配用电容C11～C15形成于芯片T1上，一端经由形成于芯片T1的向芯片T1的背面导通的通孔(VIA)而短路。
二倍波匹配用电感器L11～L15形成于芯片T1上，一端与晶体管Tr1～Tr5的栅极电极连接，另一端与电容C11～C15的另一端连接。
即，二倍波匹配用电感器L11～L15、二倍波匹配用电容C11～C15以及VIA串联连接，构成为在大致二倍波的频率下串联谐振，形成二倍波短路电路。
二倍波匹配用电感器L11～L15以及基波电路用电感器L21～L25构成漩涡形状的传送线路亦即螺旋电感器，以能够通过提高每单位面积的电感器而缩小半导体的面积。
二倍波匹配用电感器L11～L15以及基波电路用电感器L21～L25配置为：以使得传送线路在漩涡部分接近的方式重叠漩涡，且从芯片上表面观察时漩涡的卷绕方向相反。
因此，二倍波匹配用电感器L11～L15以及基波电路用电感器L21～L25呈现减极性的互感，而形成输入侧二倍波匹配用互感电路。
图2是从图1的连接点IN1到OUT1的路径的等效电路，且是抽出了本发明的实施方式1所涉及的高频半导体放大器的一部分的图。
如上所述，二倍波匹配用电感器L11与二倍波匹配用电容C11串联连接，二倍波匹配用电容C11的一端接地。二倍波匹配用电感器L11的电感值和二倍波匹配用电容C11的电容值被设定为，以二倍波的频率谐振，并且大致短路。
其中，所谓短路理想的为0Ω，但需要备注的是，在实际应用中，若与基波的阻抗相比，二倍波短路电路的阻抗为1/5以下，则对高效率化具有一定以上的效果。
二倍波匹配用电感器L11以及基波电路用电感器L21形成输入侧二倍波匹配用互感电路。即，配置为在对基波电路用电感器L21和二倍波匹配用电感器L11同时从栅极输入电力的情况下，呈现减极性的互感。
基波电路用电感器L21与金属线W21的一端连接。在金属线W21的另一端连接有分路连接的电容Cp1、和并联连接的电容Cs1以及电阻Rs1。电容Cp1、Cs1以及电阻Rs1形成于芯片P1上，构成匹配电路MC1。电阻Rs1用于提高比基波低的频率下的动作的稳定性，电容Cs1用于降低基波下的电阻值。
电容Cp1、和基波电路用电感器L21以及金属线W21作为针对输入侧的基波的预匹配电路进行动作。封装外部的传输线TL1作为阻抗变换器进行动作。
图3是用于对本发明的动作进行说明的等效电路图。图3(a)是从图1的连接点IN1到OUT1的路径的等效电路，仅简略地示出图2的说明所需的部分。
如上所述，基波电路用电感器L21和二倍波用电感器L11形成输入侧二倍波匹配用互感电路，呈现相互减极性的互感。将其用L11、L21的点表示。
将在二倍波用电感器L11中流动的电流设为i1，将在基波电路用电感器L21中流动的电流设为i2。另外，将L11的电感值设为L(L11)，将L21的电感值设为L(L21)，将互感值设为－M。
图3(b)是将图3(a)置换成没有耦合的电感器的结构时的等效电路图。基波电感器L21a的电感值为L(L21)+M，二倍波电感器L11a的电感值为L(L11)+M，电感器M1的电感值为－M。
从图3(b)可知，在电感器M1中流动有电流i1和电流i2这两者。这里，如图3(c)所示，考虑将电感器M1假想地分割为仅有电流i1流动的电感器M1b、和仅有电流i2流动的电感器M1a。
在图3(c)中，若将电感器L21a与电感器M1a的串联连接设为电感器L21b，将电感器L11a与电感器M1b的串联连接设为电感器L11b，则根据图3(a)与图3(c)的比较可知，图3(c)的L21b、L11b相当于图3(a)的L21、L11。
若将电感器M1a的电感值设为L(M1a)，将电感器LM1b的电感值设为L(M1b)，则由于图3(b)的节点N1和图3(c)的节点N11以及N12为相同的电位，因此L(M1a)、L(M1b)能够使用i1、i2以及M表示如下。
L(M1a)＝－(i1+i2)/i2×M，
L(M1b)＝－(i1+i2)/i1×M。
这里，若设为n＝i2/i1，则之前的L(M1a)、L(M1b)能够使用n表示为
L(M1a)＝－(1+1/n)×M，
L(M1b)＝－(1+n)×M。
那么，由于在基波电感器侧流动的电流i2使用n表示为n×i1，因此图3(c)中的基波电感L21b的电感值L(L21b)能够表示为
L(L21b)＝L(L21a)+L(M1a)＝L(L21)－(1/n)×M，
二倍波电感L11b的电感值L(L11b)能够表示为
L(L11b)＝L(L11a)+L(M1b)＝L(L11)－n×M。
图4是表示从图2中的晶体管Tr1的栅极观察的基波电路以及二倍波短路电路的阻抗的频率依赖性的图。在图中，实线表示基波电路的阻抗，虚线表示二倍波短路电路的阻抗。但是，在基波电路用电感器L21和二倍波匹配用电感器L11具有互感的情况下，无法进行基波电路、二倍波短路电路单独的阻抗计算，因此在设为没有互感的状态下实施计算。因此，与图2虽然略有差异，但能够掌握电路阻抗的概略移动。
图5是表示n的频率依赖性的图。图5(a)是表示n的极坐标上的轨迹的图，图5(b)是表示二倍波频率附近的n的实部的频率特性的图。
在图5(a)中表示fc处的n的位置。若对基波下的从晶体管的栅极向基波匹配电路流动的高频电流、和从晶体管的栅极向二倍波短路电路流动的高频电流进行比较，则如图4所示，二倍波短路电路的阻抗高，几乎没有电流流动，因此n的值大。另外，在基波下，预估基波匹配电路的阻抗为电感性，预估二倍波短路电路的阻抗为电容性，因此n的实部的符号为负。
另一方面，如图4所示，随着频率从基波变高而接近二倍波，电容性的二倍波短路电路的阻抗变低，从晶体管的栅极向二倍波短路电路流动的高频电流增加。二倍波短路电路的阻抗在其谐振频率下最少，若超过二倍波，则成为电感性，绝对值变高。因此，如图5(a)所示，随着频率的上升，n的轨迹从负值通过零附近，向正方向移动。
在二倍波频率附近，如图5(a)所示，几乎没有n的虚部，如图5(b)所示，n的实部相对于频率单调增加。因此，相对于频带的下限(2fl)下的电感L11b，频带的上限(2fh)下的电感L11b变小。因此，L11b和C11的谐振频率在频带的下限(2fl)低，在频带的上限(2fh)高。即，抑制从晶体管的栅极预估的二倍波的阻抗的反射系数的相位变化。此外，这里也为fl＝3.4GHz、fh＝3.6GHz。
图6是表示本发明的实施方式1所涉及的高频半导体放大器中的输入侧阻抗的轨迹的图。可知图6所示的2fl与2fh中的阻抗的间隔比图14所示的2fl与2fh中的阻抗的间隔窄。即，表示二倍波中的阻抗的相位变化接近，能够维持高效率的频带宽。
如上所述，本发明的实施方式1中的半导体装置具备：晶体管Tr1，其形成于半导体基板T1上，具有栅极电极、源极电极以及漏极电极；晶体管Tr1的输入侧基波匹配用的匹配电路MC1；第一电感器L21，其形成于半导体基板T1上，一端与晶体管Tr1的栅极电极连接，另一端与匹配电路MC1连接；电容C11，其形成于半导体基板T1上，一端短路；以及第二电感器L11，其形成于半导体基板T1上，一端与晶体管Tr1的栅极电极连接，另一端与电容C11的另一端连接，第二电感器L11在二倍波的频率下与电容C11串联谐振，与第一电感器L21呈现减极性的互感，形成输入侧二倍波匹配用互感电路。
根据这样的结构，由于将晶体管Tr1的栅极电极和基波匹配用的匹配电路MC1，经由相对于构成谐振电路的第一电感器L21减极性互感的第二电感器L11而连接，因此能够抑制从晶体管Tr1的栅极观察的二倍波阻抗的扩展，起到能够在作为目标的整个频带内进行高效率动作的效果。
此外，在实施方式1中，示出了能够实现所希望的n的电路的一个例子，但只要是能够实现随着频率的增加而从负值向正方向移动的n的电路，就没有电路结构的制约。
实施方式2
使用图7、8对本发明的实施方式2所涉及的高频半导体放大器的结构进行说明。与实施方式1的不同点在于第一电感器以及第二电感器的结构，其他部分是通用的。
在图1所示的实施方式1所涉及的高频半导体放大器中，由二倍波匹配用电感器L11以及基波电路用电感器L21构成的输入侧二倍波匹配用互感电路与栅极馈线布线(gatefeeder)GF1接近。因此，若动作频率变高，则对构成晶体管Tr1的各基本晶体管的影响变得不平衡。
具体而言，在图1中，在从栅极馈线布线GF1与二倍波匹配用电感器L11的连接点观察时的下方向，栅极馈线布线GF1与二倍波匹配用电感器L11的距离接近，而产生耦合。另一方面，在图1中，在从栅极馈线布线GF1与电感器L11的连接点观察时的上方向，栅极馈线布线GF1与二倍波匹配用电感器L11的距离比下方向分离，耦合的影响小。
这样，由于输入侧二倍波匹配用互感电路与各基本晶体管的距离不均匀，因此存在晶体管Tr1的动作变得不平衡，特性降低的问题。
图7是本发明的实施方式2所涉及的高频半导体放大器的内部的从上表面观察的详细图。图8是图7的Tr2附近的放大图。这里，以从连接点IN2到OUT2的路径为例进行说明。
与实施方式1相同，芯片T1是在SiC(Silicon Carbide)基板的上表面使以GaNGallium Nitride)为主材料的半导体层外延生长而成的半导体基板的小片。
在芯片T1的上表面形成有具有栅极电极、源极电极以及漏极电极的晶体管Tr1～Tr5。该晶体管是高频特性优异的HEMT(High Electron Mobility Transistor)。即，晶体管Tr1～Tr5是GaN系HEMT。
二倍波匹配用电容C11～C15形成于芯片T1上。二倍波匹配用电容C1～C6的一端经由形成于芯片T1的向芯片T1的背面导通的通孔(VIA)短路。
晶体管Tr2的栅极电极通过栅极馈线布线GF2相互连接。
二倍波匹配用电感器L121的一端与晶体管Tr2的栅极电极连接，另一端与二倍波匹配用电容C2的另一端连接。二倍波匹配用电感器L121和二倍波匹配用电容C2构成为在大致二倍波的频率下谐振，形成二倍波短路电路。
二倍波匹配用电感器L122的一端与晶体管Tr2的栅极电极连接，另一端与二倍波匹配用电容C3的另一端连接。二倍波匹配用电感器L122和二倍波匹配用电容C3构成为在大致二倍波的频率下谐振，形成二倍波短路电路。
基波电路用电感器L221的一端与晶体管Tr2的栅极电极连接，另一端经由金属线W22而与基波匹配用的匹配电路MC2连接。基波电路用电感器L222的一端与晶体管Tr2的栅极电极连接，另一端经由金属线W22而与基波匹配用的匹配电路MC2连接。
如图7、8所示，二倍波匹配用电感器L121和基波电路用电感器L221以交错的方式相互接近地配置。其配置设计为，从晶体管Tr2的栅极沿着二倍波匹配用电感器L121到C2的路径、和从晶体管Tr2的栅极沿着基波电路用电感器L221到金属线W22的路径在接近部分路径成为相互相反方向。
因此，二倍波匹配用电感器L121和基波电路用电感器L221呈现减极性的互感，形成输入侧二倍波匹配用互感电路。
同样，二倍波匹配用电感器L122和基波电路用电感器L222也呈现减极性的互感，形成输入侧二倍波匹配用互感电路。
在由二倍波匹配用电感器L121以及基波电路用电感器L221构成的输入侧二倍波匹配用互感电路、和由二倍波匹配用电感器L122以及基波电路用电感器L222构成的输入侧二倍波匹配用互感电路中，二倍波匹配用电感器电感器L121与L122连接，基波电路用电感器电感器L221与L222连接。
即，一对输入侧二倍波匹配用互感电路相互连接。另外，由二倍波匹配用电感器L121以及基波电路用电感器L221构成的输入侧二倍波匹配用互感电路、和由二倍波匹配用电感器L122以及基波电路用电感器L222构成的输入侧二倍波匹配用互感电路配置为，相对于在栅极的长度方向上的晶体管Tr2的中心通过并沿栅极的宽度方向延伸的直线B-B’线对称。即，一对输入侧二倍波匹配用互感电路配置为，相对于沿栅极的宽度方向延伸的直线线对称。
二倍波匹配用电感器电感器L121以及L122与栅极馈线布线GF2接近。然而，由于配置为相对于直线B-B’对称，因此与实施方式1相比，各基本晶体管与电感器的距离之差小。因此，与实施方式1相比，能够抑制各基本晶体管间的动作的不平衡，高频半导体放大器的特性提高。其他部分省略说明。
如上所述，本发明的实施方式2所涉及的高频半导体放大器具备：晶体管Tr2，其形成于半导体基板T1上，具有栅极电极、源极电极以及漏极电极；晶体管Tr2的输入侧基波匹配用的匹配电路MC2；第一电感器L221以及L222，其形成于半导体基板T1上，一端与晶体管Tr2的栅极电极连接，另一端与匹配电路MC2连接；以及电容C2以及C3，形成于半导体基板T1上，一端短路。
另外，本发明的实施方式2所涉及的高频半导体放大器具备第二电感器L121，该第二电感器L121形成于半导体基板T1上，一端与晶体管Tr2的栅极电极连接，另一端与电容C2的另一端连接，第二电感器L121在二倍波的频率下与电容C2串联谐振，形成与第一电感器L221呈现减极性互感的输入侧二倍波匹配用互感电路。
并且，本发明的实施方式2所涉及的高频半导体放大器具备第二电感器L122，该第二电感器L122形成于半导体基板T1上，一端与晶体管Tr2的栅极电极连接，另一端与电容C3的另一端连接，第二电感器L122在二倍波的频率下与电容C2串联谐振，形成与第一电感器L222呈现减极性互感的输入侧二倍波匹配用互感电路。
除此之外，在本发明的实施方式2所涉及的高频半导体放大器中，电感器L121与电感器L221相互连接，电感器L122与电感器L222相互连接。电感器L121以及电感器L221配置为相对于沿栅极的宽度方向延伸的直线线对称，电感器L122以及电感器L222配置为相对于沿栅极的宽度方向延伸的直线线对称。即，一对输入侧二倍波匹配用互感电路配置为相对于沿栅极的宽度方向延伸的直线线对称，并且相互连接。
根据这样的结构，与实施方式1所示的高频半导体放大器同样，在实施方式2所涉及的半导体装置中，将晶体管Tr2的栅极电极和基波匹配用的匹配电路MC2，经由相对于构成谐振电路的第一电感器L211以及L212减极性互感的第二电感器L121以及L122连接，因此能够抑制从晶体管Tr2的栅极观察的二倍波阻抗的扩展，起到能够在作为目标的整个频带内进行高效率动作的效果。
并且，在实施方式2所涉及的高频半导体放大器中，将一对输入侧二倍波匹配用互感电路配置为，相对于通过晶体管Tr2的在栅极的长度方向上的中心并沿栅极的宽度方向延伸的直线B-B’线对称。因此，与实施方式1相比，能够缩小各基本晶体管与电感器的距离之差。因此，与实施方式1相比，能够抑制各基本晶体管间的动作的不平衡，起到能够使高频半导体放大器的特性进一步提高的效果。
此外，在本说明书中，在本发明所涉及的高频半导体放大器、或以往的高频半导体放大器整体中，使用从连接点IN1到OUT1的路径、或连接点IN2到OUT2的路径，说明了其动作、结构，但在从连接点Inx到OUTx(x是从1到5中的任一整数)的路径中，其动作、结构也相同。
另外，在本发明的实施方式中，晶体管是形成于SiC基板上的GaN系HEMT，但基板材料也可以是Si等。或者，晶体管也可以由GaAs系、Si系的材料构成，晶体管构造也可以是MOSFET、MESFET、HBT。
本发明能够在发明的范围内，自由地组合各实施方式、对各实施方式进行适当地变形、省略。
附图标记说明
10、14...引线；12...封装；12a...金属板；12b...绝缘体；12c...盖；C1～C5、C11～C15...二倍波匹配用电容；L1～L5、L11～L15、L111～L152...二倍波匹配用电感器；L21～L25、L211～L252...基波电路用电感器；MC1～MC5...匹配电路；T1...芯片；Tr1～Tr5...晶体管；W11～W15、W21～W30、W31～W35...金属线。

Claims (3)

1.一种高频半导体放大器，
所述高频半导体放大器具备：
晶体管，其形成于半导体基板上，具有栅极电极、源极电极以及漏极电极；
所述晶体管的输入侧基波匹配用的匹配电路；
第一电感器，其形成于所述半导体基板上，一端与所述晶体管的栅极电极连接，另一端与所述匹配电路连接；
电容，其形成于所述半导体基板上，一端短路；以及
第二电感器，其形成于所述半导体基板上，一端与所述晶体管的栅极电极连接，另一端与所述电容的另一端连接，
其特征在于，
所述第二电感器在二倍波的频率下与所述电容串联谐振，且与所述第一电感器呈现减极性的互感，并与所述第一电感器形成输入侧二倍波匹配用互感电路。
2.根据权利要求1所述的高频半导体放大器，其特征在于，
所述输入侧二倍波匹配用互感电路配置为相对于沿所述栅极的宽度方向延伸的直线线对称，并相互连接。
3.根据权利要求1或2所述的高频半导体放大器，其特征在于，
所述晶体管为GaN系HEMT。
CN201980094252.6A 2019-03-25 2019-03-25 高频半导体放大器 Active CN113574797B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2019/012471 WO2020194441A1 (ja) 2019-03-25 2019-03-25 高周波半導体増幅器

Publications (2)

Publication Number Publication Date
CN113574797A true CN113574797A (zh) 2021-10-29
CN113574797B CN113574797B (zh) 2023-10-10

Family

ID=72609673

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201980094252.6A Active CN113574797B (zh) 2019-03-25 2019-03-25 高频半导体放大器

Country Status (7)

Country Link
US (1) US11979117B2 (zh)
JP (1) JP6930680B2 (zh)
KR (1) KR102587455B1 (zh)
CN (1) CN113574797B (zh)
DE (1) DE112019007087B4 (zh)
TW (1) TWI727711B (zh)
WO (1) WO2020194441A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004207602A (ja) * 2002-12-26 2004-07-22 Renesas Technology Corp 半導体装置およびその製造方法
JP2005311579A (ja) * 2004-04-20 2005-11-04 Miyoshi Electronics Corp 半導体装置
JP2010245819A (ja) * 2009-04-06 2010-10-28 Panasonic Corp 増幅回路
US20120169423A1 (en) * 2010-06-21 2012-07-05 Tomohide Kamiyama Radio frequency amplifier circuit
JP2013187774A (ja) * 2012-03-08 2013-09-19 Toshiba Corp 高周波半導体増幅器
JP2018142827A (ja) * 2017-02-27 2018-09-13 三菱電機特機システム株式会社 半導体装置および電子機器

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5117203A (en) * 1990-12-13 1992-05-26 General Electric Company Phase stable limiting power amplifier
US5276406A (en) * 1992-02-13 1994-01-04 Trontech, Inc. Low noise wide dynamic range amplifiers
JP3668610B2 (ja) 1998-04-10 2005-07-06 太陽誘電株式会社 高周波電力増幅回路
JP2002171138A (ja) * 2000-12-01 2002-06-14 Nec Corp マイクロ波電力増幅器
JP2006005848A (ja) * 2004-06-21 2006-01-05 Sharp Corp 電力増幅器及び高周波通信装置
JP4743077B2 (ja) 2006-10-23 2011-08-10 三菱電機株式会社 高周波電力増幅器
US8076994B2 (en) * 2007-06-22 2011-12-13 Cree, Inc. RF power transistor packages with internal harmonic frequency reduction and methods of forming RF power transistor packages with internal harmonic frequency reduction
US8659359B2 (en) * 2010-04-22 2014-02-25 Freescale Semiconductor, Inc. RF power transistor circuit
JP2012174996A (ja) 2011-02-23 2012-09-10 Fujitsu Ltd 半導体装置及び半導体装置の製造方法
JP2012257070A (ja) * 2011-06-09 2012-12-27 Nippon Telegr & Teleph Corp <Ntt> トランスインピーダンスアンプ
JP5954974B2 (ja) 2011-12-05 2016-07-20 三菱電機株式会社 高周波増幅器
US9825597B2 (en) * 2015-12-30 2017-11-21 Skyworks Solutions, Inc. Impedance transformation circuit for amplifier
KR101924639B1 (ko) 2016-04-14 2018-12-03 한국전자통신연구원 고주파를 이용하여 무선 신호를 증폭하기 위한 회로
KR101899922B1 (ko) * 2016-04-19 2018-09-18 한국전자통신연구원 저전력 고주파 증폭기
WO2017203571A1 (ja) * 2016-05-23 2017-11-30 三菱電機株式会社 電力増幅器
WO2017208328A1 (ja) * 2016-05-31 2017-12-07 三菱電機株式会社 高周波増幅器
KR102467950B1 (ko) 2016-12-08 2022-11-17 한국전자통신연구원 통신 장치의 임피던스 정합 회로
US10432164B2 (en) 2016-12-08 2019-10-01 Electronics And Telecommunications Research Institute Impedance matching circuit of communication apparatus
US10003311B1 (en) * 2016-12-21 2018-06-19 Infineon Technologies Ag Compact class-F chip and wire matching topology
DE112018007051T5 (de) * 2018-02-09 2020-10-22 Mitsubishi Electric Corporation Verstärker

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004207602A (ja) * 2002-12-26 2004-07-22 Renesas Technology Corp 半導体装置およびその製造方法
JP2005311579A (ja) * 2004-04-20 2005-11-04 Miyoshi Electronics Corp 半導体装置
JP2010245819A (ja) * 2009-04-06 2010-10-28 Panasonic Corp 増幅回路
US20120169423A1 (en) * 2010-06-21 2012-07-05 Tomohide Kamiyama Radio frequency amplifier circuit
JP2013187774A (ja) * 2012-03-08 2013-09-19 Toshiba Corp 高周波半導体増幅器
JP2018142827A (ja) * 2017-02-27 2018-09-13 三菱電機特機システム株式会社 半導体装置および電子機器

Also Published As

Publication number Publication date
TWI727711B (zh) 2021-05-11
KR102587455B1 (ko) 2023-10-10
DE112019007087T5 (de) 2021-12-09
KR20210125553A (ko) 2021-10-18
TW202103439A (zh) 2021-01-16
US20220029591A1 (en) 2022-01-27
DE112019007087B4 (de) 2023-12-28
JPWO2020194441A1 (ja) 2021-09-13
WO2020194441A1 (ja) 2020-10-01
CN113574797B (zh) 2023-10-10
JP6930680B2 (ja) 2021-09-01
US11979117B2 (en) 2024-05-07

Similar Documents

Publication Publication Date Title
US10673386B2 (en) Wideband power amplifiers with harmonic traps
JP5085179B2 (ja) Ｆ級増幅回路
US8717102B2 (en) RF device with compensatory resonator matching topology
EP3692633B1 (en) Rf power amplifier with combined baseband, fundamental and harmonic tuning network
EP2458730A1 (en) Radiofrequency amplifier
CN109889168B (zh) 具有谐波终止电路的放大器装置
JP7074892B2 (ja) 周波数選択インピーダンス整合ネットワークを備えるｒｆパワー増幅器
JP4936965B2 (ja) Ｆ級増幅回路
KR20210052528A (ko) 트랜지스터 레벨 입력 및 출력 고조파 종단들
CN110829988A (zh) 具有宽带阻抗匹配的放大器和其制造方法
EP4113831A1 (en) Multiple-stage doherty power amplifiers implemented with multiple semiconductor technologies
CN111989861B (zh) 高频功率放大器
CN113574797B (zh) 高频半导体放大器
CN115800931A (zh) 使用基带终止的t型匹配拓扑
TWI741782B (zh) 高頻放大器
JP6581477B2 (ja) 増幅器
US11855601B2 (en) High-frequency semiconductor device
JP2021125713A (ja) 高周波半導体装置
CN118057724A (zh) 含提供伪逆f类操作的封装内匹配电路的功率放大器装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant